3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Low-level exception handlers and MMU support
7 * rewritten by Paul Mackerras.
8 * Copyright (C) 1996 Paul Mackerras.
9 * MPC8xx modifications by Dan Malek
10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains low-level support and setup for PowerPC 8xx
13 * embedded processors, including trap and interrupt dispatch.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/init.h>
23 #include <asm/processor.h>
26 #include <asm/cache.h>
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/thread_info.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/ptrace.h>
33 #include <asm/fixmap.h>
34 #include <asm/export.h>
36 /* Macro to make the code more readable. */
37 #ifdef CONFIG_8xx_CPU6
38 #define SPRN_MI_TWC_ADDR 0x2b80
39 #define SPRN_MI_RPN_ADDR 0x2d80
40 #define SPRN_MD_TWC_ADDR 0x3b80
41 #define SPRN_MD_RPN_ADDR 0x3d80
43 #define MTSPR_CPU6(spr, reg, treg) \
44 li treg, spr##_ADDR; \
49 #define MTSPR_CPU6(spr, reg, treg) \
53 /* Macro to test if an address is a kernel address */
54 #if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
55 #define IS_KERNEL(tmp, addr) \
56 andis. tmp, addr, 0x8000 /* Address >= 0x80000000 */
57 #define BRANCH_UNLESS_KERNEL(label) beq label
59 #define IS_KERNEL(tmp, addr) \
60 rlwinm tmp, addr, 16, 16, 31; \
61 cmpli cr0, tmp, PAGE_OFFSET >> 16
62 #define BRANCH_UNLESS_KERNEL(label) blt label
67 * Value for the bits that have fixed value in RPN entries.
68 * Also used for tagging DAR for DTLBerror.
70 #ifdef CONFIG_PPC_16K_PAGES
71 #define RPN_PATTERN (0x00f0 | MD_SPS16K)
73 #define RPN_PATTERN 0x00f0
81 * This port was done on an MBX board with an 860. Right now I only
82 * support an ELF compressed (zImage) boot from EPPC-Bug because the
83 * code there loads up some registers before calling us:
84 * r3: ptr to board info data
85 * r4: initrd_start or if no initrd then 0
86 * r5: initrd_end - unused if r4 is 0
87 * r6: Start of command line string
88 * r7: End of command line string
90 * I decided to use conditional compilation instead of checking PVR and
91 * adding more processor specific branches around code I don't need.
92 * Since this is an embedded processor, I also appreciate any memory
95 * The MPC8xx does not have any BATs, but it supports large page sizes.
96 * We first initialize the MMU to support 8M byte pages, then load one
97 * entry into each of the instruction and data TLBs to map the first
98 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
99 * the "internal" processor registers before MMU_init is called.
105 mr r31,r3 /* save device tree ptr */
107 /* We have to turn on the MMU right away so we get cache modes
112 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
118 ori r0,r0,MSR_DR|MSR_IR
121 ori r0,r0,start_here@l
124 rfi /* enables MMU */
127 * Exception entry code. This code runs with address translation
128 * turned off, i.e. using physical addresses.
129 * We assume sprg3 has the physical address of the current
130 * task's thread_struct.
132 #define EXCEPTION_PROLOG \
133 EXCEPTION_PROLOG_0; \
135 EXCEPTION_PROLOG_1; \
138 #define EXCEPTION_PROLOG_0 \
139 mtspr SPRN_SPRG_SCRATCH0,r10; \
140 mtspr SPRN_SPRG_SCRATCH1,r11
142 #define EXCEPTION_PROLOG_1 \
143 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
144 andi. r11,r11,MSR_PR; \
145 tophys(r11,r1); /* use tophys(r1) if kernel */ \
147 mfspr r11,SPRN_SPRG_THREAD; \
148 lwz r11,THREAD_INFO-THREAD(r11); \
149 addi r11,r11,THREAD_SIZE; \
151 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
154 #define EXCEPTION_PROLOG_2 \
155 stw r10,_CCR(r11); /* save registers */ \
156 stw r12,GPR12(r11); \
158 mfspr r10,SPRN_SPRG_SCRATCH0; \
159 stw r10,GPR10(r11); \
160 mfspr r12,SPRN_SPRG_SCRATCH1; \
161 stw r12,GPR11(r11); \
163 stw r10,_LINK(r11); \
164 mfspr r12,SPRN_SRR0; \
165 mfspr r9,SPRN_SRR1; \
168 tovirt(r1,r11); /* set new kernel sp */ \
169 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
170 MTMSRD(r10); /* (except for mach check in rtas) */ \
172 SAVE_4GPRS(3, r11); \
176 * Exception exit code.
178 #define EXCEPTION_EPILOG_0 \
179 mfspr r10,SPRN_SPRG_SCRATCH0; \
180 mfspr r11,SPRN_SPRG_SCRATCH1
183 * Note: code which follows this uses cr0.eq (set if from kernel),
184 * r11, r12 (SRR0), and r9 (SRR1).
186 * Note2: once we have set r1 we are in a position to take exceptions
187 * again, and we could thus set MSR:RI at that point.
193 #define EXCEPTION(n, label, hdlr, xfer) \
197 addi r3,r1,STACK_FRAME_OVERHEAD; \
200 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
202 stw r10,_TRAP(r11); \
210 #define COPY_EE(d, s) rlwimi d,s,0,16,16
213 #define EXC_XFER_STD(n, hdlr) \
214 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
215 ret_from_except_full)
217 #define EXC_XFER_LITE(n, hdlr) \
218 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
221 #define EXC_XFER_EE(n, hdlr) \
222 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
223 ret_from_except_full)
225 #define EXC_XFER_EE_LITE(n, hdlr) \
226 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
230 EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD)
239 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
242 addi r3,r1,STACK_FRAME_OVERHEAD
243 EXC_XFER_STD(0x200, machine_check_exception)
245 /* Data access exception.
246 * This is "never generated" by the MPC8xx.
251 /* Instruction access exception.
252 * This is "never generated" by the MPC8xx.
257 /* External interrupt */
258 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
260 /* Alignment exception */
267 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
270 addi r3,r1,STACK_FRAME_OVERHEAD
271 EXC_XFER_EE(0x600, alignment_exception)
273 /* Program check exception */
274 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
276 /* No FPU on MPC8xx. This exception is not supposed to happen.
278 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
281 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
283 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
284 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
290 EXC_XFER_EE_LITE(0xc00, DoSyscall)
292 /* Single step - not used on 601 */
293 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
294 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
295 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
297 /* On the MPC8xx, this is a software emulation interrupt. It occurs
298 * for all unimplemented and illegal instructions.
300 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD)
304 * For the MPC8xx, this is a software tablewalk to load the instruction
305 * TLB. The task switch loads the M_TW register with the pointer to the first
307 * If we discover there is no second level table (value is zero) or if there
308 * is an invalid pte, we load that into the TLB, which causes another fault
309 * into the TLB Error interrupt where we can handle such problems.
310 * We have to use the MD_xxx registers for the tablewalk because the
311 * equivalent MI_xxx registers only perform the attribute functions.
314 #ifdef CONFIG_8xx_CPU15
315 #define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \
316 addi tmp, addr, PAGE_SIZE; \
318 addi tmp, addr, -PAGE_SIZE; \
321 #define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr)
325 #if defined(CONFIG_8xx_CPU6) || defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC)
326 mtspr SPRN_SPRG_SCRATCH2, r3
330 /* If we are faulting a kernel address, we have to use the
331 * kernel page tables.
333 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
334 INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10)
335 #if defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC)
336 /* Only modules will cause ITLB Misses as we always
337 * pin the first 8MB of kernel memory */
341 mfspr r11, SPRN_M_TW /* Get level 1 table */
342 #if defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC)
343 BRANCH_UNLESS_KERNEL(3f)
344 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
348 /* Insert level 1 index */
349 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
350 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
352 /* Extract level 2 index */
353 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
354 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
355 lwz r10, 0(r10) /* Get the pte */
357 /* Insert the APG into the TWC from the Linux PTE. */
358 rlwimi r11, r10, 0, 25, 26
359 /* Load the MI_TWC with the attributes for this "segment." */
360 MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */
362 rlwinm r11, r10, 32-11, _PAGE_PRESENT
364 rlwimi r10, r11, 0, _PAGE_PRESENT
366 /* The Linux PTE won't go exactly into the MMU TLB.
367 * Software indicator bits 20-23 and 28 must be clear.
368 * Software indicator bits 24, 25, 26, and 27 must be
369 * set. All other Linux PTE bits control the behavior
372 rlwimi r10, r11, 0, 0x0ff8 /* Set 24-27, clear 20-23,28 */
373 MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */
375 /* Restore registers */
376 #if defined(CONFIG_8xx_CPU6) || defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC)
377 mfspr r3, SPRN_SPRG_SCRATCH2
384 mtspr SPRN_SPRG_SCRATCH2, r3
388 /* If we are faulting a kernel address, we have to use the
389 * kernel page tables.
391 mfspr r10, SPRN_MD_EPN
392 rlwinm r10, r10, 16, 0xfff8
393 cmpli cr0, r10, PAGE_OFFSET@h
394 mfspr r11, SPRN_M_TW /* Get level 1 table */
396 #ifndef CONFIG_PIN_TLB_IMMR
397 cmpli cr0, r10, VIRT_IMMR_BASE@h
400 cmpli cr7, r10, (PAGE_OFFSET + 0x1800000)@h
401 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
402 #ifndef CONFIG_PIN_TLB_IMMR
406 blt cr7, DTLBMissLinear
409 mfspr r10, SPRN_MD_EPN
411 /* Insert level 1 index */
412 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
413 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
415 /* We have a pte table, so load fetch the pte from the table.
417 /* Extract level 2 index */
418 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
419 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
420 lwz r10, 0(r10) /* Get the pte */
422 /* Insert the Guarded flag and APG into the TWC from the Linux PTE.
423 * It is bit 26-27 of both the Linux PTE and the TWC (at least
424 * I got that right :-). It will be better when we can put
425 * this into the Linux pgd/pmd and load it in the operation
428 rlwimi r11, r10, 0, 26, 27
429 /* Insert the WriteThru flag into the TWC from the Linux PTE.
430 * It is bit 25 in the Linux PTE and bit 30 in the TWC
432 rlwimi r11, r10, 32-5, 30, 30
433 MTSPR_CPU6(SPRN_MD_TWC, r11, r3)
435 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
436 * We also need to know if the insn is a load/store, so:
437 * Clear _PAGE_PRESENT and load that which will
438 * trap into DTLB Error with store bit set accordinly.
440 /* PRESENT=0x1, ACCESSED=0x20
441 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
442 * r10 = (r10 & ~PRESENT) | r11;
444 rlwinm r11, r10, 32-11, _PAGE_PRESENT
446 rlwimi r10, r11, 0, _PAGE_PRESENT
447 /* The Linux PTE won't go exactly into the MMU TLB.
448 * Software indicator bits 22 and 28 must be clear.
449 * Software indicator bits 24, 25, 26, and 27 must be
450 * set. All other Linux PTE bits control the behavior
454 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
455 rlwimi r10, r11, 0, 20, 20 /* clear 20 */
456 MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */
458 /* Restore registers */
459 mfspr r3, SPRN_SPRG_SCRATCH2
460 mtspr SPRN_DAR, r11 /* Tag DAR */
465 /* This is an instruction TLB error on the MPC8xx. This could be due
466 * to many reasons, such as executing guarded memory or illegal instruction
467 * addresses. There is nothing to do but handle a big time error fault.
477 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
478 1: EXC_XFER_LITE(0x400, handle_page_fault)
480 /* This is the data TLB error on the MPC8xx. This could be due to
481 * many reasons, including a dirty update to a pte. We bail out to
482 * a higher level function that can handle it.
490 cmpwi cr0, r11, RPN_PATTERN
491 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
492 DARFixed:/* Return from dcbx instruction bug workaround */
501 1: li r10,RPN_PATTERN
502 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
503 /* 0x300 is DataAccess exception, needed by bad_page_fault() */
504 EXC_XFER_LITE(0x300, handle_page_fault)
506 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
507 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
508 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
509 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
510 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
511 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
512 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
514 /* On the MPC8xx, these next four traps are used for development
515 * support of breakpoints and such. Someday I will get around to
518 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
519 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
520 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
521 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
526 * Bottom part of DataStoreTLBMiss handlers for IMMR area and linear RAM.
527 * not enough space in the DataStoreTLBMiss area.
531 /* Set 512k byte guarded page and mark it valid */
532 li r10, MD_PS512K | MD_GUARDED | MD_SVALID
533 MTSPR_CPU6(SPRN_MD_TWC, r10, r11)
534 mfspr r10, SPRN_IMMR /* Get current IMMR */
535 rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */
536 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
537 _PAGE_PRESENT | _PAGE_NO_CACHE
538 MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */
541 mtspr SPRN_DAR, r11 /* Tag DAR */
542 mfspr r3, SPRN_SPRG_SCRATCH2
548 /* Set 8M byte page and mark it valid */
549 li r11, MD_PS8MEG | MD_SVALID
550 MTSPR_CPU6(SPRN_MD_TWC, r11, r3)
551 rlwinm r10, r10, 16, 0x0f800000 /* 8xx supports max 256Mb RAM */
552 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
554 MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */
557 mtspr SPRN_DAR, r11 /* Tag DAR */
558 mfspr r3, SPRN_SPRG_SCRATCH2
562 /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
563 * by decoding the registers used by the dcbx instruction and adding them.
564 * DAR is set to the calculated address.
566 /* define if you don't want to use self modifying code */
567 #define NO_SELF_MODIFYING_CODE
568 FixupDAR:/* Entry point for dcbx workaround. */
569 mtspr SPRN_SPRG_SCRATCH2, r10
570 /* fetch instruction from memory. */
573 mfspr r11, SPRN_M_TW /* Get level 1 table */
574 BRANCH_UNLESS_KERNEL(3f)
575 rlwinm r11, r10, 16, 0xfff8
577 cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
578 /* create physical page address from effective address */
581 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
582 /* Insert level 1 index */
583 3: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
584 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
585 rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */
586 /* Insert level 2 index */
587 rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
588 lwz r11, 0(r11) /* Get the pte */
589 /* concat physical page address(r11) and page offset(r10) */
590 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
592 /* Check if it really is a dcbx instruction. */
593 /* dcbt and dcbtst does not generate DTLB Misses/Errors,
594 * no need to include them here */
595 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
596 rlwinm r10, r10, 0, 21, 5
597 cmpwi cr0, r10, 2028 /* Is dcbz? */
599 cmpwi cr0, r10, 940 /* Is dcbi? */
601 cmpwi cr0, r10, 108 /* Is dcbst? */
602 beq+ 144f /* Fix up store bit! */
603 cmpwi cr0, r10, 172 /* Is dcbf? */
605 cmpwi cr0, r10, 1964 /* Is icbi? */
607 141: mfspr r10,SPRN_SPRG_SCRATCH2
608 b DARFixed /* Nope, go back to normal TLB processing */
610 144: mfspr r10, SPRN_DSISR
611 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
612 mtspr SPRN_DSISR, r10
613 142: /* continue, it was a dcbx, dcbi instruction. */
614 #ifndef NO_SELF_MODIFYING_CODE
615 andis. r10,r11,0x1f /* test if reg RA is r0 */
616 li r10,modified_instr@l
617 dcbtst r0,r10 /* touch for store */
618 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */
619 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */
621 stw r11,0(r10) /* store add/and instruction */
622 dcbf 0,r10 /* flush new instr. to memory. */
623 icbi 0,r10 /* invalidate instr. cache line */
624 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */
625 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */
626 isync /* Wait until new instr is loaded from memory */
628 .space 4 /* this is where the add instr. is stored */
630 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
631 143: mtdar r10 /* store faulting EA in DAR */
632 mfspr r10,SPRN_SPRG_SCRATCH2
633 b DARFixed /* Go back to normal TLB handling */
636 mtdar r10 /* save ctr reg in DAR */
637 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
638 addi r10, r10, 150f@l /* add start of table */
639 mtctr r10 /* load ctr with jump address */
640 xor r10, r10, r10 /* sum starts at zero */
641 bctr /* jump into table */
643 add r10, r10, r0 ;b 151f
644 add r10, r10, r1 ;b 151f
645 add r10, r10, r2 ;b 151f
646 add r10, r10, r3 ;b 151f
647 add r10, r10, r4 ;b 151f
648 add r10, r10, r5 ;b 151f
649 add r10, r10, r6 ;b 151f
650 add r10, r10, r7 ;b 151f
651 add r10, r10, r8 ;b 151f
652 add r10, r10, r9 ;b 151f
653 mtctr r11 ;b 154f /* r10 needs special handling */
654 mtctr r11 ;b 153f /* r11 needs special handling */
655 add r10, r10, r12 ;b 151f
656 add r10, r10, r13 ;b 151f
657 add r10, r10, r14 ;b 151f
658 add r10, r10, r15 ;b 151f
659 add r10, r10, r16 ;b 151f
660 add r10, r10, r17 ;b 151f
661 add r10, r10, r18 ;b 151f
662 add r10, r10, r19 ;b 151f
663 add r10, r10, r20 ;b 151f
664 add r10, r10, r21 ;b 151f
665 add r10, r10, r22 ;b 151f
666 add r10, r10, r23 ;b 151f
667 add r10, r10, r24 ;b 151f
668 add r10, r10, r25 ;b 151f
669 add r10, r10, r26 ;b 151f
670 add r10, r10, r27 ;b 151f
671 add r10, r10, r28 ;b 151f
672 add r10, r10, r29 ;b 151f
673 add r10, r10, r30 ;b 151f
676 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */
677 beq 152f /* if reg RA is zero, don't add it */
678 addi r11, r11, 150b@l /* add start of table */
679 mtctr r11 /* load ctr with jump address */
680 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
681 bctr /* jump into table */
684 mtctr r11 /* restore ctr reg from DAR */
685 mtdar r10 /* save fault EA to DAR */
686 mfspr r10,SPRN_SPRG_SCRATCH2
687 b DARFixed /* Go back to normal TLB handling */
689 /* special handling for r10,r11 since these are modified already */
690 153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
691 add r10, r10, r11 /* add it */
692 mfctr r11 /* restore r11 */
694 154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
695 add r10, r10, r11 /* add it */
696 mfctr r11 /* restore r11 */
701 * This is where the main kernel code starts.
706 ori r2,r2,init_task@l
708 /* ptr to phys current thread */
710 addi r4,r4,THREAD /* init task's THREAD */
711 mtspr SPRN_SPRG_THREAD,r4
714 lis r1,init_thread_union@ha
715 addi r1,r1,init_thread_union@l
717 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
719 bl early_init /* We have to do this with MMU on */
722 * Decide what sort of machine this is and initialize the MMU.
730 * Go back to running unmapped so we can load up new values
731 * and change to using our exception vectors.
732 * On the 8xx, all we have to do is invalidate the TLB to clear
733 * the old 8M byte TLB mappings and load the page table base register.
735 /* The right way to do this would be to track it down through
736 * init's THREAD like the context switch code does, but this is
737 * easier......until someone changes init's static structures.
739 lis r6, swapper_pg_dir@ha
741 #ifdef CONFIG_8xx_CPU6
742 lis r4, cpu6_errata_word@h
743 ori r4, r4, cpu6_errata_word@l
752 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
756 /* Load up the kernel context */
758 SYNC /* Force all PTE updates to finish */
759 tlbia /* Clear all TLB entries */
760 sync /* wait for tlbia/tlbie to finish */
761 TLBSYNC /* ... on all CPUs */
763 /* set up the PTE pointers for the Abatron bdiGDB.
766 lis r5, abatron_pteptrs@h
767 ori r5, r5, abatron_pteptrs@l
768 stw r5, 0xf0(0) /* Must match your Abatron config file */
772 /* Now turn on the MMU for real! */
774 lis r3,start_kernel@h
775 ori r3,r3,start_kernel@l
778 rfi /* enable MMU and jump to start_kernel */
780 /* Set up the initial MMU state so we can do the first level of
781 * kernel initialization. This maps the first 8 MBytes of memory 1:1
782 * virtual to physical. Also, set the cache mode since that is defined
783 * by TLB entries and perform any additional mapping (like of the IMMR).
784 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
785 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by
786 * these mappings is mapped by page tables.
790 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */
791 lis r10, MD_RESETVAL@h
792 #ifndef CONFIG_8xx_COPYBACK
793 oris r10, r10, MD_WTDEF@h
795 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */
797 tlbia /* Invalidate all TLB entries */
798 /* Always pin the first 8 MB ITLB to prevent ITLB
799 misses while mucking around with SRR0/SRR1 in asm
804 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
806 #ifdef CONFIG_PIN_TLB
807 oris r10, r10, MD_RSV4I@h
808 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
811 /* Now map the lower 8 Meg into the ITLB. */
812 lis r8, KERNELBASE@h /* Create vaddr for TLB */
813 ori r8, r8, MI_EVALID /* Mark it valid */
814 mtspr SPRN_MI_EPN, r8
815 li r8, MI_PS8MEG | (2 << 5) /* Set 8M byte page, APG 2 */
816 ori r8, r8, MI_SVALID /* Make it valid */
817 mtspr SPRN_MI_TWC, r8
818 li r8, MI_BOOTINIT /* Create RPN for address 0 */
819 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
821 lis r8, MI_APG_INIT@h /* Set protection modes */
822 ori r8, r8, MI_APG_INIT@l
824 lis r8, MD_APG_INIT@h
825 ori r8, r8, MD_APG_INIT@l
828 /* Map a 512k page for the IMMR to get the processor
829 * internal registers (among other things).
831 #ifdef CONFIG_PIN_TLB_IMMR
833 mtspr SPRN_MD_CTR, r10
835 mfspr r9, 638 /* Get current IMMR */
836 andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */
838 lis r8, VIRT_IMMR_BASE@h /* Create vaddr for TLB */
839 ori r8, r8, MD_EVALID /* Mark it valid */
840 mtspr SPRN_MD_EPN, r8
841 li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */
842 ori r8, r8, MD_SVALID /* Make it valid */
843 mtspr SPRN_MD_TWC, r8
844 mr r8, r9 /* Create paddr for TLB */
845 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
846 mtspr SPRN_MD_RPN, r8
849 /* Since the cache is enabled according to the information we
850 * just loaded into the TLB, invalidate and enable the caches here.
851 * We should probably check/set other modes....later.
854 mtspr SPRN_IC_CST, r8
855 mtspr SPRN_DC_CST, r8
857 mtspr SPRN_IC_CST, r8
858 #ifdef CONFIG_8xx_COPYBACK
859 mtspr SPRN_DC_CST, r8
861 /* For a debug option, I left this here to easily enable
862 * the write through cache mode
865 mtspr SPRN_DC_CST, r8
867 mtspr SPRN_DC_CST, r8
873 * We put a few things here that have to be page-aligned.
874 * This stuff goes at the beginning of the data segment,
875 * which is page-aligned.
880 .globl empty_zero_page
884 EXPORT_SYMBOL(empty_zero_page)
886 .globl swapper_pg_dir
888 .space PGD_TABLE_SIZE
890 /* Room for two PTE table poiners, usually the kernel and current user
891 * pointer to their respective root page table (pgdir).
896 #ifdef CONFIG_8xx_CPU6
897 .globl cpu6_errata_word