1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Adapted for Power Macintosh by Paul Mackerras.
9 * Low-level exception handlers and MMU support
10 * rewritten by Paul Mackerras.
11 * Copyright (C) 1996 Paul Mackerras.
13 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
14 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
16 * This file contains the entry point for the 64-bit kernel along
17 * with some early initialization code common to all 64-bit powerpc
21 #include <linux/linkage.h>
22 #include <linux/threads.h>
23 #include <linux/init.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/head-64.h>
29 #include <asm/asm-offsets.h>
31 #include <asm/cputable.h>
32 #include <asm/setup.h>
33 #include <asm/hvcall.h>
34 #include <asm/thread_info.h>
35 #include <asm/firmware.h>
36 #include <asm/page_64.h>
37 #include <asm/irqflags.h>
38 #include <asm/kvm_book3s_asm.h>
39 #include <asm/ptrace.h>
40 #include <asm/hw_irq.h>
41 #include <asm/cputhreads.h>
42 #include <asm/ppc-opcode.h>
43 #include <asm/feature-fixups.h>
44 #ifdef CONFIG_PPC_BOOK3S
45 #include <asm/exception-64s.h>
47 #include <asm/exception-64e.h>
50 /* The physical memory is laid out such that the secondary processor
51 * spin code sits at 0x0000...0x00ff. On server, the vectors follow
52 * using the layout described in exceptions-64s.S
56 * Entering into this code we make the following assumptions:
58 * For pSeries or server processors:
59 * 1. The MMU is off & open firmware is running in real mode.
60 * 2. The primary CPU enters at __start.
61 * 3. If the RTAS supports "query-cpu-stopped-state", then secondary
62 * CPUs will enter as directed by "start-cpu" RTAS call, which is
63 * generic_secondary_smp_init, with PIR in r3.
64 * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as
65 * directed by the "start-cpu" RTS call, with PIR in r3.
66 * -or- For OPAL entry:
67 * 1. The MMU is off, processor in HV mode.
68 * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base
69 * in r8, and entry in r9 for debugging purposes.
70 * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which
71 * is at generic_secondary_smp_init, with PIR in r3.
73 * For Book3E processors:
74 * 1. The MMU is on running in AS0 in a state defined in ePAPR
75 * 2. The kernel is entered at __start
79 * boot_from_prom and prom_init run at the physical address. Everything
80 * after prom and kexec entry run at the virtual address (PAGE_OFFSET).
81 * Secondaries run at the virtual address from generic_secondary_common_init
85 OPEN_FIXED_SECTION(first_256B, 0x0, 0x100)
86 USE_FIXED_SECTION(first_256B)
88 * Offsets are relative from the start of fixed section, and
89 * first_256B starts at 0. Offsets are a bit easier to use here
90 * than the fixed section entry macros.
94 /* NOP this out unconditionally */
97 b __start_initialization_multiplatform
100 /* Catch branch to 0 in real mode */
103 /* Secondary processors spin on this value until it becomes non-zero.
104 * When non-zero, it contains the real address of the function the cpu
108 .globl __secondary_hold_spinloop
109 __secondary_hold_spinloop:
112 /* Secondary processors write this value with their cpu # */
113 /* after they enter the spin loop immediately below. */
114 .globl __secondary_hold_acknowledge
115 __secondary_hold_acknowledge:
118 #ifdef CONFIG_RELOCATABLE
119 /* This flag is set to 1 by a loader if the kernel should run
120 * at the loaded address instead of the linked address. This
121 * is used by kexec-tools to keep the kdump kernel in the
122 * crash_kernel region. The loader is responsible for
123 * observing the alignment requirement.
126 #ifdef CONFIG_RELOCATABLE_TEST
127 #define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */
129 #define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */
132 /* Do not move this variable as kexec-tools knows about it. */
136 DEFINE_FIXED_SYMBOL(__run_at_load, first_256B)
137 .long RUN_AT_LOAD_DEFAULT
142 * The following code is used to hold secondary processors
143 * in a spin loop after they have entered the kernel, but
144 * before the bulk of the kernel has been relocated. This code
145 * is relocated to physical address 0x60 before prom_init is run.
146 * All of it must fit below the first exception vector at 0x100.
147 * Use .globl here not _GLOBAL because we want __secondary_hold
148 * to be the actual text address, not a descriptor.
150 .globl __secondary_hold
153 #ifndef CONFIG_PPC_BOOK3E_64
156 mtmsrd r24 /* RI on */
158 /* Grab our physical cpu number */
160 /* stash r4 for book3e */
163 /* Tell the master cpu we're here */
164 /* Relocation is off & we are located at an address less */
165 /* than 0x100, so only need to grab low order offset. */
166 std r24,(ABS_ADDR(__secondary_hold_acknowledge, first_256B))(0)
169 /* All secondary cpus wait here until told to start. */
170 100: ld r12,(ABS_ADDR(__secondary_hold_spinloop, first_256B))(0)
174 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
175 #ifdef CONFIG_PPC_BOOK3E_64
181 * it may be the case that other platforms have r4 right to
182 * begin with, this gives us some safety in case it is not
184 #ifdef CONFIG_PPC_BOOK3E_64
189 /* Make sure that patched code is visible */
194 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
196 CLOSE_FIXED_SECTION(first_256B)
199 * On server, we include the exception vectors code here as it
200 * relies on absolute addressing which is only possible within
201 * this compilation unit
203 #ifdef CONFIG_PPC_BOOK3S
204 #include "exceptions-64s.S"
206 OPEN_TEXT_SECTION(0x100)
211 #include "interrupt_64.S"
213 #ifdef CONFIG_PPC_BOOK3E_64
215 * The booting_thread_hwid holds the thread id we want to boot in cpu
216 * hotplug case. It is set by cpu hotplug code, and is invalid by default.
217 * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID]
220 .globl booting_thread_hwid
222 .long INVALID_THREAD_HWID
225 * start a thread in the same core
227 * r3 = the thread physical id
228 * r4 = the entry point where thread starts
230 _GLOBAL(book3e_start_thread)
231 LOAD_REG_IMMEDIATE(r5, MSR_KERNEL)
236 /* If the thread id is invalid, just exit. */
254 * stop a thread in the same core
256 * r3 = the thread physical id
258 _GLOBAL(book3e_stop_thread)
263 /* If the thread id is invalid, just exit. */
272 _GLOBAL(fsl_secondary_thread_init)
275 /* Enable branch prediction */
277 ori r3,r3,BUCSR_INIT@l
282 * Fix PIR to match the linear numbering in the device tree.
284 * On e6500, the reset value of PIR uses the low three bits for
285 * the thread within a core, and the upper bits for the core
286 * number. There are two threads per core, so shift everything
287 * but the low bit right by two bits so that the cpu numbering is
290 * If the old value of BUCSR is non-zero, this thread has run
291 * before. Thus, we assume we are coming from kexec or a similar
292 * scenario, and PIR is already set to the correct value. This
293 * is a bit of a hack, but there are limited opportunities for
294 * getting information into the thread and the alternatives
295 * seemed like they'd be overkill. We can't tell just by looking
296 * at the old PIR value which state it's in, since the same value
297 * could be valid for one thread out of reset and for a different
304 rlwimi r3, r3, 30, 2, 30
309 /* turn on 64-bit mode */
312 /* Book3E initialization */
314 bl book3e_secondary_thread_init
317 b generic_secondary_common_init
319 #endif /* CONFIG_PPC_BOOK3E_64 */
322 * On pSeries and most other platforms, secondary processors spin
323 * in the following code.
324 * At entry, r3 = this processor's number (physical cpu id)
326 * On Book3E, r4 = 1 to indicate that the initial TLB entry for
327 * this core already exists (setup via some other mechanism such
328 * as SCOM before entry).
330 _GLOBAL(generic_secondary_smp_init)
341 /* turn on 64-bit mode */
344 #ifdef CONFIG_PPC_BOOK3E_64
345 /* Book3E initialization */
348 bl book3e_secondary_core_init
349 /* Now NIA and r2 are relocated to PAGE_OFFSET if not already */
351 * After common core init has finished, check if the current thread is the
352 * one we wanted to boot. If not, start the specified thread and stop the
355 LOAD_REG_ADDR(r4, booting_thread_hwid)
357 li r5, INVALID_THREAD_HWID
362 * The value of booting_thread_hwid has been stored in r3,
363 * so make it invalid.
368 * Get the current thread id and check if it is the one we wanted.
369 * If not, start the one specified in booting_thread_hwid and stop
370 * the current thread.
376 /* start the specified thread */
377 LOAD_REG_ADDR(r5, DOTSYM(fsl_secondary_thread_init))
378 bl book3e_start_thread
380 /* stop the current thread */
382 bl book3e_stop_thread
387 /* Now the MMU is off, can branch to our PAGE_OFFSET address */
390 addi r11,r11,(2f - 1b)
398 generic_secondary_common_init:
399 /* Set up a paca value for this processor. Since we have the
400 * physical cpu id in r24, we need to search the pacas to find
401 * which logical id maps to our physical one.
404 b kexec_wait /* wait for next kernel if !SMP */
406 LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */
407 ld r8,0(r8) /* Get base vaddr of array */
408 #if (NR_CPUS == 1) || defined(CONFIG_FORCE_NR_CPUS)
409 LOAD_REG_IMMEDIATE(r7, NR_CPUS)
411 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */
412 lwz r7,0(r7) /* also the max paca allocated */
414 li r5,0 /* logical cpu id */
416 sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */
417 ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */
418 lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
419 cmpw r6,r24 /* Compare to our id */
422 cmpw r5,r7 /* Check if more pacas exist */
425 mr r3,r24 /* not found, copy phys to r3 */
426 b kexec_wait /* next kernel might do better */
429 #ifdef CONFIG_PPC_BOOK3E_64
430 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */
431 mtspr SPRN_SPRG_TLB_EXFRAME,r12
434 /* From now on, r24 is expected to be logical cpuid */
437 /* Create a temp kernel stack for use before relocation is on. */
438 ld r1,PACAEMERGSP(r13)
439 subi r1,r1,STACK_FRAME_MIN_SIZE
441 /* See if we need to call a cpu state restore handler */
442 LOAD_REG_ADDR(r23, cur_cpu_spec)
444 ld r12,CPU_SPEC_RESTORE(r23)
447 #ifdef CONFIG_PPC64_ELF_ABI_V1
453 3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */
461 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
464 beq 4b /* Loop until told to go */
466 sync /* order paca.run and cur_cpu_spec */
467 isync /* In case code patching happened */
474 * Assumes we're mapped EA == RA if the MMU is on.
476 #ifdef CONFIG_PPC_BOOK3S
477 SYM_FUNC_START_LOCAL(__mmu_off)
479 andi. r0,r3,MSR_IR|MSR_DR
487 b . /* prevent speculative execution */
488 SYM_FUNC_END(__mmu_off)
490 SYM_FUNC_START_LOCAL(start_initialization_book3s)
493 /* Setup some critical 970 SPRs before switching MMU off */
496 cmpwi r0,0x39 /* 970 */
498 cmpwi r0,0x3c /* 970FX */
500 cmpwi r0,0x44 /* 970MP */
502 cmpwi r0,0x45 /* 970GX */
504 1: bl __cpu_preinit_ppc970
507 /* Switch off MMU if not already off */
510 /* Now the MMU is off, can return to our PAGE_OFFSET address */
514 SYM_FUNC_END(start_initialization_book3s)
518 * Here is our main kernel entry point. We support currently 2 kind of entries
519 * depending on the value of r5.
521 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
524 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
525 * DT block, r4 is a physical pointer to the kernel itself
528 __start_initialization_multiplatform:
529 /* Make sure we are running in 64 bits mode */
532 /* Zero r13 (paca) so early program check / mce don't use it */
539 * Are we booted from a PROM Of-type client-interface ?
543 b __boot_from_prom /* yes -> prom */
545 /* Save parameters */
548 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
549 /* Save OPAL entry */
554 /* Get TOC pointer (current runtime address) */
557 /* These functions return to the virtual (PAGE_OFFSET) address */
558 #ifdef CONFIG_PPC_BOOK3E_64
559 bl start_initialization_book3e
561 bl start_initialization_book3s
562 #endif /* CONFIG_PPC_BOOK3E_64 */
564 /* Get TOC pointer, virtual */
567 /* find out where we are now */
569 /* OPAL doesn't pass base address in r4, have to derive it. */
571 0: mflr r26 /* r26 = runtime addr here */
572 addis r26,r26,(_stext - 0b)@ha
573 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
579 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
580 /* Get TOC pointer, non-virtual */
583 /* find out where we are now */
585 0: mflr r26 /* r26 = runtime addr here */
586 addis r26,r26,(_stext - 0b)@ha
587 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
589 /* Save parameters */
597 * Align the stack to 16-byte boundary
598 * Depending on the size and layout of the ELF sections in the initial
599 * boot binary, the stack pointer may be unaligned on PowerMac
603 #ifdef CONFIG_RELOCATABLE
604 /* Relocate code for where we are now */
609 /* Restore parameters */
616 /* Do all of the interaction with OF client interface */
619 #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
621 /* We never return. We also hit that trap if trying to boot
622 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
627 #ifdef CONFIG_RELOCATABLE
628 /* process relocations for the final address of the kernel */
629 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
630 cmplwi cr0,r7,1 /* flagged to stay where we are ? */
631 mr r25,r26 /* then use current kernel base */
633 LOAD_REG_IMMEDIATE(r25, PAGE_OFFSET) /* else use static kernel base */
636 #if defined(CONFIG_PPC_BOOK3E_64)
637 /* IVPR needs to be set after relocation. */
643 * We need to run with _stext at physical address PHYSICAL_START.
644 * This will leave some code in the first 256B of
645 * real memory, which are reserved for software use.
647 * Note: This process overwrites the OF exception vectors.
649 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET)
650 mr. r4,r26 /* In some cases the loader may */
651 beq 9f /* have already put us at zero */
652 li r6,0x100 /* Start offset, the first 0x100 */
653 /* bytes were copied earlier. */
655 #ifdef CONFIG_RELOCATABLE
657 * Check if the kernel has to be running as relocatable kernel based on the
658 * variable __run_at_load, if it is set the kernel is treated as relocatable
659 * kernel, otherwise it will be moved to PHYSICAL_START
661 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
665 #ifdef CONFIG_PPC_BOOK3E_64
666 LOAD_REG_ADDR(r5, __end_interrupts)
667 LOAD_REG_ADDR(r11, _stext)
670 /* just copy interrupts */
671 LOAD_REG_IMMEDIATE_SYM(r5, r11, FIXED_SYMBOL_ABS_ADDR(__end_interrupts))
676 /* # bytes of memory to copy */
677 lis r5,(ABS_ADDR(copy_to_here, text))@ha
678 addi r5,r5,(ABS_ADDR(copy_to_here, text))@l
680 bl copy_and_flush /* copy the first n bytes */
681 /* this includes the code being */
683 /* Jump to the copy of this code that we just made */
684 addis r8,r3,(ABS_ADDR(4f, text))@ha
685 addi r12,r8,(ABS_ADDR(4f, text))@l
690 p_end: .8byte _end - copy_to_here
694 * Now copy the rest of the kernel up to _end, add
695 * _end - copy_to_here to the copy limit and run again.
697 addis r8,r26,(ABS_ADDR(p_end, text))@ha
698 ld r8,(ABS_ADDR(p_end, text))@l(r8)
700 5: bl copy_and_flush /* copy the rest */
702 9: b start_here_multiplatform
705 * Copy routine used to copy the kernel to start at physical address 0
706 * and flush and invalidate the caches as needed.
707 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
708 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
710 * Note: this routine *only* clobbers r0, r6 and lr
712 _GLOBAL(copy_and_flush)
715 4: li r0,8 /* Use the smallest common */
716 /* denominator cache line */
717 /* size. This results in */
718 /* extra cache line flushes */
719 /* but operation is correct. */
720 /* Can't get cache line size */
721 /* from NACA as it is being */
724 mtctr r0 /* put # words/line in ctr */
725 3: addi r6,r6,8 /* copy a cache line */
729 dcbst r6,r3 /* write it to memory */
731 icbi r6,r3 /* flush the icache line */
740 _ASM_NOKPROBE_SYMBOL(copy_and_flush); /* Called in real mode */
746 #ifdef CONFIG_PPC_PMAC
748 * On PowerMac, secondary processors starts from the reset vector, which
749 * is temporarily turned into a call to one of the functions below.
754 .globl __secondary_start_pmac_0
755 __secondary_start_pmac_0:
756 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
766 _GLOBAL(pmac_secondary_start)
767 /* turn on 64-bit mode */
772 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
779 /* Branch to our PAGE_OFFSET address */
782 addi r11,r11,(2f - 1b)
789 /* Copy some CPU settings from CPU 0 */
790 bl __restore_cpu_ppc970
792 /* pSeries do that early though I don't think we really need it */
795 mtmsrd r3 /* RI on */
797 /* Set up a paca value for this processor. */
798 LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */
799 ld r4,0(r4) /* Get base vaddr of paca_ptrs array */
800 sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */
801 ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */
802 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/
804 /* Mark interrupts soft and hard disabled (they might be enabled
805 * in the PACA when doing hotplug)
808 stb r0,PACAIRQSOFTMASK(r13)
809 li r0,PACA_IRQ_HARD_DIS
810 stb r0,PACAIRQHAPPENED(r13)
812 /* Create a temp kernel stack for use before relocation is on. */
813 ld r1,PACAEMERGSP(r13)
814 subi r1,r1,STACK_FRAME_MIN_SIZE
818 #endif /* CONFIG_PPC_PMAC */
821 * This function is called after the master CPU has released the
822 * secondary processors. The execution environment is relocation off.
823 * The paca for this processor has the following fields initialized at
825 * 1. Processor number
826 * 2. Segment table pointer (virtual address)
827 * On entry the following are set:
828 * r1 = stack pointer (real addr of temp stack)
829 * r24 = cpu# (in Linux terms)
830 * r13 = paca virtual address
831 * SPRG_PACA = paca virtual address
836 .globl __secondary_start
838 /* Set thread priority to MEDIUM */
842 * Do early setup for this CPU, in particular initialising the MMU so we
843 * can turn it on below. This is a call to C, which is OK, we're still
844 * running on the emergency stack.
846 bl CFUNC(early_setup_secondary)
849 * The primary has initialized our kernel stack for us in the paca, grab
850 * it and put it in r1. We must *not* use it until we turn on the MMU
851 * below, because it may not be inside the RMO.
853 ld r1, PACAKSAVE(r13)
855 /* Clear backchain so we get nice backtraces */
859 /* Mark interrupts soft and hard disabled (they might be enabled
860 * in the PACA when doing hotplug)
863 stb r7,PACAIRQSOFTMASK(r13)
864 li r0,PACA_IRQ_HARD_DIS
865 stb r0,PACAIRQHAPPENED(r13)
867 /* enable MMU and jump to start_secondary */
868 LOAD_REG_ADDR(r3, start_secondary_prolog)
869 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
874 b . /* prevent speculative execution */
877 * Running with relocation on at this point. All we want to do is
878 * zero the stack back-chain pointer and get the TOC virtual address
879 * before going into C code.
881 start_secondary_prolog:
884 std r3,0(r1) /* Zero the stack frame pointer */
885 bl CFUNC(start_secondary)
888 * Reset stack pointer and call start_secondary
889 * to continue with online operation when woken up
890 * from cede in cpu offline.
892 _GLOBAL(start_secondary_resume)
893 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
895 std r3,0(r1) /* Zero the stack frame pointer */
896 bl CFUNC(start_secondary)
901 * This subroutine clobbers r11 and r12
903 SYM_FUNC_START_LOCAL(enable_64b_mode)
904 mfmsr r11 /* grab the current MSR */
905 #ifdef CONFIG_PPC_BOOK3E_64
906 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */
908 #else /* CONFIG_PPC_BOOK3E_64 */
909 LOAD_REG_IMMEDIATE(r12, MSR_64BIT)
915 SYM_FUNC_END(enable_64b_mode)
918 * This puts the TOC pointer into r2, offset by 0x8000 (as expected
919 * by the toolchain). It computes the correct value for wherever we
920 * are running at the moment, using position-independent code.
922 * Note: The compiler constructs pointers using offsets from the
923 * TOC in -mcmodel=medium mode. After we relocate to 0 but before
924 * the MMU is on we need our TOC to be a virtual address otherwise
925 * these pointers will be real addresses which may get stored and
926 * accessed later with the MMU on. We branch to the virtual address
927 * while still in real mode then call relative_toc again to handle
930 _GLOBAL(relative_toc)
931 #ifdef CONFIG_PPC_KERNEL_PCREL
938 ld r2,(p_toc - 0b)(r11)
944 p_toc: .8byte .TOC. - 0b
948 * This is where the main kernel code starts.
951 start_here_multiplatform:
952 /* Adjust TOC for moved kernel. Could adjust when moving it instead. */
955 /* Clear out the BSS. It may have been done in prom_init,
956 * already but that's irrelevant since prom_init will soon
957 * be detached from the kernel completely. Besides, we need
958 * to clear it now for kexec-style entry.
960 LOAD_REG_ADDR(r11,__bss_stop)
961 LOAD_REG_ADDR(r8,__bss_start)
962 sub r11,r11,r8 /* bss size */
963 addi r11,r11,7 /* round up to an even double word */
964 srdi. r11,r11,3 /* shift right by 3 */
968 mtctr r11 /* zero this many doublewords */
973 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
974 /* Setup OPAL entry */
975 LOAD_REG_ADDR(r11, opal)
980 #ifndef CONFIG_PPC_BOOK3E_64
983 mtmsrd r6 /* RI on */
986 #ifdef CONFIG_RELOCATABLE
987 /* Save the physical address we're running at in kernstart_addr */
988 LOAD_REG_ADDR(r4, kernstart_addr)
993 /* set up a stack pointer */
994 LOAD_REG_ADDR(r3,init_thread_union)
995 LOAD_REG_IMMEDIATE(r1,THREAD_SIZE)
998 stdu r0,-STACK_FRAME_MIN_SIZE(r1)
1001 * Do very early kernel initializations, including initial hash table
1002 * and SLB setup before we turn on relocation.
1006 bl CFUNC(kasan_early_init)
1008 /* Restore parameters passed from prom_init/kexec */
1010 LOAD_REG_ADDR(r12, DOTSYM(early_setup))
1012 bctrl /* also sets r13 and SPRG_PACA */
1014 LOAD_REG_ADDR(r3, start_here_common)
1019 b . /* prevent speculative execution */
1021 /* This is where all platforms converge execution */
1024 /* relocation is on at this point */
1025 std r1,PACAKSAVE(r13)
1027 /* Load the TOC (virtual address) */
1030 /* Mark interrupts soft and hard disabled (they might be enabled
1031 * in the PACA when doing hotplug)
1034 stb r0,PACAIRQSOFTMASK(r13)
1035 li r0,PACA_IRQ_HARD_DIS
1036 stb r0,PACAIRQHAPPENED(r13)
1038 /* Generic kernel entry */
1039 bl CFUNC(start_kernel)
1043 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0