1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Adapted for Power Macintosh by Paul Mackerras.
9 * Low-level exception handlers and MMU support
10 * rewritten by Paul Mackerras.
11 * Copyright (C) 1996 Paul Mackerras.
13 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
14 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
16 * This file contains the entry point for the 64-bit kernel along
17 * with some early initialization code common to all 64-bit powerpc
21 #include <linux/threads.h>
22 #include <linux/init.h>
26 #include <asm/ppc_asm.h>
27 #include <asm/head-64.h>
28 #include <asm/asm-offsets.h>
30 #include <asm/cputable.h>
31 #include <asm/setup.h>
32 #include <asm/hvcall.h>
33 #include <asm/thread_info.h>
34 #include <asm/firmware.h>
35 #include <asm/page_64.h>
36 #include <asm/irqflags.h>
37 #include <asm/kvm_book3s_asm.h>
38 #include <asm/ptrace.h>
39 #include <asm/hw_irq.h>
40 #include <asm/cputhreads.h>
41 #include <asm/ppc-opcode.h>
42 #include <asm/export.h>
43 #include <asm/feature-fixups.h>
44 #ifdef CONFIG_PPC_BOOK3S
45 #include <asm/exception-64s.h>
47 #include <asm/exception-64e.h>
50 /* The physical memory is laid out such that the secondary processor
51 * spin code sits at 0x0000...0x00ff. On server, the vectors follow
52 * using the layout described in exceptions-64s.S
56 * Entering into this code we make the following assumptions:
58 * For pSeries or server processors:
59 * 1. The MMU is off & open firmware is running in real mode.
60 * 2. The primary CPU enters at __start.
61 * 3. If the RTAS supports "query-cpu-stopped-state", then secondary
62 * CPUs will enter as directed by "start-cpu" RTAS call, which is
63 * generic_secondary_smp_init, with PIR in r3.
64 * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as
65 * directed by the "start-cpu" RTS call, with PIR in r3.
66 * -or- For OPAL entry:
67 * 1. The MMU is off, processor in HV mode.
68 * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base
69 * in r8, and entry in r9 for debugging purposes.
70 * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which
71 * is at generic_secondary_smp_init, with PIR in r3.
73 * For Book3E processors:
74 * 1. The MMU is on running in AS0 in a state defined in ePAPR
75 * 2. The kernel is entered at __start
78 OPEN_FIXED_SECTION(first_256B, 0x0, 0x100)
79 USE_FIXED_SECTION(first_256B)
81 * Offsets are relative from the start of fixed section, and
82 * first_256B starts at 0. Offsets are a bit easier to use here
83 * than the fixed section entry macros.
87 /* NOP this out unconditionally */
90 b __start_initialization_multiplatform
93 /* Catch branch to 0 in real mode */
96 /* Secondary processors spin on this value until it becomes non-zero.
97 * When non-zero, it contains the real address of the function the cpu
101 .globl __secondary_hold_spinloop
102 __secondary_hold_spinloop:
105 /* Secondary processors write this value with their cpu # */
106 /* after they enter the spin loop immediately below. */
107 .globl __secondary_hold_acknowledge
108 __secondary_hold_acknowledge:
111 #ifdef CONFIG_RELOCATABLE
112 /* This flag is set to 1 by a loader if the kernel should run
113 * at the loaded address instead of the linked address. This
114 * is used by kexec-tools to keep the the kdump kernel in the
115 * crash_kernel region. The loader is responsible for
116 * observing the alignment requirement.
119 #ifdef CONFIG_RELOCATABLE_TEST
120 #define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */
122 #define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */
125 /* Do not move this variable as kexec-tools knows about it. */
129 DEFINE_FIXED_SYMBOL(__run_at_load)
130 .long RUN_AT_LOAD_DEFAULT
135 * The following code is used to hold secondary processors
136 * in a spin loop after they have entered the kernel, but
137 * before the bulk of the kernel has been relocated. This code
138 * is relocated to physical address 0x60 before prom_init is run.
139 * All of it must fit below the first exception vector at 0x100.
140 * Use .globl here not _GLOBAL because we want __secondary_hold
141 * to be the actual text address, not a descriptor.
143 .globl __secondary_hold
146 #ifndef CONFIG_PPC_BOOK3E
149 mtmsrd r24 /* RI on */
151 /* Grab our physical cpu number */
153 /* stash r4 for book3e */
156 /* Tell the master cpu we're here */
157 /* Relocation is off & we are located at an address less */
158 /* than 0x100, so only need to grab low order offset. */
159 std r24,(ABS_ADDR(__secondary_hold_acknowledge))(0)
163 #ifdef CONFIG_PPC_BOOK3E
166 /* All secondary cpus wait here until told to start. */
167 100: ld r12,(ABS_ADDR(__secondary_hold_spinloop))(r26)
171 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
172 #ifdef CONFIG_PPC_BOOK3E
178 * it may be the case that other platforms have r4 right to
179 * begin with, this gives us some safety in case it is not
181 #ifdef CONFIG_PPC_BOOK3E
186 /* Make sure that patched code is visible */
191 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
193 CLOSE_FIXED_SECTION(first_256B)
195 /* This value is used to mark exception frames on the stack. */
197 /* This value is used to mark exception frames on the stack. */
199 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
203 * On server, we include the exception vectors code here as it
204 * relies on absolute addressing which is only possible within
205 * this compilation unit
207 #ifdef CONFIG_PPC_BOOK3S
208 #include "exceptions-64s.S"
210 OPEN_TEXT_SECTION(0x100)
215 #include "interrupt_64.S"
217 #ifdef CONFIG_PPC_BOOK3E
219 * The booting_thread_hwid holds the thread id we want to boot in cpu
220 * hotplug case. It is set by cpu hotplug code, and is invalid by default.
221 * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID]
224 .globl booting_thread_hwid
226 .long INVALID_THREAD_HWID
229 * start a thread in the same core
231 * r3 = the thread physical id
232 * r4 = the entry point where thread starts
234 _GLOBAL(book3e_start_thread)
235 LOAD_REG_IMMEDIATE(r5, MSR_KERNEL)
240 /* If the thread id is invalid, just exit. */
258 * stop a thread in the same core
260 * r3 = the thread physical id
262 _GLOBAL(book3e_stop_thread)
267 /* If the thread id is invalid, just exit. */
276 _GLOBAL(fsl_secondary_thread_init)
279 /* Enable branch prediction */
281 ori r3,r3,BUCSR_INIT@l
286 * Fix PIR to match the linear numbering in the device tree.
288 * On e6500, the reset value of PIR uses the low three bits for
289 * the thread within a core, and the upper bits for the core
290 * number. There are two threads per core, so shift everything
291 * but the low bit right by two bits so that the cpu numbering is
294 * If the old value of BUCSR is non-zero, this thread has run
295 * before. Thus, we assume we are coming from kexec or a similar
296 * scenario, and PIR is already set to the correct value. This
297 * is a bit of a hack, but there are limited opportunities for
298 * getting information into the thread and the alternatives
299 * seemed like they'd be overkill. We can't tell just by looking
300 * at the old PIR value which state it's in, since the same value
301 * could be valid for one thread out of reset and for a different
308 rlwimi r3, r3, 30, 2, 30
313 /* turn on 64-bit mode */
316 /* get a valid TOC pointer, wherever we're mapped at */
320 /* Book3E initialization */
322 bl book3e_secondary_thread_init
323 b generic_secondary_common_init
325 #endif /* CONFIG_PPC_BOOK3E */
328 * On pSeries and most other platforms, secondary processors spin
329 * in the following code.
330 * At entry, r3 = this processor's number (physical cpu id)
332 * On Book3E, r4 = 1 to indicate that the initial TLB entry for
333 * this core already exists (setup via some other mechanism such
334 * as SCOM before entry).
336 _GLOBAL(generic_secondary_smp_init)
341 /* turn on 64-bit mode */
344 /* get a valid TOC pointer, wherever we're mapped at */
348 #ifdef CONFIG_PPC_BOOK3E
349 /* Book3E initialization */
352 bl book3e_secondary_core_init
355 * After common core init has finished, check if the current thread is the
356 * one we wanted to boot. If not, start the specified thread and stop the
359 LOAD_REG_ADDR(r4, booting_thread_hwid)
361 li r5, INVALID_THREAD_HWID
366 * The value of booting_thread_hwid has been stored in r3,
367 * so make it invalid.
372 * Get the current thread id and check if it is the one we wanted.
373 * If not, start the one specified in booting_thread_hwid and stop
374 * the current thread.
380 /* start the specified thread */
381 LOAD_REG_ADDR(r5, fsl_secondary_thread_init)
383 bl book3e_start_thread
385 /* stop the current thread */
387 bl book3e_stop_thread
393 generic_secondary_common_init:
394 /* Set up a paca value for this processor. Since we have the
395 * physical cpu id in r24, we need to search the pacas to find
396 * which logical id maps to our physical one.
399 b kexec_wait /* wait for next kernel if !SMP */
401 LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */
402 ld r8,0(r8) /* Get base vaddr of array */
403 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */
404 lwz r7,0(r7) /* also the max paca allocated */
405 li r5,0 /* logical cpu id */
407 sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */
408 ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */
409 lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
410 cmpw r6,r24 /* Compare to our id */
413 cmpw r5,r7 /* Check if more pacas exist */
416 mr r3,r24 /* not found, copy phys to r3 */
417 b kexec_wait /* next kernel might do better */
420 #ifdef CONFIG_PPC_BOOK3E
421 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */
422 mtspr SPRN_SPRG_TLB_EXFRAME,r12
425 /* From now on, r24 is expected to be logical cpuid */
428 /* Create a temp kernel stack for use before relocation is on. */
429 ld r1,PACAEMERGSP(r13)
430 subi r1,r1,STACK_FRAME_OVERHEAD
432 /* See if we need to call a cpu state restore handler */
433 LOAD_REG_ADDR(r23, cur_cpu_spec)
435 ld r12,CPU_SPEC_RESTORE(r23)
438 #ifdef PPC64_ELF_ABI_v1
444 3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */
452 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
455 beq 4b /* Loop until told to go */
457 sync /* order paca.run and cur_cpu_spec */
458 isync /* In case code patching happened */
465 * Assumes we're mapped EA == RA if the MMU is on.
467 #ifdef CONFIG_PPC_BOOK3S
470 andi. r0,r3,MSR_IR|MSR_DR
478 b . /* prevent speculative execution */
483 * Here is our main kernel entry point. We support currently 2 kind of entries
484 * depending on the value of r5.
486 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
489 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
490 * DT block, r4 is a physical pointer to the kernel itself
493 __start_initialization_multiplatform:
494 /* Make sure we are running in 64 bits mode */
497 /* Get TOC pointer (current runtime address) */
500 /* find out where we are now */
502 0: mflr r26 /* r26 = runtime addr here */
503 addis r26,r26,(_stext - 0b)@ha
504 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
507 * Are we booted from a PROM Of-type client-interface ?
511 b __boot_from_prom /* yes -> prom */
513 /* Save parameters */
516 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
517 /* Save OPAL entry */
522 #ifdef CONFIG_PPC_BOOK3E
523 bl start_initialization_book3e
526 /* Setup some critical 970 SPRs before switching MMU off */
529 cmpwi r0,0x39 /* 970 */
531 cmpwi r0,0x3c /* 970FX */
533 cmpwi r0,0x44 /* 970MP */
535 cmpwi r0,0x45 /* 970GX */
537 1: bl __cpu_preinit_ppc970
540 /* Switch off MMU if not already off */
543 #endif /* CONFIG_PPC_BOOK3E */
547 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
548 /* Save parameters */
556 * Align the stack to 16-byte boundary
557 * Depending on the size and layout of the ELF sections in the initial
558 * boot binary, the stack pointer may be unaligned on PowerMac
562 #ifdef CONFIG_RELOCATABLE
563 /* Relocate code for where we are now */
568 /* Restore parameters */
575 /* Do all of the interaction with OF client interface */
578 #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
580 /* We never return. We also hit that trap if trying to boot
581 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
586 #ifdef CONFIG_RELOCATABLE
587 /* process relocations for the final address of the kernel */
588 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
590 #if defined(CONFIG_PPC_BOOK3E)
591 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
593 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
594 #if defined(CONFIG_PPC_BOOK3E)
597 cmplwi cr0,r7,1 /* flagged to stay where we are ? */
602 #if defined(CONFIG_PPC_BOOK3E)
603 /* IVPR needs to be set after relocation. */
609 * We need to run with _stext at physical address PHYSICAL_START.
610 * This will leave some code in the first 256B of
611 * real memory, which are reserved for software use.
613 * Note: This process overwrites the OF exception vectors.
615 li r3,0 /* target addr */
616 #ifdef CONFIG_PPC_BOOK3E
617 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */
619 mr. r4,r26 /* In some cases the loader may */
620 #if defined(CONFIG_PPC_BOOK3E)
623 beq 9f /* have already put us at zero */
624 li r6,0x100 /* Start offset, the first 0x100 */
625 /* bytes were copied earlier. */
627 #ifdef CONFIG_RELOCATABLE
629 * Check if the kernel has to be running as relocatable kernel based on the
630 * variable __run_at_load, if it is set the kernel is treated as relocatable
631 * kernel, otherwise it will be moved to PHYSICAL_START
633 #if defined(CONFIG_PPC_BOOK3E)
634 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
636 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
640 #ifdef CONFIG_PPC_BOOK3E
641 LOAD_REG_ADDR(r5, __end_interrupts)
642 LOAD_REG_ADDR(r11, _stext)
645 /* just copy interrupts */
646 LOAD_REG_IMMEDIATE_SYM(r5, r11, FIXED_SYMBOL_ABS_ADDR(__end_interrupts))
651 /* # bytes of memory to copy */
652 lis r5,(ABS_ADDR(copy_to_here))@ha
653 addi r5,r5,(ABS_ADDR(copy_to_here))@l
655 bl copy_and_flush /* copy the first n bytes */
656 /* this includes the code being */
658 /* Jump to the copy of this code that we just made */
659 addis r8,r3,(ABS_ADDR(4f))@ha
660 addi r12,r8,(ABS_ADDR(4f))@l
665 p_end: .8byte _end - copy_to_here
669 * Now copy the rest of the kernel up to _end, add
670 * _end - copy_to_here to the copy limit and run again.
672 addis r8,r26,(ABS_ADDR(p_end))@ha
673 ld r8,(ABS_ADDR(p_end))@l(r8)
675 5: bl copy_and_flush /* copy the rest */
677 9: b start_here_multiplatform
680 * Copy routine used to copy the kernel to start at physical address 0
681 * and flush and invalidate the caches as needed.
682 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
683 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
685 * Note: this routine *only* clobbers r0, r6 and lr
687 _GLOBAL(copy_and_flush)
690 4: li r0,8 /* Use the smallest common */
691 /* denominator cache line */
692 /* size. This results in */
693 /* extra cache line flushes */
694 /* but operation is correct. */
695 /* Can't get cache line size */
696 /* from NACA as it is being */
699 mtctr r0 /* put # words/line in ctr */
700 3: addi r6,r6,8 /* copy a cache line */
704 dcbst r6,r3 /* write it to memory */
706 icbi r6,r3 /* flush the icache line */
715 _ASM_NOKPROBE_SYMBOL(copy_and_flush); /* Called in real mode */
721 #ifdef CONFIG_PPC_PMAC
723 * On PowerMac, secondary processors starts from the reset vector, which
724 * is temporarily turned into a call to one of the functions below.
729 .globl __secondary_start_pmac_0
730 __secondary_start_pmac_0:
731 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
741 _GLOBAL(pmac_secondary_start)
742 /* turn on 64-bit mode */
747 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
754 /* get TOC pointer (real address) */
758 /* Copy some CPU settings from CPU 0 */
759 bl __restore_cpu_ppc970
761 /* pSeries do that early though I don't think we really need it */
764 mtmsrd r3 /* RI on */
766 /* Set up a paca value for this processor. */
767 LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */
768 ld r4,0(r4) /* Get base vaddr of paca_ptrs array */
769 sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */
770 ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */
771 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/
773 /* Mark interrupts soft and hard disabled (they might be enabled
774 * in the PACA when doing hotplug)
777 stb r0,PACAIRQSOFTMASK(r13)
778 li r0,PACA_IRQ_HARD_DIS
779 stb r0,PACAIRQHAPPENED(r13)
781 /* Create a temp kernel stack for use before relocation is on. */
782 ld r1,PACAEMERGSP(r13)
783 subi r1,r1,STACK_FRAME_OVERHEAD
787 #endif /* CONFIG_PPC_PMAC */
790 * This function is called after the master CPU has released the
791 * secondary processors. The execution environment is relocation off.
792 * The paca for this processor has the following fields initialized at
794 * 1. Processor number
795 * 2. Segment table pointer (virtual address)
796 * On entry the following are set:
797 * r1 = stack pointer (real addr of temp stack)
798 * r24 = cpu# (in Linux terms)
799 * r13 = paca virtual address
800 * SPRG_PACA = paca virtual address
805 .globl __secondary_start
807 /* Set thread priority to MEDIUM */
811 * Do early setup for this CPU, in particular initialising the MMU so we
812 * can turn it on below. This is a call to C, which is OK, we're still
813 * running on the emergency stack.
815 bl early_setup_secondary
818 * The primary has initialized our kernel stack for us in the paca, grab
819 * it and put it in r1. We must *not* use it until we turn on the MMU
820 * below, because it may not be inside the RMO.
822 ld r1, PACAKSAVE(r13)
824 /* Clear backchain so we get nice backtraces */
828 /* Mark interrupts soft and hard disabled (they might be enabled
829 * in the PACA when doing hotplug)
832 stb r7,PACAIRQSOFTMASK(r13)
833 li r0,PACA_IRQ_HARD_DIS
834 stb r0,PACAIRQHAPPENED(r13)
836 /* enable MMU and jump to start_secondary */
837 LOAD_REG_ADDR(r3, start_secondary_prolog)
838 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
843 b . /* prevent speculative execution */
846 * Running with relocation on at this point. All we want to do is
847 * zero the stack back-chain pointer and get the TOC virtual address
848 * before going into C code.
850 start_secondary_prolog:
853 std r3,0(r1) /* Zero the stack frame pointer */
857 * Reset stack pointer and call start_secondary
858 * to continue with online operation when woken up
859 * from cede in cpu offline.
861 _GLOBAL(start_secondary_resume)
862 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
864 std r3,0(r1) /* Zero the stack frame pointer */
870 * This subroutine clobbers r11 and r12
873 mfmsr r11 /* grab the current MSR */
874 #ifdef CONFIG_PPC_BOOK3E
875 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */
877 #else /* CONFIG_PPC_BOOK3E */
878 LOAD_REG_IMMEDIATE(r12, MSR_64BIT)
886 * This puts the TOC pointer into r2, offset by 0x8000 (as expected
887 * by the toolchain). It computes the correct value for wherever we
888 * are running at the moment, using position-independent code.
890 * Note: The compiler constructs pointers using offsets from the
891 * TOC in -mcmodel=medium mode. After we relocate to 0 but before
892 * the MMU is on we need our TOC to be a virtual address otherwise
893 * these pointers will be real addresses which may get stored and
894 * accessed later with the MMU on. We use tovirt() at the call
895 * sites to handle this.
897 _GLOBAL(relative_toc)
901 ld r2,(p_toc - 0b)(r11)
907 p_toc: .8byte __toc_start + 0x8000 - 0b
910 * This is where the main kernel code starts.
913 start_here_multiplatform:
918 /* Clear out the BSS. It may have been done in prom_init,
919 * already but that's irrelevant since prom_init will soon
920 * be detached from the kernel completely. Besides, we need
921 * to clear it now for kexec-style entry.
923 LOAD_REG_ADDR(r11,__bss_stop)
924 LOAD_REG_ADDR(r8,__bss_start)
925 sub r11,r11,r8 /* bss size */
926 addi r11,r11,7 /* round up to an even double word */
927 srdi. r11,r11,3 /* shift right by 3 */
931 mtctr r11 /* zero this many doublewords */
936 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
937 /* Setup OPAL entry */
938 LOAD_REG_ADDR(r11, opal)
943 #ifndef CONFIG_PPC_BOOK3E
946 mtmsrd r6 /* RI on */
949 #ifdef CONFIG_RELOCATABLE
950 /* Save the physical address we're running at in kernstart_addr */
951 LOAD_REG_ADDR(r4, kernstart_addr)
956 /* set up a stack pointer */
957 LOAD_REG_ADDR(r3,init_thread_union)
958 LOAD_REG_IMMEDIATE(r1,THREAD_SIZE)
961 stdu r0,-STACK_FRAME_OVERHEAD(r1)
964 * Do very early kernel initializations, including initial hash table
965 * and SLB setup before we turn on relocation.
968 /* Restore parameters passed from prom_init/kexec */
970 LOAD_REG_ADDR(r12, DOTSYM(early_setup))
972 bctrl /* also sets r13 and SPRG_PACA */
974 LOAD_REG_ADDR(r3, start_here_common)
979 b . /* prevent speculative execution */
981 /* This is where all platforms converge execution */
984 /* relocation is on at this point */
985 std r1,PACAKSAVE(r13)
987 /* Load the TOC (virtual address) */
990 /* Mark interrupts soft and hard disabled (they might be enabled
991 * in the PACA when doing hotplug)
994 stb r0,PACAIRQSOFTMASK(r13)
995 li r0,PACA_IRQ_HARD_DIS
996 stb r0,PACAIRQHAPPENED(r13)
998 /* Generic kernel entry */
1003 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0