1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Adapted for Power Macintosh by Paul Mackerras.
9 * Low-level exception handlers and MMU support
10 * rewritten by Paul Mackerras.
11 * Copyright (C) 1996 Paul Mackerras.
13 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
14 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
16 * This file contains the entry point for the 64-bit kernel along
17 * with some early initialization code common to all 64-bit powerpc
21 #include <linux/linkage.h>
22 #include <linux/threads.h>
23 #include <linux/init.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/head-64.h>
29 #include <asm/asm-offsets.h>
31 #include <asm/cputable.h>
32 #include <asm/setup.h>
33 #include <asm/hvcall.h>
34 #include <asm/thread_info.h>
35 #include <asm/firmware.h>
36 #include <asm/page_64.h>
37 #include <asm/irqflags.h>
38 #include <asm/kvm_book3s_asm.h>
39 #include <asm/ptrace.h>
40 #include <asm/hw_irq.h>
41 #include <asm/cputhreads.h>
42 #include <asm/ppc-opcode.h>
43 #include <asm/export.h>
44 #include <asm/feature-fixups.h>
45 #ifdef CONFIG_PPC_BOOK3S
46 #include <asm/exception-64s.h>
48 #include <asm/exception-64e.h>
51 /* The physical memory is laid out such that the secondary processor
52 * spin code sits at 0x0000...0x00ff. On server, the vectors follow
53 * using the layout described in exceptions-64s.S
57 * Entering into this code we make the following assumptions:
59 * For pSeries or server processors:
60 * 1. The MMU is off & open firmware is running in real mode.
61 * 2. The primary CPU enters at __start.
62 * 3. If the RTAS supports "query-cpu-stopped-state", then secondary
63 * CPUs will enter as directed by "start-cpu" RTAS call, which is
64 * generic_secondary_smp_init, with PIR in r3.
65 * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as
66 * directed by the "start-cpu" RTS call, with PIR in r3.
67 * -or- For OPAL entry:
68 * 1. The MMU is off, processor in HV mode.
69 * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base
70 * in r8, and entry in r9 for debugging purposes.
71 * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which
72 * is at generic_secondary_smp_init, with PIR in r3.
74 * For Book3E processors:
75 * 1. The MMU is on running in AS0 in a state defined in ePAPR
76 * 2. The kernel is entered at __start
80 * boot_from_prom and prom_init run at the physical address. Everything
81 * after prom and kexec entry run at the virtual address (PAGE_OFFSET).
82 * Secondaries run at the virtual address from generic_secondary_common_init
86 OPEN_FIXED_SECTION(first_256B, 0x0, 0x100)
87 USE_FIXED_SECTION(first_256B)
89 * Offsets are relative from the start of fixed section, and
90 * first_256B starts at 0. Offsets are a bit easier to use here
91 * than the fixed section entry macros.
95 /* NOP this out unconditionally */
98 b __start_initialization_multiplatform
101 /* Catch branch to 0 in real mode */
104 /* Secondary processors spin on this value until it becomes non-zero.
105 * When non-zero, it contains the real address of the function the cpu
109 .globl __secondary_hold_spinloop
110 __secondary_hold_spinloop:
113 /* Secondary processors write this value with their cpu # */
114 /* after they enter the spin loop immediately below. */
115 .globl __secondary_hold_acknowledge
116 __secondary_hold_acknowledge:
119 #ifdef CONFIG_RELOCATABLE
120 /* This flag is set to 1 by a loader if the kernel should run
121 * at the loaded address instead of the linked address. This
122 * is used by kexec-tools to keep the kdump kernel in the
123 * crash_kernel region. The loader is responsible for
124 * observing the alignment requirement.
127 #ifdef CONFIG_RELOCATABLE_TEST
128 #define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */
130 #define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */
133 /* Do not move this variable as kexec-tools knows about it. */
137 DEFINE_FIXED_SYMBOL(__run_at_load, first_256B)
138 .long RUN_AT_LOAD_DEFAULT
143 * The following code is used to hold secondary processors
144 * in a spin loop after they have entered the kernel, but
145 * before the bulk of the kernel has been relocated. This code
146 * is relocated to physical address 0x60 before prom_init is run.
147 * All of it must fit below the first exception vector at 0x100.
148 * Use .globl here not _GLOBAL because we want __secondary_hold
149 * to be the actual text address, not a descriptor.
151 .globl __secondary_hold
154 #ifndef CONFIG_PPC_BOOK3E_64
157 mtmsrd r24 /* RI on */
159 /* Grab our physical cpu number */
161 /* stash r4 for book3e */
164 /* Tell the master cpu we're here */
165 /* Relocation is off & we are located at an address less */
166 /* than 0x100, so only need to grab low order offset. */
167 std r24,(ABS_ADDR(__secondary_hold_acknowledge, first_256B))(0)
170 /* All secondary cpus wait here until told to start. */
171 100: ld r12,(ABS_ADDR(__secondary_hold_spinloop, first_256B))(0)
175 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
176 #ifdef CONFIG_PPC_BOOK3E_64
182 * it may be the case that other platforms have r4 right to
183 * begin with, this gives us some safety in case it is not
185 #ifdef CONFIG_PPC_BOOK3E_64
190 /* Make sure that patched code is visible */
195 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
197 CLOSE_FIXED_SECTION(first_256B)
200 * On server, we include the exception vectors code here as it
201 * relies on absolute addressing which is only possible within
202 * this compilation unit
204 #ifdef CONFIG_PPC_BOOK3S
205 #include "exceptions-64s.S"
207 OPEN_TEXT_SECTION(0x100)
212 #include "interrupt_64.S"
214 #ifdef CONFIG_PPC_BOOK3E_64
216 * The booting_thread_hwid holds the thread id we want to boot in cpu
217 * hotplug case. It is set by cpu hotplug code, and is invalid by default.
218 * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID]
221 .globl booting_thread_hwid
223 .long INVALID_THREAD_HWID
226 * start a thread in the same core
228 * r3 = the thread physical id
229 * r4 = the entry point where thread starts
231 _GLOBAL(book3e_start_thread)
232 LOAD_REG_IMMEDIATE(r5, MSR_KERNEL)
237 /* If the thread id is invalid, just exit. */
255 * stop a thread in the same core
257 * r3 = the thread physical id
259 _GLOBAL(book3e_stop_thread)
264 /* If the thread id is invalid, just exit. */
273 _GLOBAL(fsl_secondary_thread_init)
276 /* Enable branch prediction */
278 ori r3,r3,BUCSR_INIT@l
283 * Fix PIR to match the linear numbering in the device tree.
285 * On e6500, the reset value of PIR uses the low three bits for
286 * the thread within a core, and the upper bits for the core
287 * number. There are two threads per core, so shift everything
288 * but the low bit right by two bits so that the cpu numbering is
291 * If the old value of BUCSR is non-zero, this thread has run
292 * before. Thus, we assume we are coming from kexec or a similar
293 * scenario, and PIR is already set to the correct value. This
294 * is a bit of a hack, but there are limited opportunities for
295 * getting information into the thread and the alternatives
296 * seemed like they'd be overkill. We can't tell just by looking
297 * at the old PIR value which state it's in, since the same value
298 * could be valid for one thread out of reset and for a different
305 rlwimi r3, r3, 30, 2, 30
310 /* turn on 64-bit mode */
313 /* Book3E initialization */
315 bl book3e_secondary_thread_init
318 b generic_secondary_common_init
320 #endif /* CONFIG_PPC_BOOK3E_64 */
323 * On pSeries and most other platforms, secondary processors spin
324 * in the following code.
325 * At entry, r3 = this processor's number (physical cpu id)
327 * On Book3E, r4 = 1 to indicate that the initial TLB entry for
328 * this core already exists (setup via some other mechanism such
329 * as SCOM before entry).
331 _GLOBAL(generic_secondary_smp_init)
342 /* turn on 64-bit mode */
345 #ifdef CONFIG_PPC_BOOK3E_64
346 /* Book3E initialization */
349 bl book3e_secondary_core_init
350 /* Now NIA and r2 are relocated to PAGE_OFFSET if not already */
352 * After common core init has finished, check if the current thread is the
353 * one we wanted to boot. If not, start the specified thread and stop the
356 LOAD_REG_ADDR(r4, booting_thread_hwid)
358 li r5, INVALID_THREAD_HWID
363 * The value of booting_thread_hwid has been stored in r3,
364 * so make it invalid.
369 * Get the current thread id and check if it is the one we wanted.
370 * If not, start the one specified in booting_thread_hwid and stop
371 * the current thread.
377 /* start the specified thread */
378 LOAD_REG_ADDR(r5, DOTSYM(fsl_secondary_thread_init))
379 bl book3e_start_thread
381 /* stop the current thread */
383 bl book3e_stop_thread
388 /* Now the MMU is off, can branch to our PAGE_OFFSET address */
391 addi r11,r11,(2f - 1b)
399 generic_secondary_common_init:
400 /* Set up a paca value for this processor. Since we have the
401 * physical cpu id in r24, we need to search the pacas to find
402 * which logical id maps to our physical one.
405 b kexec_wait /* wait for next kernel if !SMP */
407 LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */
408 ld r8,0(r8) /* Get base vaddr of array */
409 #if (NR_CPUS == 1) || defined(CONFIG_FORCE_NR_CPUS)
410 LOAD_REG_IMMEDIATE(r7, NR_CPUS)
412 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */
413 lwz r7,0(r7) /* also the max paca allocated */
415 li r5,0 /* logical cpu id */
417 sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */
418 ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */
419 lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
420 cmpw r6,r24 /* Compare to our id */
423 cmpw r5,r7 /* Check if more pacas exist */
426 mr r3,r24 /* not found, copy phys to r3 */
427 b kexec_wait /* next kernel might do better */
430 #ifdef CONFIG_PPC_BOOK3E_64
431 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */
432 mtspr SPRN_SPRG_TLB_EXFRAME,r12
435 /* From now on, r24 is expected to be logical cpuid */
438 /* Create a temp kernel stack for use before relocation is on. */
439 ld r1,PACAEMERGSP(r13)
440 subi r1,r1,STACK_FRAME_MIN_SIZE
442 /* See if we need to call a cpu state restore handler */
443 LOAD_REG_ADDR(r23, cur_cpu_spec)
445 ld r12,CPU_SPEC_RESTORE(r23)
448 #ifdef CONFIG_PPC64_ELF_ABI_V1
454 3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */
462 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
465 beq 4b /* Loop until told to go */
467 sync /* order paca.run and cur_cpu_spec */
468 isync /* In case code patching happened */
475 * Assumes we're mapped EA == RA if the MMU is on.
477 #ifdef CONFIG_PPC_BOOK3S
478 SYM_FUNC_START_LOCAL(__mmu_off)
480 andi. r0,r3,MSR_IR|MSR_DR
488 b . /* prevent speculative execution */
489 SYM_FUNC_END(__mmu_off)
491 SYM_FUNC_START_LOCAL(start_initialization_book3s)
494 /* Setup some critical 970 SPRs before switching MMU off */
497 cmpwi r0,0x39 /* 970 */
499 cmpwi r0,0x3c /* 970FX */
501 cmpwi r0,0x44 /* 970MP */
503 cmpwi r0,0x45 /* 970GX */
505 1: bl __cpu_preinit_ppc970
508 /* Switch off MMU if not already off */
511 /* Now the MMU is off, can return to our PAGE_OFFSET address */
515 SYM_FUNC_END(start_initialization_book3s)
519 * Here is our main kernel entry point. We support currently 2 kind of entries
520 * depending on the value of r5.
522 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
525 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
526 * DT block, r4 is a physical pointer to the kernel itself
529 __start_initialization_multiplatform:
530 /* Make sure we are running in 64 bits mode */
533 /* Zero r13 (paca) so early program check / mce don't use it */
540 * Are we booted from a PROM Of-type client-interface ?
544 b __boot_from_prom /* yes -> prom */
546 /* Save parameters */
549 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
550 /* Save OPAL entry */
555 /* Get TOC pointer (current runtime address) */
558 /* These functions return to the virtual (PAGE_OFFSET) address */
559 #ifdef CONFIG_PPC_BOOK3E_64
560 bl start_initialization_book3e
562 bl start_initialization_book3s
563 #endif /* CONFIG_PPC_BOOK3E_64 */
565 /* Get TOC pointer, virtual */
568 /* find out where we are now */
570 /* OPAL doesn't pass base address in r4, have to derive it. */
572 0: mflr r26 /* r26 = runtime addr here */
573 addis r26,r26,(_stext - 0b)@ha
574 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
580 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
581 /* Get TOC pointer, non-virtual */
584 /* find out where we are now */
586 0: mflr r26 /* r26 = runtime addr here */
587 addis r26,r26,(_stext - 0b)@ha
588 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
590 /* Save parameters */
598 * Align the stack to 16-byte boundary
599 * Depending on the size and layout of the ELF sections in the initial
600 * boot binary, the stack pointer may be unaligned on PowerMac
604 #ifdef CONFIG_RELOCATABLE
605 /* Relocate code for where we are now */
610 /* Restore parameters */
617 /* Do all of the interaction with OF client interface */
620 #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
622 /* We never return. We also hit that trap if trying to boot
623 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
628 #ifdef CONFIG_RELOCATABLE
629 /* process relocations for the final address of the kernel */
630 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
631 cmplwi cr0,r7,1 /* flagged to stay where we are ? */
632 mr r25,r26 /* then use current kernel base */
634 LOAD_REG_IMMEDIATE(r25, PAGE_OFFSET) /* else use static kernel base */
637 #if defined(CONFIG_PPC_BOOK3E_64)
638 /* IVPR needs to be set after relocation. */
644 * We need to run with _stext at physical address PHYSICAL_START.
645 * This will leave some code in the first 256B of
646 * real memory, which are reserved for software use.
648 * Note: This process overwrites the OF exception vectors.
650 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET)
651 mr. r4,r26 /* In some cases the loader may */
652 beq 9f /* have already put us at zero */
653 li r6,0x100 /* Start offset, the first 0x100 */
654 /* bytes were copied earlier. */
656 #ifdef CONFIG_RELOCATABLE
658 * Check if the kernel has to be running as relocatable kernel based on the
659 * variable __run_at_load, if it is set the kernel is treated as relocatable
660 * kernel, otherwise it will be moved to PHYSICAL_START
662 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
666 #ifdef CONFIG_PPC_BOOK3E_64
667 LOAD_REG_ADDR(r5, __end_interrupts)
668 LOAD_REG_ADDR(r11, _stext)
671 /* just copy interrupts */
672 LOAD_REG_IMMEDIATE_SYM(r5, r11, FIXED_SYMBOL_ABS_ADDR(__end_interrupts))
677 /* # bytes of memory to copy */
678 lis r5,(ABS_ADDR(copy_to_here, text))@ha
679 addi r5,r5,(ABS_ADDR(copy_to_here, text))@l
681 bl copy_and_flush /* copy the first n bytes */
682 /* this includes the code being */
684 /* Jump to the copy of this code that we just made */
685 addis r8,r3,(ABS_ADDR(4f, text))@ha
686 addi r12,r8,(ABS_ADDR(4f, text))@l
691 p_end: .8byte _end - copy_to_here
695 * Now copy the rest of the kernel up to _end, add
696 * _end - copy_to_here to the copy limit and run again.
698 addis r8,r26,(ABS_ADDR(p_end, text))@ha
699 ld r8,(ABS_ADDR(p_end, text))@l(r8)
701 5: bl copy_and_flush /* copy the rest */
703 9: b start_here_multiplatform
706 * Copy routine used to copy the kernel to start at physical address 0
707 * and flush and invalidate the caches as needed.
708 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
709 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
711 * Note: this routine *only* clobbers r0, r6 and lr
713 _GLOBAL(copy_and_flush)
716 4: li r0,8 /* Use the smallest common */
717 /* denominator cache line */
718 /* size. This results in */
719 /* extra cache line flushes */
720 /* but operation is correct. */
721 /* Can't get cache line size */
722 /* from NACA as it is being */
725 mtctr r0 /* put # words/line in ctr */
726 3: addi r6,r6,8 /* copy a cache line */
730 dcbst r6,r3 /* write it to memory */
732 icbi r6,r3 /* flush the icache line */
741 _ASM_NOKPROBE_SYMBOL(copy_and_flush); /* Called in real mode */
747 #ifdef CONFIG_PPC_PMAC
749 * On PowerMac, secondary processors starts from the reset vector, which
750 * is temporarily turned into a call to one of the functions below.
755 .globl __secondary_start_pmac_0
756 __secondary_start_pmac_0:
757 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
767 _GLOBAL(pmac_secondary_start)
768 /* turn on 64-bit mode */
773 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
780 /* Branch to our PAGE_OFFSET address */
783 addi r11,r11,(2f - 1b)
790 /* Copy some CPU settings from CPU 0 */
791 bl __restore_cpu_ppc970
793 /* pSeries do that early though I don't think we really need it */
796 mtmsrd r3 /* RI on */
798 /* Set up a paca value for this processor. */
799 LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */
800 ld r4,0(r4) /* Get base vaddr of paca_ptrs array */
801 sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */
802 ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */
803 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/
805 /* Mark interrupts soft and hard disabled (they might be enabled
806 * in the PACA when doing hotplug)
809 stb r0,PACAIRQSOFTMASK(r13)
810 li r0,PACA_IRQ_HARD_DIS
811 stb r0,PACAIRQHAPPENED(r13)
813 /* Create a temp kernel stack for use before relocation is on. */
814 ld r1,PACAEMERGSP(r13)
815 subi r1,r1,STACK_FRAME_MIN_SIZE
819 #endif /* CONFIG_PPC_PMAC */
822 * This function is called after the master CPU has released the
823 * secondary processors. The execution environment is relocation off.
824 * The paca for this processor has the following fields initialized at
826 * 1. Processor number
827 * 2. Segment table pointer (virtual address)
828 * On entry the following are set:
829 * r1 = stack pointer (real addr of temp stack)
830 * r24 = cpu# (in Linux terms)
831 * r13 = paca virtual address
832 * SPRG_PACA = paca virtual address
837 .globl __secondary_start
839 /* Set thread priority to MEDIUM */
843 * Do early setup for this CPU, in particular initialising the MMU so we
844 * can turn it on below. This is a call to C, which is OK, we're still
845 * running on the emergency stack.
847 bl CFUNC(early_setup_secondary)
850 * The primary has initialized our kernel stack for us in the paca, grab
851 * it and put it in r1. We must *not* use it until we turn on the MMU
852 * below, because it may not be inside the RMO.
854 ld r1, PACAKSAVE(r13)
856 /* Clear backchain so we get nice backtraces */
860 /* Mark interrupts soft and hard disabled (they might be enabled
861 * in the PACA when doing hotplug)
864 stb r7,PACAIRQSOFTMASK(r13)
865 li r0,PACA_IRQ_HARD_DIS
866 stb r0,PACAIRQHAPPENED(r13)
868 /* enable MMU and jump to start_secondary */
869 LOAD_REG_ADDR(r3, start_secondary_prolog)
870 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
875 b . /* prevent speculative execution */
878 * Running with relocation on at this point. All we want to do is
879 * zero the stack back-chain pointer and get the TOC virtual address
880 * before going into C code.
882 start_secondary_prolog:
885 std r3,0(r1) /* Zero the stack frame pointer */
886 bl CFUNC(start_secondary)
889 * Reset stack pointer and call start_secondary
890 * to continue with online operation when woken up
891 * from cede in cpu offline.
893 _GLOBAL(start_secondary_resume)
894 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
896 std r3,0(r1) /* Zero the stack frame pointer */
897 bl CFUNC(start_secondary)
902 * This subroutine clobbers r11 and r12
904 SYM_FUNC_START_LOCAL(enable_64b_mode)
905 mfmsr r11 /* grab the current MSR */
906 #ifdef CONFIG_PPC_BOOK3E_64
907 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */
909 #else /* CONFIG_PPC_BOOK3E_64 */
910 LOAD_REG_IMMEDIATE(r12, MSR_64BIT)
916 SYM_FUNC_END(enable_64b_mode)
919 * This puts the TOC pointer into r2, offset by 0x8000 (as expected
920 * by the toolchain). It computes the correct value for wherever we
921 * are running at the moment, using position-independent code.
923 * Note: The compiler constructs pointers using offsets from the
924 * TOC in -mcmodel=medium mode. After we relocate to 0 but before
925 * the MMU is on we need our TOC to be a virtual address otherwise
926 * these pointers will be real addresses which may get stored and
927 * accessed later with the MMU on. We branch to the virtual address
928 * while still in real mode then call relative_toc again to handle
931 _GLOBAL(relative_toc)
932 #ifdef CONFIG_PPC_KERNEL_PCREL
939 ld r2,(p_toc - 0b)(r11)
945 p_toc: .8byte .TOC. - 0b
949 * This is where the main kernel code starts.
952 start_here_multiplatform:
953 /* Adjust TOC for moved kernel. Could adjust when moving it instead. */
956 /* Clear out the BSS. It may have been done in prom_init,
957 * already but that's irrelevant since prom_init will soon
958 * be detached from the kernel completely. Besides, we need
959 * to clear it now for kexec-style entry.
961 LOAD_REG_ADDR(r11,__bss_stop)
962 LOAD_REG_ADDR(r8,__bss_start)
963 sub r11,r11,r8 /* bss size */
964 addi r11,r11,7 /* round up to an even double word */
965 srdi. r11,r11,3 /* shift right by 3 */
969 mtctr r11 /* zero this many doublewords */
974 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
975 /* Setup OPAL entry */
976 LOAD_REG_ADDR(r11, opal)
981 #ifndef CONFIG_PPC_BOOK3E_64
984 mtmsrd r6 /* RI on */
987 #ifdef CONFIG_RELOCATABLE
988 /* Save the physical address we're running at in kernstart_addr */
989 LOAD_REG_ADDR(r4, kernstart_addr)
994 /* set up a stack pointer */
995 LOAD_REG_ADDR(r3,init_thread_union)
996 LOAD_REG_IMMEDIATE(r1,THREAD_SIZE)
999 stdu r0,-STACK_FRAME_MIN_SIZE(r1)
1002 * Do very early kernel initializations, including initial hash table
1003 * and SLB setup before we turn on relocation.
1007 bl CFUNC(kasan_early_init)
1009 /* Restore parameters passed from prom_init/kexec */
1011 LOAD_REG_ADDR(r12, DOTSYM(early_setup))
1013 bctrl /* also sets r13 and SPRG_PACA */
1015 LOAD_REG_ADDR(r3, start_here_common)
1020 b . /* prevent speculative execution */
1022 /* This is where all platforms converge execution */
1025 /* relocation is on at this point */
1026 std r1,PACAKSAVE(r13)
1028 /* Load the TOC (virtual address) */
1031 /* Mark interrupts soft and hard disabled (they might be enabled
1032 * in the PACA when doing hotplug)
1035 stb r0,PACAIRQSOFTMASK(r13)
1036 li r0,PACA_IRQ_HARD_DIS
1037 stb r0,PACAIRQHAPPENED(r13)
1039 /* Generic kernel entry */
1040 bl CFUNC(start_kernel)
1044 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0