1 /* SPDX-License-Identifier: GPL-2.0 */
3 * This file contains the 64-bit "server" PowerPC variant
4 * of the low level exception handling including exception
5 * vectors, exception return, part of the slb and stab
6 * handling and other fixed offset specific things.
8 * This file is meant to be #included from head_64.S due to
9 * position dependent assembly.
11 * Most of this originates from head_64.S and thus has the same
16 #include <linux/linkage.h>
17 #include <asm/hw_irq.h>
18 #include <asm/exception-64s.h>
19 #include <asm/ptrace.h>
20 #include <asm/cpuidle.h>
21 #include <asm/head-64.h>
22 #include <asm/feature-fixups.h>
26 * Following are fixed section helper macros.
28 * EXC_REAL_BEGIN/END - real, unrelocated exception vectors
29 * EXC_VIRT_BEGIN/END - virt (AIL), unrelocated exception vectors
30 * TRAMP_REAL_BEGIN - real, unrelocated helpers (virt may call these)
31 * TRAMP_VIRT_BEGIN - virt, unreloc helpers (in practice, real can use)
32 * EXC_COMMON - After switching to virtual, relocated mode.
35 #define EXC_REAL_BEGIN(name, start, size) \
36 FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##name, start, size)
38 #define EXC_REAL_END(name, start, size) \
39 FIXED_SECTION_ENTRY_END_LOCATION(real_vectors, exc_real_##start##_##name, start, size)
41 #define EXC_VIRT_BEGIN(name, start, size) \
42 FIXED_SECTION_ENTRY_BEGIN_LOCATION(virt_vectors, exc_virt_##start##_##name, start, size)
44 #define EXC_VIRT_END(name, start, size) \
45 FIXED_SECTION_ENTRY_END_LOCATION(virt_vectors, exc_virt_##start##_##name, start, size)
47 #define EXC_COMMON_BEGIN(name) \
49 .balign IFETCH_ALIGN_BYTES; \
51 _ASM_NOKPROBE_SYMBOL(name); \
52 DEFINE_FIXED_SYMBOL(name, text); \
55 #define TRAMP_REAL_BEGIN(name) \
56 FIXED_SECTION_ENTRY_BEGIN(real_trampolines, name)
58 #define TRAMP_VIRT_BEGIN(name) \
59 FIXED_SECTION_ENTRY_BEGIN(virt_trampolines, name)
61 #define EXC_REAL_NONE(start, size) \
62 FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##unused, start, size); \
63 FIXED_SECTION_ENTRY_END_LOCATION(real_vectors, exc_real_##start##_##unused, start, size)
65 #define EXC_VIRT_NONE(start, size) \
66 FIXED_SECTION_ENTRY_BEGIN_LOCATION(virt_vectors, exc_virt_##start##_##unused, start, size); \
67 FIXED_SECTION_ENTRY_END_LOCATION(virt_vectors, exc_virt_##start##_##unused, start, size)
70 * We're short on space and time in the exception prolog, so we can't
71 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label.
72 * Instead we get the base of the kernel from paca->kernelbase and or in the low
73 * part of label. This requires that the label be within 64KB of kernelbase, and
74 * that kernelbase be 64K aligned.
76 #define LOAD_HANDLER(reg, label) \
77 ld reg,PACAKBASE(r13); /* get high part of &label */ \
78 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label)
80 #define __LOAD_HANDLER(reg, label, section) \
81 ld reg,PACAKBASE(r13); \
82 ori reg,reg,(ABS_ADDR(label, section))@l
85 * Branches from unrelocated code (e.g., interrupts) to labels outside
86 * head-y require >64K offsets.
88 #define __LOAD_FAR_HANDLER(reg, label, section) \
89 ld reg,PACAKBASE(r13); \
90 ori reg,reg,(ABS_ADDR(label, section))@l; \
91 addis reg,reg,(ABS_ADDR(label, section))@h
94 * Interrupt code generation macros
96 #define IVEC .L_IVEC_\name\() /* Interrupt vector address */
97 #define IHSRR .L_IHSRR_\name\() /* Sets SRR or HSRR registers */
98 #define IHSRR_IF_HVMODE .L_IHSRR_IF_HVMODE_\name\() /* HSRR if HV else SRR */
99 #define IAREA .L_IAREA_\name\() /* PACA save area */
100 #define IVIRT .L_IVIRT_\name\() /* Has virt mode entry point */
101 #define IISIDE .L_IISIDE_\name\() /* Uses SRR0/1 not DAR/DSISR */
102 #define ICFAR .L_ICFAR_\name\() /* Uses CFAR */
103 #define ICFAR_IF_HVMODE .L_ICFAR_IF_HVMODE_\name\() /* Uses CFAR if HV */
104 #define IDAR .L_IDAR_\name\() /* Uses DAR (or SRR0) */
105 #define IDSISR .L_IDSISR_\name\() /* Uses DSISR (or SRR1) */
106 #define IBRANCH_TO_COMMON .L_IBRANCH_TO_COMMON_\name\() /* ENTRY branch to common */
107 #define IREALMODE_COMMON .L_IREALMODE_COMMON_\name\() /* Common runs in realmode */
108 #define IMASK .L_IMASK_\name\() /* IRQ soft-mask bit */
109 #define IKVM_REAL .L_IKVM_REAL_\name\() /* Real entry tests KVM */
110 #define __IKVM_REAL(name) .L_IKVM_REAL_ ## name
111 #define IKVM_VIRT .L_IKVM_VIRT_\name\() /* Virt entry tests KVM */
112 #define ISTACK .L_ISTACK_\name\() /* Set regular kernel stack */
113 #define __ISTACK(name) .L_ISTACK_ ## name
114 #define IKUAP .L_IKUAP_\name\() /* Do KUAP lock */
115 #define IMSR_R12 .L_IMSR_R12_\name\() /* Assumes MSR saved to r12 */
117 #define INT_DEFINE_BEGIN(n) \
118 .macro int_define_ ## n name
120 #define INT_DEFINE_END(n) \
122 int_define_ ## n n ; \
125 .macro do_define_int name
127 .error "IVEC not defined"
132 .ifndef IHSRR_IF_HVMODE
147 .ifndef ICFAR_IF_HVMODE
156 .ifndef IBRANCH_TO_COMMON
159 .ifndef IREALMODE_COMMON
162 .if ! IBRANCH_TO_COMMON
163 .error "IREALMODE_COMMON=1 but IBRANCH_TO_COMMON=0"
187 * All interrupts which set HSRR registers, as well as SRESET and MCE and
188 * syscall when invoked with "sc 1" switch to MSR[HV]=1 (HVMODE) to be taken,
189 * so they all generally need to test whether they were taken in guest context.
191 * Note: SRESET and MCE may also be sent to the guest by the hypervisor, and be
192 * taken with MSR[HV]=0.
194 * Interrupts which set SRR registers (with the above exceptions) do not
195 * elevate to MSR[HV]=1 mode, though most can be taken when running with
196 * MSR[HV]=1 (e.g., bare metal kernel and userspace). So these interrupts do
197 * not need to test whether a guest is running because they get delivered to
198 * the guest directly, including nested HV KVM guests.
200 * The exception is PR KVM, where the guest runs with MSR[PR]=1 and the host
201 * runs with MSR[HV]=0, so the host takes all interrupts on behalf of the
202 * guest. PR KVM runs with LPCR[AIL]=0 which causes interrupts to always be
203 * delivered to the real-mode entry point, therefore such interrupts only test
204 * KVM in their real mode handlers, and only when PR KVM is possible.
206 * Interrupts that are taken in MSR[HV]=0 and escalate to MSR[HV]=1 are always
207 * delivered in real-mode when the MMU is in hash mode because the MMU
208 * registers are not set appropriately to translate host addresses. In nested
209 * radix mode these can be delivered in virt-mode as the host translations are
210 * used implicitly (see: effective LPID, effective PID).
214 * If an interrupt is taken while a guest is running, it is immediately routed
218 .macro KVMTEST name handler
219 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
220 lbz r10,HSTATE_IN_GUEST(r13)
222 /* HSRR variants have the 0x2 bit added to their trap number */
228 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
239 * This is the BOOK3S interrupt entry code macro.
241 * This can result in one of several things happening:
242 * - Branch to the _common handler, relocated, in virtual mode.
243 * These are normal interrupts (synchronous and asynchronous) handled by
245 * - Branch to KVM, relocated but real mode interrupts remain in real mode.
246 * These occur when HSTATE_IN_GUEST is set. The interrupt may be caused by
247 * / intended for host or guest kernel, but KVM must always be involved
248 * because the machine state is set for guest execution.
249 * - Branch to the masked handler, unrelocated.
250 * These occur when maskable asynchronous interrupts are taken with the
252 * - Branch to an "early" handler in real mode but relocated.
253 * This is done if early=1. MCE and HMI use these to handle errors in real
255 * - Fall through and continue executing in real, unrelocated mode.
256 * This is done if early=2.
259 .macro GEN_BRANCH_TO_COMMON name, virt
261 LOAD_HANDLER(r10, \name\()_common)
266 #ifndef CONFIG_RELOCATABLE
267 b \name\()_common_virt
269 LOAD_HANDLER(r10, \name\()_common_virt)
274 LOAD_HANDLER(r10, \name\()_common_real)
281 .macro GEN_INT_ENTRY name, virt, ool=0
282 SET_SCRATCH0(r13) /* save r13 */
284 std r9,IAREA+EX_R9(r13) /* save r9 */
287 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
289 std r10,IAREA+EX_R10(r13) /* save r10 */
293 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
294 .elseif ICFAR_IF_HVMODE
296 BEGIN_FTR_SECTION_NESTED(69)
298 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 69)
300 BEGIN_FTR_SECTION_NESTED(69)
302 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 69)
303 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
309 TRAMP_REAL_BEGIN(tramp_real_\name)
313 TRAMP_VIRT_BEGIN(tramp_virt_\name)
318 std r9,IAREA+EX_PPR(r13)
319 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
320 .if ICFAR || ICFAR_IF_HVMODE
322 std r10,IAREA+EX_CFAR(r13)
323 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
327 std r10,IAREA+EX_CTR(r13)
329 std r11,IAREA+EX_R11(r13) /* save r11 - r12 */
330 std r12,IAREA+EX_R12(r13)
333 * DAR/DSISR, SCRATCH0 must be read before setting MSR[RI],
334 * because a d-side MCE will clobber those registers so is
335 * not recoverable if they are live.
338 std r10,IAREA+EX_R13(r13)
345 std r10,IAREA+EX_DAR(r13)
347 .if IDSISR && !IISIDE
349 mfspr r10,SPRN_HDSISR
353 stw r10,IAREA+EX_DSISR(r13)
358 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
359 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
361 mfspr r11,SPRN_SRR0 /* save SRR0 */
362 mfspr r12,SPRN_SRR1 /* and SRR1 */
363 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
365 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
366 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
368 mfspr r11,SPRN_SRR0 /* save SRR0 */
369 mfspr r12,SPRN_SRR1 /* and SRR1 */
372 .if IBRANCH_TO_COMMON
373 GEN_BRANCH_TO_COMMON \name \virt
382 * __GEN_COMMON_ENTRY is required to receive the branch from interrupt
383 * entry, except in the case of the real-mode handlers which require
384 * __GEN_REALMODE_COMMON_ENTRY.
386 * This switches to virtual mode and sets MSR[RI].
388 .macro __GEN_COMMON_ENTRY name
389 DEFINE_FIXED_SYMBOL(\name\()_common_real, text)
390 \name\()_common_real:
392 KVMTEST \name kvm_interrupt
395 ld r10,PACAKMSR(r13) /* get MSR value for kernel */
396 /* MSR[RI] is clear iff using SRR regs */
400 END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
408 b 1f /* skip the virt test coming from real */
411 .balign IFETCH_ALIGN_BYTES
412 DEFINE_FIXED_SYMBOL(\name\()_common_virt, text)
413 \name\()_common_virt:
415 KVMTEST \name kvm_interrupt
422 * Don't switch to virt mode. Used for early MCE and HMI handlers that
423 * want to run in real mode.
425 .macro __GEN_REALMODE_COMMON_ENTRY name
426 DEFINE_FIXED_SYMBOL(\name\()_common_real, text)
427 \name\()_common_real:
429 KVMTEST \name kvm_interrupt
433 .macro __GEN_COMMON_BODY name
436 .error "No support for masked interrupt to use custom stack"
439 /* If coming from user, skip soft-mask tests. */
444 * Kernel code running below __end_soft_masked may be
445 * implicitly soft-masked if it is within the regions
446 * in the soft mask table.
448 LOAD_HANDLER(r10, __end_soft_masked)
452 /* SEARCH_SOFT_MASK_TABLE clobbers r9,r10,r12 */
454 stw r9,PACA_EXGEN+EX_CCR(r13)
455 SEARCH_SOFT_MASK_TABLE
457 mfctr r12 /* Restore r12 to SRR1 */
458 lwz r9,PACA_EXGEN+EX_CCR(r13)
459 beq 1f /* Not in soft-mask table */
461 b 2f /* In soft-mask table, always mask */
463 /* Test the soft mask state against our interrupt's bit */
464 1: lbz r10,PACAIRQSOFTMASK(r13)
465 2: andi. r10,r10,IMASK
466 /* Associate vector numbers with bits in paca->irq_happened */
467 .if IVEC == 0x500 || IVEC == 0xea0
469 .elseif IVEC == 0x900
471 .elseif IVEC == 0xa00 || IVEC == 0xe80
472 li r10,PACA_IRQ_DBELL
473 .elseif IVEC == 0xe60
475 .elseif IVEC == 0xf00
478 .abort "Bad maskable vector"
483 bne masked_Hinterrupt
486 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
488 bne masked_Hinterrupt
495 andi. r10,r12,MSR_PR /* See if coming from user */
496 3: mr r10,r1 /* Save r1 */
497 subi r1,r1,INT_FRAME_SIZE /* alloc frame on kernel stack */
499 ld r1,PACAKSAVE(r13) /* kernel stack to use */
500 100: tdgei r1,-INT_FRAME_SIZE /* trap if r1 is in userspace */
501 EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,0
504 std r9,_CCR(r1) /* save CR in stackframe */
505 std r11,_NIP(r1) /* save SRR0 in stackframe */
506 std r12,_MSR(r1) /* save SRR1 in stackframe */
507 std r10,0(r1) /* make stack chain pointer */
508 std r0,GPR0(r1) /* save r0 in stackframe */
509 std r10,GPR1(r1) /* save r1 in stackframe */
512 /* Mark our [H]SRRs valid for return */
516 stb r10,PACAHSRR_VALID(r13)
518 stb r10,PACASRR_VALID(r13)
519 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
521 stb r10,PACAHSRR_VALID(r13)
523 stb r10,PACASRR_VALID(r13)
528 kuap_save_amr_and_lock r9, r10, cr1, cr0
530 beq 101f /* if from kernel mode */
532 ld r9,IAREA+EX_PPR(r13) /* Read PPR from paca */
534 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
538 kuap_save_amr_and_lock r9, r10, cr1
542 /* Save original regs values from save area to stack frame. */
543 ld r9,IAREA+EX_R9(r13) /* move r9, r10 to stackframe */
544 ld r10,IAREA+EX_R10(r13)
547 ld r9,IAREA+EX_R11(r13) /* move r11 - r13 to stackframe */
548 ld r10,IAREA+EX_R12(r13)
549 ld r11,IAREA+EX_R13(r13)
566 ld r10,IAREA+EX_DAR(r13)
574 lis r11,DSISR_SRR1_MATCH_64S@h
577 lwz r10,IAREA+EX_DSISR(r13)
583 .if ICFAR || ICFAR_IF_HVMODE
584 ld r10,IAREA+EX_CFAR(r13)
588 std r10,ORIG_GPR3(r1)
589 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
590 ld r10,IAREA+EX_CTR(r13)
592 SAVE_GPRS(2, 8, r1) /* save r2 - r8 in stackframe */
594 mflr r9 /* Get LR, later save to stack */
595 LOAD_PACA_TOC() /* get kernel TOC into r2 */
597 lbz r10,PACAIRQSOFTMASK(r13)
598 mfspr r11,SPRN_XER /* save XER in stackframe */
602 std r9,_TRAP(r1) /* set trap number */
604 LOAD_REG_IMMEDIATE(r11, STACK_FRAME_REGS_MARKER)
605 std r10,RESULT(r1) /* clear regs->result */
606 std r11,STACK_INT_FRAME_MARKER(r1) /* mark the frame */
610 * On entry r13 points to the paca, r9-r13 are saved in the paca,
611 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
612 * SRR1, and relocation is on.
614 * If stack=0, then the stack is already set in r1, and r1 is saved in r10.
615 * PPR save and CPU accounting is not done for the !stack case (XXX why not?)
617 .macro GEN_COMMON name
618 __GEN_COMMON_ENTRY \name
619 __GEN_COMMON_BODY \name
622 .macro SEARCH_RESTART_TABLE
623 #ifdef CONFIG_RELOCATABLE
626 LOAD_REG_ADDR(r9, __start___restart_table)
627 LOAD_REG_ADDR(r10, __stop___restart_table)
630 LOAD_REG_IMMEDIATE_SYM(r9, r12, __start___restart_table)
631 LOAD_REG_IMMEDIATE_SYM(r10, r12, __stop___restart_table)
652 .macro SEARCH_SOFT_MASK_TABLE
653 #ifdef CONFIG_RELOCATABLE
656 LOAD_REG_ADDR(r9, __start___soft_mask_table)
657 LOAD_REG_ADDR(r10, __stop___soft_mask_table)
660 LOAD_REG_IMMEDIATE_SYM(r9, r12, __start___soft_mask_table)
661 LOAD_REG_IMMEDIATE_SYM(r10, r12, __stop___soft_mask_table)
683 * Restore all registers including H/SRR0/1 saved in a stack frame of a
684 * standard exception.
686 .macro EXCEPTION_RESTORE_REGS hsrr=0
687 /* Move original SRR0 and SRR1 into the respective regs */
692 stb r10,PACAHSRR_VALID(r13)
695 stb r10,PACASRR_VALID(r13)
711 SANITIZE_RESTORE_NVGPRS()
714 /* restore original r1. */
719 * EARLY_BOOT_FIXUP - Fix real-mode interrupt with wrong endian in early boot.
721 * There's a short window during boot where although the kernel is running
722 * little endian, any exceptions will cause the CPU to switch back to big
723 * endian. For example a WARN() boils down to a trap instruction, which will
724 * cause a program check, and we end up here but with the CPU in big endian
725 * mode. The first instruction of the program check handler (in GEN_INT_ENTRY
726 * below) is an mtsprg, which when executed in the wrong endian is an lhzu with
727 * a ~3GB displacement from r3. The content of r3 is random, so that is a load
728 * from some random location, and depending on the system can easily lead to a
729 * checkstop, or an infinitely recursive page fault.
731 * So to handle that case we have a trampoline here that can detect we are in
732 * the wrong endian and flip us back to the correct endian. We can't flip
733 * MSR[LE] using mtmsr, so we have to use rfid. That requires backing up SRR0/1
734 * as well as a GPR. To do that we use SPRG0/2/3, as SPRG1 is already used for
735 * the paca. SPRG3 is user readable, but this trampoline is only active very
736 * early in boot, and SPRG3 will be reinitialised in vdso_getcpu_init() before
739 .macro EARLY_BOOT_FIXUP
741 #ifdef CONFIG_CPU_LITTLE_ENDIAN
742 tdi 0,0,0x48 // Trap never, or in reverse endian: b . + 8
743 b 2f // Skip trampoline if endian is correct
744 .long 0xa643707d // mtsprg 0, r11 Backup r11
745 .long 0xa6027a7d // mfsrr0 r11
746 .long 0xa643727d // mtsprg 2, r11 Backup SRR0 in SPRG2
747 .long 0xa6027b7d // mfsrr1 r11
748 .long 0xa643737d // mtsprg 3, r11 Backup SRR1 in SPRG3
749 .long 0xa600607d // mfmsr r11
750 .long 0x01006b69 // xori r11, r11, 1 Invert MSR[LE]
751 .long 0xa6037b7d // mtsrr1 r11
753 * This is 'li r11,1f' where 1f is the absolute address of that
754 * label, byteswapped into the SI field of the instruction.
757 ((ABS_ADDR(1f, real_vectors) & 0x00ff) << 24) | \
758 ((ABS_ADDR(1f, real_vectors) & 0xff00) << 8)
759 .long 0xa6037a7d // mtsrr0 r11
760 .long 0x2400004c // rfid
763 mtsrr1 r11 // Restore SRR1
765 mtsrr0 r11 // Restore SRR0
766 mfsprg r11, 0 // Restore r11
770 * program check could hit at any time, and pseries can not block
771 * MSR[ME] in early boot. So check if there is anything useful in r13
772 * yet, and spin forever if not.
780 END_FTR_SECTION(0, 1) // nop out after boot
784 * There are a few constraints to be concerned with.
785 * - Real mode exceptions code/data must be located at their physical location.
786 * - Virtual mode exceptions must be mapped at their 0xc000... location.
787 * - Fixed location code must not call directly beyond the __end_interrupts
788 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
790 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
792 * - Conditional branch targets must be within +/-32K of caller.
794 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
795 * therefore don't have to run in physically located code or rfid to
796 * virtual mode kernel code. However on relocatable kernels they do have
797 * to branch to KERNELBASE offset because the rest of the kernel (outside
798 * the exception vectors) may be located elsewhere.
800 * Virtual exceptions correspond with physical, except their entry points
801 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
802 * offset applied. Virtual exceptions are enabled with the Alternate
803 * Interrupt Location (AIL) bit set in the LPCR. However this does not
804 * guarantee they will be delivered virtually. Some conditions (see the ISA)
805 * cause exceptions to be delivered in real mode.
807 * The scv instructions are a special case. They get a 0x3000 offset applied.
808 * scv exceptions have unique reentrancy properties, see below.
810 * It's impossible to receive interrupts below 0x300 via AIL.
812 * KVM: None of the virtual exceptions are from the guest. Anything that
813 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
816 * We layout physical memory as follows:
817 * 0x0000 - 0x00ff : Secondary processor spin code
818 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
819 * 0x1900 - 0x2fff : Real mode trampolines
820 * 0x3000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
821 * 0x5900 - 0x6fff : Relon mode trampolines
822 * 0x7000 - 0x7fff : FWNMI data area
823 * 0x8000 - .... : Common interrupt handlers, remaining early
824 * setup code, rest of kernel.
826 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
827 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
830 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
831 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x3000)
832 OPEN_FIXED_SECTION(virt_vectors, 0x3000, 0x5900)
833 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
835 #ifdef CONFIG_PPC_POWERNV
836 .globl start_real_trampolines
837 .globl end_real_trampolines
838 .globl start_virt_trampolines
839 .globl end_virt_trampolines
842 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
844 * Data area reserved for FWNMI option.
845 * This address (0x7000) is fixed by the RPA.
846 * pseries and powernv need to keep the whole page from
847 * 0x7000 to 0x8000 free for use by the firmware
849 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
850 OPEN_TEXT_SECTION(0x8000)
852 OPEN_TEXT_SECTION(0x7000)
855 USE_FIXED_SECTION(real_vectors)
858 * This is the start of the interrupt handlers for pSeries
859 * This code runs with relocation off.
860 * Code from here to __end_interrupts gets copied down to real
861 * address 0x100 when we are running a relocatable kernel.
862 * Therefore any relative branches in this section must only
863 * branch to labels in this section.
865 .globl __start_interrupts
869 * Interrupt 0x3000 - System Call Vectored Interrupt (syscall).
870 * This is a synchronous interrupt invoked with the "scv" instruction. The
871 * system call does not alter the HV bit, so it is directed to the OS.
874 * scv instructions enter the kernel without changing EE, RI, ME, or HV.
875 * In particular, this means we can take a maskable interrupt at any point
876 * in the scv handler, which is unlike any other interrupt. This is solved
877 * by treating the instruction addresses in the handler as being soft-masked,
878 * by adding a SOFT_MASK_TABLE entry for them.
880 * AIL-0 mode scv exceptions go to 0x17000-0x17fff, but we set AIL-3 and
881 * ensure scv is never executed with relocation off, which means AIL-0
882 * should never happen.
884 * Before leaving the following inside-__end_soft_masked text, at least of the
885 * following must be true:
886 * - MSR[PR]=1 (i.e., return to userspace)
887 * - MSR_EE|MSR_RI is clear (no reentrant exceptions)
888 * - Standard kernel environment is set up (stack, paca, etc)
891 * These interrupts do not elevate HV 0->1, so HV is not involved. PR KVM
892 * ensures that FSCR[SCV] is disabled whenever it has to force AIL off.
896 * syscall register convention is in Documentation/arch/powerpc/syscall64-abi.rst
898 EXC_VIRT_BEGIN(system_call_vectored, 0x3000, 0x1000)
904 li r10,IRQS_ALL_DISABLED
905 stb r10,PACAIRQSOFTMASK(r13)
906 #ifdef CONFIG_RELOCATABLE
907 b system_call_vectored_tramp
909 b system_call_vectored_common
919 li r10,IRQS_ALL_DISABLED
920 stb r10,PACAIRQSOFTMASK(r13)
921 li r0,-1 /* cause failure */
922 #ifdef CONFIG_RELOCATABLE
923 b system_call_vectored_sigill_tramp
925 b system_call_vectored_sigill
928 EXC_VIRT_END(system_call_vectored, 0x3000, 0x1000)
930 // Treat scv vectors as soft-masked, see comment above.
931 // Use absolute values rather than labels here, so they don't get relocated,
932 // because this code runs unrelocated.
933 SOFT_MASK_TABLE(0xc000000000003000, 0xc000000000004000)
935 #ifdef CONFIG_RELOCATABLE
936 TRAMP_VIRT_BEGIN(system_call_vectored_tramp)
937 __LOAD_HANDLER(r10, system_call_vectored_common, virt_trampolines)
941 TRAMP_VIRT_BEGIN(system_call_vectored_sigill_tramp)
942 __LOAD_HANDLER(r10, system_call_vectored_sigill, virt_trampolines)
948 /* No virt vectors corresponding with 0x0..0x100 */
949 EXC_VIRT_NONE(0x4000, 0x100)
953 * Interrupt 0x100 - System Reset Interrupt (SRESET aka NMI).
954 * This is a non-maskable, asynchronous interrupt always taken in real-mode.
956 * - Wake from power-saving state, on powernv.
957 * - An NMI from another CPU, triggered by firmware or hypercall.
958 * - As crash/debug signal injected from BMC, firmware or hypervisor.
961 * Power-save wakeup is the only performance critical path, so this is
962 * determined quickly as possible first. In this case volatile registers
963 * can be discarded and SPRs like CFAR don't need to be read.
965 * If not a powersave wakeup, then it's run as a regular interrupt, however
966 * it uses its own stack and PACA save area to preserve the regular kernel
967 * environment for debugging.
969 * This interrupt is not maskable, so triggering it when MSR[RI] is clear,
970 * or SCRATCH0 is in use, etc. may cause a crash. It's also not entirely
971 * correct to switch to virtual mode to run the regular interrupt handler
972 * because it might be interrupted when the MMU is in a bad state (e.g., SLB
976 * PAPR specifies a "fwnmi" facility which sends the sreset to a different
977 * entry point with a different register set up. Some hypervisors will
978 * send the sreset to 0x100 in the guest if it is not fwnmi capable.
981 * Unlike most SRR interrupts, this may be taken by the host while executing
982 * in a guest, so a KVM test is required. KVM will pull the CPU out of guest
983 * mode and then raise the sreset.
985 INT_DEFINE_BEGIN(system_reset)
988 IVIRT=0 /* no virt entry point */
991 INT_DEFINE_END(system_reset)
993 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
994 #ifdef CONFIG_PPC_P7_NAP
996 * If running native on arch 2.06 or later, check if we are waking up
997 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1
998 * bits 46:47. A non-0 value indicates that we are coming from a power
999 * saving state. The idle wakeup handler initially runs in real mode,
1000 * but we branch to the 0xc000... address so we can turn on relocation
1001 * with mtmsrd later, after SPRs are restored.
1003 * Careful to minimise cost for the fast path (idle wakeup) while
1004 * also avoiding clobbering CFAR for the debug path (non-idle).
1006 * For the idle wake case volatile registers can be clobbered, which
1007 * is why we use those initially. If it turns out to not be an idle
1008 * wake, carefully put everything back the way it was, so we can use
1009 * common exception macros to handle it.
1014 std r3,PACA_EXNMI+0*8(r13)
1015 std r4,PACA_EXNMI+1*8(r13)
1016 std r5,PACA_EXNMI+2*8(r13)
1019 rlwinm. r5,r3,47-31,30,31
1020 bne+ system_reset_idle_wake
1021 /* Not powersave wakeup. Restore regs for regular interrupt handler. */
1023 ld r3,PACA_EXNMI+0*8(r13)
1024 ld r4,PACA_EXNMI+1*8(r13)
1025 ld r5,PACA_EXNMI+2*8(r13)
1027 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
1030 GEN_INT_ENTRY system_reset, virt=0
1032 * In theory, we should not enable relocation here if it was disabled
1033 * in SRR1, because the MMU may not be configured to support it (e.g.,
1034 * SLB may have been cleared). In practice, there should only be a few
1035 * small windows where that's the case, and sreset is considered to
1036 * be dangerous anyway.
1038 EXC_REAL_END(system_reset, 0x100, 0x100)
1039 EXC_VIRT_NONE(0x4100, 0x100)
1041 #ifdef CONFIG_PPC_P7_NAP
1042 TRAMP_REAL_BEGIN(system_reset_idle_wake)
1043 /* We are waking up from idle, so may clobber any volatile register */
1045 bltlr cr1 /* no state loss, return to idle caller with r3=SRR1 */
1046 __LOAD_FAR_HANDLER(r12, DOTSYM(idle_return_gpr_loss), real_trampolines)
1051 #ifdef CONFIG_PPC_PSERIES
1053 * Vectors for the FWNMI option. Share common code.
1055 TRAMP_REAL_BEGIN(system_reset_fwnmi)
1056 GEN_INT_ENTRY system_reset, virt=0
1058 #endif /* CONFIG_PPC_PSERIES */
1060 EXC_COMMON_BEGIN(system_reset_common)
1061 __GEN_COMMON_ENTRY system_reset
1063 * Increment paca->in_nmi. When the interrupt entry wrapper later
1064 * enable MSR_RI, then SLB or MCE will be able to recover, but a nested
1065 * NMI will notice in_nmi and not recover because of the use of the NMI
1066 * stack. in_nmi reentrancy is tested in system_reset_exception.
1068 lhz r10,PACA_IN_NMI(r13)
1070 sth r10,PACA_IN_NMI(r13)
1073 ld r1,PACA_NMI_EMERG_SP(r13)
1074 subi r1,r1,INT_FRAME_SIZE
1075 __GEN_COMMON_BODY system_reset
1077 addi r3,r1,STACK_INT_FRAME_REGS
1078 bl CFUNC(system_reset_exception)
1080 /* Clear MSR_RI before setting SRR0 and SRR1. */
1085 * MSR_RI is clear, now we can decrement paca->in_nmi.
1087 lhz r10,PACA_IN_NMI(r13)
1089 sth r10,PACA_IN_NMI(r13)
1091 kuap_kernel_restore r9, r10
1092 EXCEPTION_RESTORE_REGS
1093 RFI_TO_USER_OR_KERNEL
1097 * Interrupt 0x200 - Machine Check Interrupt (MCE).
1098 * This is a non-maskable interrupt always taken in real-mode. It can be
1099 * synchronous or asynchronous, caused by hardware or software, and it may be
1100 * taken in a power-saving state.
1103 * Similarly to system reset, this uses its own stack and PACA save area,
1104 * the difference is re-entrancy is allowed on the machine check stack.
1106 * machine_check_early is run in real mode, and carefully decodes the
1107 * machine check and tries to handle it (e.g., flush the SLB if there was an
1108 * error detected there), determines if it was recoverable and logs the
1111 * This early code does not "reconcile" irq soft-mask state like SRESET or
1112 * regular interrupts do, so irqs_disabled() among other things may not work
1113 * properly (irq disable/enable already doesn't work because irq tracing can
1114 * not work in real mode).
1116 * Then, depending on the execution context when the interrupt is taken, there
1117 * are 3 main actions:
1118 * - Executing in kernel mode. The event is queued with irq_work, which means
1119 * it is handled when it is next safe to do so (i.e., the kernel has enabled
1120 * interrupts), which could be immediately when the interrupt returns. This
1121 * avoids nasty issues like switching to virtual mode when the MMU is in a
1122 * bad state, or when executing OPAL code. (SRESET is exposed to such issues,
1123 * but it has different priorities). Check to see if the CPU was in power
1124 * save, and return via the wake up code if it was.
1126 * - Executing in user mode. machine_check_exception is run like a normal
1127 * interrupt handler, which processes the data generated by the early handler.
1129 * - Executing in guest mode. The interrupt is run with its KVM test, and
1130 * branches to KVM to deal with. KVM may queue the event for the host
1133 * This interrupt is not maskable, so if it triggers when MSR[RI] is clear,
1134 * or SCRATCH0 is in use, it may cause a crash.
1139 INT_DEFINE_BEGIN(machine_check_early)
1142 IVIRT=0 /* no virt entry point */
1147 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */
1148 INT_DEFINE_END(machine_check_early)
1150 INT_DEFINE_BEGIN(machine_check)
1153 IVIRT=0 /* no virt entry point */
1157 INT_DEFINE_END(machine_check)
1159 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
1161 GEN_INT_ENTRY machine_check_early, virt=0
1162 EXC_REAL_END(machine_check, 0x200, 0x100)
1163 EXC_VIRT_NONE(0x4200, 0x100)
1165 #ifdef CONFIG_PPC_PSERIES
1166 TRAMP_REAL_BEGIN(machine_check_fwnmi)
1167 /* See comment at machine_check exception, don't turn on RI */
1168 GEN_INT_ENTRY machine_check_early, virt=0
1171 #define MACHINE_CHECK_HANDLER_WINDUP \
1172 /* Clear MSR_RI before setting SRR0 and SRR1. */\
1174 mtmsrd r9,1; /* Clear MSR_RI */ \
1175 /* Decrement paca->in_mce now RI is clear. */ \
1176 lhz r12,PACA_IN_MCE(r13); \
1178 sth r12,PACA_IN_MCE(r13); \
1179 EXCEPTION_RESTORE_REGS
1181 EXC_COMMON_BEGIN(machine_check_early_common)
1182 __GEN_REALMODE_COMMON_ENTRY machine_check_early
1185 * Switch to mc_emergency stack and handle re-entrancy (we limit
1186 * the nested MCE upto level 4 to avoid stack overflow).
1187 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
1189 * We use paca->in_mce to check whether this is the first entry or
1190 * nested machine check. We increment paca->in_mce to track nested
1193 * If this is the first entry then set stack pointer to
1194 * paca->mc_emergency_sp, otherwise r1 is already pointing to
1195 * stack frame on mc_emergency stack.
1197 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
1198 * checkstop if we get another machine check exception before we do
1199 * rfid with MSR_ME=1.
1201 * This interrupt can wake directly from idle. If that is the case,
1202 * the machine check is handled then the idle wakeup code is called
1205 lhz r10,PACA_IN_MCE(r13)
1206 cmpwi r10,0 /* Are we in nested machine check */
1207 cmpwi cr1,r10,MAX_MCE_DEPTH /* Are we at maximum nesting */
1208 addi r10,r10,1 /* increment paca->in_mce */
1209 sth r10,PACA_IN_MCE(r13)
1211 mr r10,r1 /* Save r1 */
1213 /* First machine check entry */
1214 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
1215 1: /* Limit nested MCE to level 4 to avoid stack overflow */
1216 bgt cr1,unrecoverable_mce /* Check if we hit limit of 4 */
1217 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1219 __GEN_COMMON_BODY machine_check_early
1222 bl enable_machine_check
1223 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1224 addi r3,r1,STACK_INT_FRAME_REGS
1226 bl CFUNC(machine_check_early_boot)
1227 END_FTR_SECTION(0, 1) // nop out after boot
1228 bl CFUNC(machine_check_early)
1229 std r3,RESULT(r1) /* Save result */
1232 #ifdef CONFIG_PPC_P7_NAP
1234 * Check if thread was in power saving mode. We come here when any
1235 * of the following is true:
1236 * a. thread wasn't in power saving mode
1237 * b. thread was in power saving mode with no state loss,
1238 * supervisor state loss or hypervisor state loss.
1240 * Go back to nap/sleep/winkle mode again if (b) is true.
1243 rlwinm. r11,r12,47-31,30,31
1244 bne machine_check_idle_common
1245 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
1248 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1250 * Check if we are coming from guest. If yes, then run the normal
1251 * exception handler which will take the
1252 * machine_check_kvm->kvm_interrupt branch to deliver the MC event
1255 lbz r11,HSTATE_IN_GUEST(r13)
1256 cmpwi r11,0 /* Check if coming from guest */
1257 bne mce_deliver /* continue if we are. */
1261 * Check if we are coming from userspace. If yes, then run the normal
1262 * exception handler which will deliver the MC event to this kernel.
1264 andi. r11,r12,MSR_PR /* See if coming from user. */
1265 bne mce_deliver /* continue in V mode if we are. */
1268 * At this point we are coming from kernel context.
1269 * Queue up the MCE event and return from the interrupt.
1270 * But before that, check if this is an un-recoverable exception.
1271 * If yes, then stay on emergency stack and panic.
1273 andi. r11,r12,MSR_RI
1274 beq unrecoverable_mce
1277 * Check if we have successfully handled/recovered from error, if not
1278 * then stay on emergency stack and panic.
1280 ld r3,RESULT(r1) /* Load result */
1281 cmpdi r3,0 /* see if we handled MCE successfully */
1282 beq unrecoverable_mce /* if !handled then panic */
1285 * Return from MC interrupt.
1286 * Queue up the MCE event so that we can log it later, while
1287 * returning from kernel or opal call.
1289 bl CFUNC(machine_check_queue_event)
1290 MACHINE_CHECK_HANDLER_WINDUP
1295 * This is a host user or guest MCE. Restore all registers, then
1296 * run the "late" handler. For host user, this will run the
1297 * machine_check_exception handler in virtual mode like a normal
1298 * interrupt handler. For guest, this will trigger the KVM test
1299 * and branch to the KVM interrupt similarly to other interrupts.
1302 ld r10,ORIG_GPR3(r1)
1304 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1305 MACHINE_CHECK_HANDLER_WINDUP
1306 GEN_INT_ENTRY machine_check, virt=0
1308 EXC_COMMON_BEGIN(machine_check_common)
1310 * Machine check is different because we use a different
1311 * save area: PACA_EXMC instead of PACA_EXGEN.
1313 GEN_COMMON machine_check
1314 addi r3,r1,STACK_INT_FRAME_REGS
1315 bl CFUNC(machine_check_exception_async)
1316 b interrupt_return_srr
1319 #ifdef CONFIG_PPC_P7_NAP
1321 * This is an idle wakeup. Low level machine check has already been
1322 * done. Queue the event then call the idle code to do the wake up.
1324 EXC_COMMON_BEGIN(machine_check_idle_common)
1325 bl CFUNC(machine_check_queue_event)
1328 * GPR-loss wakeups are relatively straightforward, because the
1329 * idle sleep code has saved all non-volatile registers on its
1330 * own stack, and r1 in PACAR1.
1332 * For no-loss wakeups the r1 and lr registers used by the
1333 * early machine check handler have to be restored first. r2 is
1334 * the kernel TOC, so no need to restore it.
1336 * Then decrement MCE nesting after finishing with the stack.
1342 lhz r11,PACA_IN_MCE(r13)
1344 sth r11,PACA_IN_MCE(r13)
1347 rlwinm r10,r3,47-31,30,31
1349 bltlr cr1 /* no state loss, return to idle caller with r3=SRR1 */
1350 b idle_return_gpr_loss
1353 EXC_COMMON_BEGIN(unrecoverable_mce)
1355 * We are going down. But there are chances that we might get hit by
1356 * another MCE during panic path and we may run into unstable state
1357 * with no way out. Hence, turn ME bit off while going down, so that
1358 * when another MCE is hit during panic path, system will checkstop
1359 * and hypervisor will get restarted cleanly by SP.
1362 li r10,0 /* clear MSR_RI */
1364 bl CFUNC(disable_machine_check)
1365 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1366 ld r10,PACAKMSR(r13)
1371 lhz r12,PACA_IN_MCE(r13)
1373 sth r12,PACA_IN_MCE(r13)
1376 * Invoke machine_check_exception to print MCE event and panic.
1377 * This is the NMI version of the handler because we are called from
1378 * the early handler which is a true NMI.
1380 addi r3,r1,STACK_INT_FRAME_REGS
1381 bl CFUNC(machine_check_exception)
1384 * We will not reach here. Even if we did, there is no way out.
1385 * Call unrecoverable_exception and die.
1387 addi r3,r1,STACK_INT_FRAME_REGS
1388 bl CFUNC(unrecoverable_exception)
1393 * Interrupt 0x300 - Data Storage Interrupt (DSI).
1394 * This is a synchronous interrupt generated due to a data access exception,
1395 * e.g., a load orstore which does not have a valid page table entry with
1396 * permissions. DAWR matches also fault here, as do RC updates, and minor misc
1397 * errors e.g., copy/paste, AMO, certain invalid CI accesses, etc.
1401 * Go to do_hash_fault, which attempts to fill the HPT from an entry in the
1402 * Linux page table. Hash faults can hit in kernel mode in a fairly
1403 * arbitrary state (e.g., interrupts disabled, locks held) when accessing
1404 * "non-bolted" regions, e.g., vmalloc space. However these should always be
1405 * backed by Linux page table entries.
1407 * If no entry is found the Linux page fault handler is invoked (by
1408 * do_hash_fault). Linux page faults can happen in kernel mode due to user
1409 * copy operations of course.
1411 * KVM: The KVM HDSI handler may perform a load with MSR[DR]=1 in guest
1412 * MMU context, which may cause a DSI in the host, which must go to the
1413 * KVM handler. MSR[IR] is not enabled, so the real-mode handler will
1414 * always be used regardless of AIL setting.
1417 * The hardware loads from the Linux page table directly, so a fault goes
1418 * immediately to Linux page fault.
1420 * Conditions like DAWR match are handled on the way in to Linux page fault.
1422 INT_DEFINE_BEGIN(data_access)
1427 INT_DEFINE_END(data_access)
1429 EXC_REAL_BEGIN(data_access, 0x300, 0x80)
1430 GEN_INT_ENTRY data_access, virt=0
1431 EXC_REAL_END(data_access, 0x300, 0x80)
1432 EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
1433 GEN_INT_ENTRY data_access, virt=1
1434 EXC_VIRT_END(data_access, 0x4300, 0x80)
1435 EXC_COMMON_BEGIN(data_access_common)
1436 GEN_COMMON data_access
1438 addi r3,r1,STACK_INT_FRAME_REGS
1439 andis. r0,r4,DSISR_DABRMATCH@h
1441 #ifdef CONFIG_PPC_64S_HASH_MMU
1442 BEGIN_MMU_FTR_SECTION
1443 bl CFUNC(do_hash_fault)
1444 MMU_FTR_SECTION_ELSE
1445 bl CFUNC(do_page_fault)
1446 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1448 bl CFUNC(do_page_fault)
1450 b interrupt_return_srr
1452 1: bl CFUNC(do_break)
1454 * do_break() may have changed the NV GPRS while handling a breakpoint.
1455 * If so, we need to restore them with their updated values.
1457 HANDLER_RESTORE_NVGPRS()
1458 b interrupt_return_srr
1462 * Interrupt 0x380 - Data Segment Interrupt (DSLB).
1463 * This is a synchronous interrupt in response to an MMU fault missing SLB
1464 * entry for HPT, or an address outside RPT translation range.
1468 * This refills the SLB, or reports an access fault similarly to a bad page
1469 * fault. When coming from user-mode, the SLB handler may access any kernel
1470 * data, though it may itself take a DSLB. When coming from kernel mode,
1471 * recursive faults must be avoided so access is restricted to the kernel
1472 * image text/data, kernel stack, and any data allocated below
1473 * ppc64_bolted_size (first segment). The kernel handler must avoid stomping
1474 * on user-handler data structures.
1476 * KVM: Same as 0x300, DSLB must test for KVM guest.
1478 INT_DEFINE_BEGIN(data_access_slb)
1482 INT_DEFINE_END(data_access_slb)
1484 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
1485 GEN_INT_ENTRY data_access_slb, virt=0
1486 EXC_REAL_END(data_access_slb, 0x380, 0x80)
1487 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
1488 GEN_INT_ENTRY data_access_slb, virt=1
1489 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
1490 EXC_COMMON_BEGIN(data_access_slb_common)
1491 GEN_COMMON data_access_slb
1492 #ifdef CONFIG_PPC_64S_HASH_MMU
1493 BEGIN_MMU_FTR_SECTION
1494 /* HPT case, do SLB fault */
1495 addi r3,r1,STACK_INT_FRAME_REGS
1496 bl CFUNC(do_slb_fault)
1499 b fast_interrupt_return_srr
1501 MMU_FTR_SECTION_ELSE
1502 /* Radix case, access is outside page table range */
1504 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1509 addi r3,r1,STACK_INT_FRAME_REGS
1510 bl CFUNC(do_bad_segment_interrupt)
1511 b interrupt_return_srr
1515 * Interrupt 0x400 - Instruction Storage Interrupt (ISI).
1516 * This is a synchronous interrupt in response to an MMU fault due to an
1517 * instruction fetch.
1520 * Similar to DSI, though in response to fetch. The faulting address is found
1521 * in SRR0 (rather than DAR), and status in SRR1 (rather than DSISR).
1523 INT_DEFINE_BEGIN(instruction_access)
1528 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1531 INT_DEFINE_END(instruction_access)
1533 EXC_REAL_BEGIN(instruction_access, 0x400, 0x80)
1534 GEN_INT_ENTRY instruction_access, virt=0
1535 EXC_REAL_END(instruction_access, 0x400, 0x80)
1536 EXC_VIRT_BEGIN(instruction_access, 0x4400, 0x80)
1537 GEN_INT_ENTRY instruction_access, virt=1
1538 EXC_VIRT_END(instruction_access, 0x4400, 0x80)
1539 EXC_COMMON_BEGIN(instruction_access_common)
1540 GEN_COMMON instruction_access
1541 addi r3,r1,STACK_INT_FRAME_REGS
1542 #ifdef CONFIG_PPC_64S_HASH_MMU
1543 BEGIN_MMU_FTR_SECTION
1544 bl CFUNC(do_hash_fault)
1545 MMU_FTR_SECTION_ELSE
1546 bl CFUNC(do_page_fault)
1547 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1549 bl CFUNC(do_page_fault)
1551 b interrupt_return_srr
1555 * Interrupt 0x480 - Instruction Segment Interrupt (ISLB).
1556 * This is a synchronous interrupt in response to an MMU fault due to an
1557 * instruction fetch.
1560 * Similar to DSLB, though in response to fetch. The faulting address is found
1561 * in SRR0 (rather than DAR).
1563 INT_DEFINE_BEGIN(instruction_access_slb)
1567 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1570 INT_DEFINE_END(instruction_access_slb)
1572 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
1573 GEN_INT_ENTRY instruction_access_slb, virt=0
1574 EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
1575 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
1576 GEN_INT_ENTRY instruction_access_slb, virt=1
1577 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
1578 EXC_COMMON_BEGIN(instruction_access_slb_common)
1579 GEN_COMMON instruction_access_slb
1580 #ifdef CONFIG_PPC_64S_HASH_MMU
1581 BEGIN_MMU_FTR_SECTION
1582 /* HPT case, do SLB fault */
1583 addi r3,r1,STACK_INT_FRAME_REGS
1584 bl CFUNC(do_slb_fault)
1587 b fast_interrupt_return_srr
1589 MMU_FTR_SECTION_ELSE
1590 /* Radix case, access is outside page table range */
1592 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1597 addi r3,r1,STACK_INT_FRAME_REGS
1598 bl CFUNC(do_bad_segment_interrupt)
1599 b interrupt_return_srr
1603 * Interrupt 0x500 - External Interrupt.
1604 * This is an asynchronous maskable interrupt in response to an "external
1605 * exception" from the interrupt controller or hypervisor (e.g., device
1606 * interrupt). It is maskable in hardware by clearing MSR[EE], and
1607 * soft-maskable with IRQS_DISABLED mask (i.e., local_irq_disable()).
1609 * When running in HV mode, Linux sets up the LPCR[LPES] bit such that
1610 * interrupts are delivered with HSRR registers, guests use SRRs, which
1611 * reqiures IHSRR_IF_HVMODE.
1613 * On bare metal POWER9 and later, Linux sets the LPCR[HVICE] bit such that
1614 * external interrupts are delivered as Hypervisor Virtualization Interrupts
1615 * rather than External Interrupts.
1618 * This calls into Linux IRQ handler. NVGPRs are not saved to reduce overhead,
1619 * because registers at the time of the interrupt are not so important as it is
1622 * If soft masked, the masked handler will note the pending interrupt for
1623 * replay, and clear MSR[EE] in the interrupted context.
1625 * CFAR is not required because this is an asynchronous interrupt that in
1626 * general won't have much bearing on the state of the CPU, with the possible
1627 * exception of crash/debug IPIs, but those are generally moving to use SRESET
1628 * IPIs. Unless this is an HV interrupt and KVM HV is possible, in which case
1629 * it may be exiting the guest and need CFAR to be saved.
1631 INT_DEFINE_BEGIN(hardware_interrupt)
1638 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
1641 INT_DEFINE_END(hardware_interrupt)
1643 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
1644 GEN_INT_ENTRY hardware_interrupt, virt=0
1645 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
1646 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
1647 GEN_INT_ENTRY hardware_interrupt, virt=1
1648 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
1649 EXC_COMMON_BEGIN(hardware_interrupt_common)
1650 GEN_COMMON hardware_interrupt
1651 addi r3,r1,STACK_INT_FRAME_REGS
1654 b interrupt_return_hsrr
1656 b interrupt_return_srr
1657 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
1661 * Interrupt 0x600 - Alignment Interrupt
1662 * This is a synchronous interrupt in response to data alignment fault.
1664 INT_DEFINE_BEGIN(alignment)
1668 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1671 INT_DEFINE_END(alignment)
1673 EXC_REAL_BEGIN(alignment, 0x600, 0x100)
1674 GEN_INT_ENTRY alignment, virt=0
1675 EXC_REAL_END(alignment, 0x600, 0x100)
1676 EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
1677 GEN_INT_ENTRY alignment, virt=1
1678 EXC_VIRT_END(alignment, 0x4600, 0x100)
1679 EXC_COMMON_BEGIN(alignment_common)
1680 GEN_COMMON alignment
1681 addi r3,r1,STACK_INT_FRAME_REGS
1682 bl CFUNC(alignment_exception)
1683 HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
1684 b interrupt_return_srr
1688 * Interrupt 0x700 - Program Interrupt (program check).
1689 * This is a synchronous interrupt in response to various instruction faults:
1690 * traps, privilege errors, TM errors, floating point exceptions.
1693 * This interrupt may use the "emergency stack" in some cases when being taken
1694 * from kernel context, which complicates handling.
1696 INT_DEFINE_BEGIN(program_check)
1698 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1701 INT_DEFINE_END(program_check)
1703 EXC_REAL_BEGIN(program_check, 0x700, 0x100)
1705 GEN_INT_ENTRY program_check, virt=0
1706 EXC_REAL_END(program_check, 0x700, 0x100)
1707 EXC_VIRT_BEGIN(program_check, 0x4700, 0x100)
1708 GEN_INT_ENTRY program_check, virt=1
1709 EXC_VIRT_END(program_check, 0x4700, 0x100)
1710 EXC_COMMON_BEGIN(program_check_common)
1711 __GEN_COMMON_ENTRY program_check
1714 * It's possible to receive a TM Bad Thing type program check with
1715 * userspace register values (in particular r1), but with SRR1 reporting
1716 * that we came from the kernel. Normally that would confuse the bad
1717 * stack logic, and we would report a bad kernel stack pointer. Instead
1718 * we switch to the emergency stack if we're taking a TM Bad Thing from
1722 andi. r10,r12,MSR_PR
1723 bne .Lnormal_stack /* If userspace, go normal path */
1725 andis. r10,r12,(SRR1_PROGTM)@h
1726 bne .Lemergency_stack /* If TM, emergency */
1728 cmpdi r1,-INT_FRAME_SIZE /* check if r1 is in userspace */
1729 blt .Lnormal_stack /* normal path if not */
1731 /* Use the emergency stack */
1733 andi. r10,r12,MSR_PR /* Set CR0 correctly for label */
1734 /* 3 in EXCEPTION_PROLOG_COMMON */
1735 mr r10,r1 /* Save r1 */
1736 ld r1,PACAEMERGSP(r13) /* Use emergency stack */
1737 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1738 __ISTACK(program_check)=0
1739 __GEN_COMMON_BODY program_check
1740 b .Ldo_program_check
1743 __ISTACK(program_check)=1
1744 __GEN_COMMON_BODY program_check
1747 addi r3,r1,STACK_INT_FRAME_REGS
1748 bl CFUNC(program_check_exception)
1749 HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
1750 b interrupt_return_srr
1754 * Interrupt 0x800 - Floating-Point Unavailable Interrupt.
1755 * This is a synchronous interrupt in response to executing an fp instruction
1759 * This will load FP registers and enable the FP bit if coming from userspace,
1760 * otherwise report a bad kernel use of FP.
1762 INT_DEFINE_BEGIN(fp_unavailable)
1764 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1768 INT_DEFINE_END(fp_unavailable)
1770 EXC_REAL_BEGIN(fp_unavailable, 0x800, 0x100)
1771 GEN_INT_ENTRY fp_unavailable, virt=0
1772 EXC_REAL_END(fp_unavailable, 0x800, 0x100)
1773 EXC_VIRT_BEGIN(fp_unavailable, 0x4800, 0x100)
1774 GEN_INT_ENTRY fp_unavailable, virt=1
1775 EXC_VIRT_END(fp_unavailable, 0x4800, 0x100)
1776 EXC_COMMON_BEGIN(fp_unavailable_common)
1777 GEN_COMMON fp_unavailable
1778 bne 1f /* if from user, just load it up */
1779 addi r3,r1,STACK_INT_FRAME_REGS
1780 bl CFUNC(kernel_fp_unavailable_exception)
1782 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
1784 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1786 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1787 * transaction), go do TM stuff
1789 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1791 END_FTR_SECTION_IFSET(CPU_FTR_TM)
1793 bl CFUNC(load_up_fpu)
1794 b fast_interrupt_return_srr
1795 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1796 2: /* User process was in a transaction */
1797 addi r3,r1,STACK_INT_FRAME_REGS
1798 bl CFUNC(fp_unavailable_tm)
1799 b interrupt_return_srr
1804 * Interrupt 0x900 - Decrementer Interrupt.
1805 * This is an asynchronous interrupt in response to a decrementer exception
1806 * (e.g., DEC has wrapped below zero). It is maskable in hardware by clearing
1807 * MSR[EE], and soft-maskable with IRQS_DISABLED mask (i.e.,
1808 * local_irq_disable()).
1811 * This calls into Linux timer handler. NVGPRs are not saved (see 0x500).
1813 * If soft masked, the masked handler will note the pending interrupt for
1814 * replay, and bump the decrementer to a high value, leaving MSR[EE] enabled
1815 * in the interrupted context.
1816 * If PPC_WATCHDOG is configured, the soft masked handler will actually set
1817 * things back up to run soft_nmi_interrupt as a regular interrupt handler
1818 * on the emergency stack.
1820 * CFAR is not required because this is asynchronous (see hardware_interrupt).
1821 * A watchdog interrupt may like to have CFAR, but usually the interesting
1822 * branch is long gone by that point (e.g., infinite loop).
1824 INT_DEFINE_BEGIN(decrementer)
1827 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1831 INT_DEFINE_END(decrementer)
1833 EXC_REAL_BEGIN(decrementer, 0x900, 0x80)
1834 GEN_INT_ENTRY decrementer, virt=0
1835 EXC_REAL_END(decrementer, 0x900, 0x80)
1836 EXC_VIRT_BEGIN(decrementer, 0x4900, 0x80)
1837 GEN_INT_ENTRY decrementer, virt=1
1838 EXC_VIRT_END(decrementer, 0x4900, 0x80)
1839 EXC_COMMON_BEGIN(decrementer_common)
1840 GEN_COMMON decrementer
1841 addi r3,r1,STACK_INT_FRAME_REGS
1842 bl CFUNC(timer_interrupt)
1843 b interrupt_return_srr
1847 * Interrupt 0x980 - Hypervisor Decrementer Interrupt.
1848 * This is an asynchronous interrupt, similar to 0x900 but for the HDEC
1852 * Linux does not use this outside KVM where it's used to keep a host timer
1853 * while the guest is given control of DEC. It should normally be caught by
1854 * the KVM test and routed there.
1856 INT_DEFINE_BEGIN(hdecrementer)
1862 INT_DEFINE_END(hdecrementer)
1864 EXC_REAL_BEGIN(hdecrementer, 0x980, 0x80)
1865 GEN_INT_ENTRY hdecrementer, virt=0
1866 EXC_REAL_END(hdecrementer, 0x980, 0x80)
1867 EXC_VIRT_BEGIN(hdecrementer, 0x4980, 0x80)
1868 GEN_INT_ENTRY hdecrementer, virt=1
1869 EXC_VIRT_END(hdecrementer, 0x4980, 0x80)
1870 EXC_COMMON_BEGIN(hdecrementer_common)
1871 __GEN_COMMON_ENTRY hdecrementer
1873 * Hypervisor decrementer interrupts not caught by the KVM test
1874 * shouldn't occur but are sometimes left pending on exit from a KVM
1875 * guest. We don't need to do anything to clear them, as they are
1878 * Be careful to avoid touching the kernel stack.
1881 stb r10,PACAHSRR_VALID(r13)
1882 ld r10,PACA_EXGEN+EX_CTR(r13)
1885 ld r9,PACA_EXGEN+EX_R9(r13)
1886 ld r10,PACA_EXGEN+EX_R10(r13)
1887 ld r11,PACA_EXGEN+EX_R11(r13)
1888 ld r12,PACA_EXGEN+EX_R12(r13)
1889 ld r13,PACA_EXGEN+EX_R13(r13)
1894 * Interrupt 0xa00 - Directed Privileged Doorbell Interrupt.
1895 * This is an asynchronous interrupt in response to a msgsndp doorbell.
1896 * It is maskable in hardware by clearing MSR[EE], and soft-maskable with
1897 * IRQS_DISABLED mask (i.e., local_irq_disable()).
1900 * Guests may use this for IPIs between threads in a core if the
1901 * hypervisor supports it. NVGPRS are not saved (see 0x500).
1903 * If soft masked, the masked handler will note the pending interrupt for
1904 * replay, leaving MSR[EE] enabled in the interrupted context because the
1905 * doorbells are edge triggered.
1907 * CFAR is not required, similarly to hardware_interrupt.
1909 INT_DEFINE_BEGIN(doorbell_super)
1912 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1916 INT_DEFINE_END(doorbell_super)
1918 EXC_REAL_BEGIN(doorbell_super, 0xa00, 0x100)
1919 GEN_INT_ENTRY doorbell_super, virt=0
1920 EXC_REAL_END(doorbell_super, 0xa00, 0x100)
1921 EXC_VIRT_BEGIN(doorbell_super, 0x4a00, 0x100)
1922 GEN_INT_ENTRY doorbell_super, virt=1
1923 EXC_VIRT_END(doorbell_super, 0x4a00, 0x100)
1924 EXC_COMMON_BEGIN(doorbell_super_common)
1925 GEN_COMMON doorbell_super
1926 addi r3,r1,STACK_INT_FRAME_REGS
1927 #ifdef CONFIG_PPC_DOORBELL
1928 bl CFUNC(doorbell_exception)
1930 bl CFUNC(unknown_async_exception)
1932 b interrupt_return_srr
1935 EXC_REAL_NONE(0xb00, 0x100)
1936 EXC_VIRT_NONE(0x4b00, 0x100)
1939 * Interrupt 0xc00 - System Call Interrupt (syscall, hcall).
1940 * This is a synchronous interrupt invoked with the "sc" instruction. The
1941 * system call is invoked with "sc 0" and does not alter the HV bit, so it
1942 * is directed to the currently running OS. The hypercall is invoked with
1943 * "sc 1" and it sets HV=1, so it elevates to hypervisor.
1945 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
1946 * 0x4c00 virtual mode.
1949 * If the KVM test fires then it was due to a hypercall and is accordingly
1950 * routed to KVM. Otherwise this executes a normal Linux system call.
1954 * syscall and hypercalls register conventions are documented in
1955 * Documentation/arch/powerpc/syscall64-abi.rst and
1956 * Documentation/arch/powerpc/papr_hcalls.rst respectively.
1958 * The intersection of volatile registers that don't contain possible
1959 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry
1960 * without saving, though xer is not a good idea to use, as hardware may
1961 * interpret some bits so it may be costly to change them.
1963 INT_DEFINE_BEGIN(system_call)
1968 INT_DEFINE_END(system_call)
1970 .macro SYSTEM_CALL virt
1971 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1973 * There is a little bit of juggling to get syscall and hcall
1974 * working well. Save r13 in ctr to avoid using SPRG scratch
1977 * Userspace syscalls have already saved the PPR, hcalls must save
1978 * it before setting HMT_MEDIUM.
1982 std r10,PACA_EXGEN+EX_R10(r13)
1984 KVMTEST system_call kvm_hcall /* uses r10, branch to kvm_hcall */
1992 #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
1996 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
1999 /* We reach here with PACA in r13, r13 in r9. */
2006 __LOAD_HANDLER(r10, system_call_common_real, real_vectors)
2010 #ifdef CONFIG_RELOCATABLE
2011 __LOAD_HANDLER(r10, system_call_common, virt_vectors)
2015 b system_call_common
2019 #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
2020 /* Fast LE/BE switch system call */
2021 1: mfspr r12,SPRN_SRR1
2025 RFI_TO_USER /* return to userspace */
2026 b . /* prevent speculative execution */
2030 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
2032 EXC_REAL_END(system_call, 0xc00, 0x100)
2033 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
2035 EXC_VIRT_END(system_call, 0x4c00, 0x100)
2037 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
2038 TRAMP_REAL_BEGIN(kvm_hcall)
2039 std r9,PACA_EXGEN+EX_R9(r13)
2040 std r11,PACA_EXGEN+EX_R11(r13)
2041 std r12,PACA_EXGEN+EX_R12(r13)
2044 std r10,PACA_EXGEN+EX_R13(r13)
2046 std r10,PACA_EXGEN+EX_CFAR(r13)
2047 std r10,PACA_EXGEN+EX_CTR(r13)
2049 * Save the PPR (on systems that support it) before changing to
2050 * HMT_MEDIUM. That allows the KVM code to save that value into the
2051 * guest state (it is the guest's PPR value).
2055 std r10,PACA_EXGEN+EX_PPR(r13)
2056 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
2060 #ifdef CONFIG_RELOCATABLE
2062 * Requires __LOAD_FAR_HANDLER beause kvmppc_hcall lives
2063 * outside the head section.
2065 __LOAD_FAR_HANDLER(r10, kvmppc_hcall, real_trampolines)
2074 * Interrupt 0xd00 - Trace Interrupt.
2075 * This is a synchronous interrupt in response to instruction step or
2076 * breakpoint faults.
2078 INT_DEFINE_BEGIN(single_step)
2080 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2083 INT_DEFINE_END(single_step)
2085 EXC_REAL_BEGIN(single_step, 0xd00, 0x100)
2086 GEN_INT_ENTRY single_step, virt=0
2087 EXC_REAL_END(single_step, 0xd00, 0x100)
2088 EXC_VIRT_BEGIN(single_step, 0x4d00, 0x100)
2089 GEN_INT_ENTRY single_step, virt=1
2090 EXC_VIRT_END(single_step, 0x4d00, 0x100)
2091 EXC_COMMON_BEGIN(single_step_common)
2092 GEN_COMMON single_step
2093 addi r3,r1,STACK_INT_FRAME_REGS
2094 bl CFUNC(single_step_exception)
2095 b interrupt_return_srr
2099 * Interrupt 0xe00 - Hypervisor Data Storage Interrupt (HDSI).
2100 * This is a synchronous interrupt in response to an MMU fault caused by a
2101 * guest data access.
2104 * This should always get routed to KVM. In radix MMU mode, this is caused
2105 * by a guest nested radix access that can't be performed due to the
2106 * partition scope page table. In hash mode, this can be caused by guests
2107 * running with translation disabled (virtual real mode) or with VPM enabled.
2108 * KVM will update the page table structures or disallow the access.
2110 INT_DEFINE_BEGIN(h_data_storage)
2117 INT_DEFINE_END(h_data_storage)
2119 EXC_REAL_BEGIN(h_data_storage, 0xe00, 0x20)
2120 GEN_INT_ENTRY h_data_storage, virt=0, ool=1
2121 EXC_REAL_END(h_data_storage, 0xe00, 0x20)
2122 EXC_VIRT_BEGIN(h_data_storage, 0x4e00, 0x20)
2123 GEN_INT_ENTRY h_data_storage, virt=1, ool=1
2124 EXC_VIRT_END(h_data_storage, 0x4e00, 0x20)
2125 EXC_COMMON_BEGIN(h_data_storage_common)
2126 GEN_COMMON h_data_storage
2127 addi r3,r1,STACK_INT_FRAME_REGS
2128 BEGIN_MMU_FTR_SECTION
2129 bl CFUNC(do_bad_page_fault_segv)
2130 MMU_FTR_SECTION_ELSE
2131 bl CFUNC(unknown_exception)
2132 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX)
2133 b interrupt_return_hsrr
2137 * Interrupt 0xe20 - Hypervisor Instruction Storage Interrupt (HISI).
2138 * This is a synchronous interrupt in response to an MMU fault caused by a
2139 * guest instruction fetch, similar to HDSI.
2141 INT_DEFINE_BEGIN(h_instr_storage)
2146 INT_DEFINE_END(h_instr_storage)
2148 EXC_REAL_BEGIN(h_instr_storage, 0xe20, 0x20)
2149 GEN_INT_ENTRY h_instr_storage, virt=0, ool=1
2150 EXC_REAL_END(h_instr_storage, 0xe20, 0x20)
2151 EXC_VIRT_BEGIN(h_instr_storage, 0x4e20, 0x20)
2152 GEN_INT_ENTRY h_instr_storage, virt=1, ool=1
2153 EXC_VIRT_END(h_instr_storage, 0x4e20, 0x20)
2154 EXC_COMMON_BEGIN(h_instr_storage_common)
2155 GEN_COMMON h_instr_storage
2156 addi r3,r1,STACK_INT_FRAME_REGS
2157 bl CFUNC(unknown_exception)
2158 b interrupt_return_hsrr
2162 * Interrupt 0xe40 - Hypervisor Emulation Assistance Interrupt.
2164 INT_DEFINE_BEGIN(emulation_assist)
2169 INT_DEFINE_END(emulation_assist)
2171 EXC_REAL_BEGIN(emulation_assist, 0xe40, 0x20)
2172 GEN_INT_ENTRY emulation_assist, virt=0, ool=1
2173 EXC_REAL_END(emulation_assist, 0xe40, 0x20)
2174 EXC_VIRT_BEGIN(emulation_assist, 0x4e40, 0x20)
2175 GEN_INT_ENTRY emulation_assist, virt=1, ool=1
2176 EXC_VIRT_END(emulation_assist, 0x4e40, 0x20)
2177 EXC_COMMON_BEGIN(emulation_assist_common)
2178 GEN_COMMON emulation_assist
2179 addi r3,r1,STACK_INT_FRAME_REGS
2180 bl CFUNC(emulation_assist_interrupt)
2181 HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
2182 b interrupt_return_hsrr
2186 * Interrupt 0xe60 - Hypervisor Maintenance Interrupt (HMI).
2187 * This is an asynchronous interrupt caused by a Hypervisor Maintenance
2188 * Exception. It is always taken in real mode but uses HSRR registers
2189 * unlike SRESET and MCE.
2191 * It is maskable in hardware by clearing MSR[EE], and partially soft-maskable
2192 * with IRQS_DISABLED mask (i.e., local_irq_disable()).
2195 * This is a special case, this is handled similarly to machine checks, with an
2196 * initial real mode handler that is not soft-masked, which attempts to fix the
2197 * problem. Then a regular handler which is soft-maskable and reports the
2200 * The emergency stack is used for the early real mode handler.
2202 * XXX: unclear why MCE and HMI schemes could not be made common, e.g.,
2203 * either use soft-masking for the MCE, or use irq_work for the HMI.
2206 * Unlike MCE, this calls into KVM without calling the real mode handler
2209 INT_DEFINE_BEGIN(hmi_exception_early)
2214 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */
2216 INT_DEFINE_END(hmi_exception_early)
2218 INT_DEFINE_BEGIN(hmi_exception)
2223 INT_DEFINE_END(hmi_exception)
2225 EXC_REAL_BEGIN(hmi_exception, 0xe60, 0x20)
2226 GEN_INT_ENTRY hmi_exception_early, virt=0, ool=1
2227 EXC_REAL_END(hmi_exception, 0xe60, 0x20)
2228 EXC_VIRT_NONE(0x4e60, 0x20)
2230 EXC_COMMON_BEGIN(hmi_exception_early_common)
2231 __GEN_REALMODE_COMMON_ENTRY hmi_exception_early
2233 mr r10,r1 /* Save r1 */
2234 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */
2235 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
2237 __GEN_COMMON_BODY hmi_exception_early
2239 addi r3,r1,STACK_INT_FRAME_REGS
2240 bl CFUNC(hmi_exception_realmode)
2244 EXCEPTION_RESTORE_REGS hsrr=1
2245 HRFI_TO_USER_OR_KERNEL
2249 * Go to virtual mode and pull the HMI event information from
2252 EXCEPTION_RESTORE_REGS hsrr=1
2253 GEN_INT_ENTRY hmi_exception, virt=0
2255 EXC_COMMON_BEGIN(hmi_exception_common)
2256 GEN_COMMON hmi_exception
2257 addi r3,r1,STACK_INT_FRAME_REGS
2258 bl CFUNC(handle_hmi_exception)
2259 b interrupt_return_hsrr
2263 * Interrupt 0xe80 - Directed Hypervisor Doorbell Interrupt.
2264 * This is an asynchronous interrupt in response to a msgsnd doorbell.
2265 * Similar to the 0xa00 doorbell but for host rather than guest.
2267 * CFAR is not required (similar to doorbell_interrupt), unless KVM HV
2268 * is enabled, in which case it may be a guest exit. Most PowerNV kernels
2269 * include KVM support so it would be nice if this could be dynamically
2270 * patched out if KVM was not currently running any guests.
2272 INT_DEFINE_BEGIN(h_doorbell)
2278 #ifndef CONFIG_KVM_BOOK3S_HV_POSSIBLE
2281 INT_DEFINE_END(h_doorbell)
2283 EXC_REAL_BEGIN(h_doorbell, 0xe80, 0x20)
2284 GEN_INT_ENTRY h_doorbell, virt=0, ool=1
2285 EXC_REAL_END(h_doorbell, 0xe80, 0x20)
2286 EXC_VIRT_BEGIN(h_doorbell, 0x4e80, 0x20)
2287 GEN_INT_ENTRY h_doorbell, virt=1, ool=1
2288 EXC_VIRT_END(h_doorbell, 0x4e80, 0x20)
2289 EXC_COMMON_BEGIN(h_doorbell_common)
2290 GEN_COMMON h_doorbell
2291 addi r3,r1,STACK_INT_FRAME_REGS
2292 #ifdef CONFIG_PPC_DOORBELL
2293 bl CFUNC(doorbell_exception)
2295 bl CFUNC(unknown_async_exception)
2297 b interrupt_return_hsrr
2301 * Interrupt 0xea0 - Hypervisor Virtualization Interrupt.
2302 * This is an asynchronous interrupt in response to an "external exception".
2303 * Similar to 0x500 but for host only.
2305 * Like h_doorbell, CFAR is only required for KVM HV because this can be
2308 INT_DEFINE_BEGIN(h_virt_irq)
2314 #ifndef CONFIG_KVM_BOOK3S_HV_POSSIBLE
2317 INT_DEFINE_END(h_virt_irq)
2319 EXC_REAL_BEGIN(h_virt_irq, 0xea0, 0x20)
2320 GEN_INT_ENTRY h_virt_irq, virt=0, ool=1
2321 EXC_REAL_END(h_virt_irq, 0xea0, 0x20)
2322 EXC_VIRT_BEGIN(h_virt_irq, 0x4ea0, 0x20)
2323 GEN_INT_ENTRY h_virt_irq, virt=1, ool=1
2324 EXC_VIRT_END(h_virt_irq, 0x4ea0, 0x20)
2325 EXC_COMMON_BEGIN(h_virt_irq_common)
2326 GEN_COMMON h_virt_irq
2327 addi r3,r1,STACK_INT_FRAME_REGS
2329 b interrupt_return_hsrr
2332 EXC_REAL_NONE(0xec0, 0x20)
2333 EXC_VIRT_NONE(0x4ec0, 0x20)
2334 EXC_REAL_NONE(0xee0, 0x20)
2335 EXC_VIRT_NONE(0x4ee0, 0x20)
2339 * Interrupt 0xf00 - Performance Monitor Interrupt (PMI, PMU).
2340 * This is an asynchronous interrupt in response to a PMU exception.
2341 * It is maskable in hardware by clearing MSR[EE], and soft-maskable with
2342 * IRQS_PMI_DISABLED mask (NOTE: NOT local_irq_disable()).
2345 * This calls into the perf subsystem.
2347 * Like the watchdog soft-nmi, it appears an NMI interrupt to Linux, in that it
2348 * runs under local_irq_disable. However it may be soft-masked in
2349 * powerpc-specific code.
2351 * If soft masked, the masked handler will note the pending interrupt for
2352 * replay, and clear MSR[EE] in the interrupted context.
2354 * CFAR is not used by perf interrupts so not required.
2356 INT_DEFINE_BEGIN(performance_monitor)
2358 IMASK=IRQS_PMI_DISABLED
2359 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2363 INT_DEFINE_END(performance_monitor)
2365 EXC_REAL_BEGIN(performance_monitor, 0xf00, 0x20)
2366 GEN_INT_ENTRY performance_monitor, virt=0, ool=1
2367 EXC_REAL_END(performance_monitor, 0xf00, 0x20)
2368 EXC_VIRT_BEGIN(performance_monitor, 0x4f00, 0x20)
2369 GEN_INT_ENTRY performance_monitor, virt=1, ool=1
2370 EXC_VIRT_END(performance_monitor, 0x4f00, 0x20)
2371 EXC_COMMON_BEGIN(performance_monitor_common)
2372 GEN_COMMON performance_monitor
2373 addi r3,r1,STACK_INT_FRAME_REGS
2374 lbz r4,PACAIRQSOFTMASK(r13)
2375 cmpdi r4,IRQS_ENABLED
2377 bl CFUNC(performance_monitor_exception_async)
2378 b interrupt_return_srr
2380 bl CFUNC(performance_monitor_exception_nmi)
2381 /* Clear MSR_RI before setting SRR0 and SRR1. */
2385 kuap_kernel_restore r9, r10
2387 EXCEPTION_RESTORE_REGS hsrr=0
2391 * Interrupt 0xf20 - Vector Unavailable Interrupt.
2392 * This is a synchronous interrupt in response to
2393 * executing a vector (or altivec) instruction with MSR[VEC]=0.
2394 * Similar to FP unavailable.
2396 INT_DEFINE_BEGIN(altivec_unavailable)
2398 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2402 INT_DEFINE_END(altivec_unavailable)
2404 EXC_REAL_BEGIN(altivec_unavailable, 0xf20, 0x20)
2405 GEN_INT_ENTRY altivec_unavailable, virt=0, ool=1
2406 EXC_REAL_END(altivec_unavailable, 0xf20, 0x20)
2407 EXC_VIRT_BEGIN(altivec_unavailable, 0x4f20, 0x20)
2408 GEN_INT_ENTRY altivec_unavailable, virt=1, ool=1
2409 EXC_VIRT_END(altivec_unavailable, 0x4f20, 0x20)
2410 EXC_COMMON_BEGIN(altivec_unavailable_common)
2411 GEN_COMMON altivec_unavailable
2412 #ifdef CONFIG_ALTIVEC
2415 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2416 BEGIN_FTR_SECTION_NESTED(69)
2417 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
2418 * transaction), go do TM stuff
2420 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
2422 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
2424 bl CFUNC(load_up_altivec)
2425 b fast_interrupt_return_srr
2426 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2427 2: /* User process was in a transaction */
2428 addi r3,r1,STACK_INT_FRAME_REGS
2429 bl CFUNC(altivec_unavailable_tm)
2430 b interrupt_return_srr
2433 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2435 addi r3,r1,STACK_INT_FRAME_REGS
2436 bl CFUNC(altivec_unavailable_exception)
2437 b interrupt_return_srr
2441 * Interrupt 0xf40 - VSX Unavailable Interrupt.
2442 * This is a synchronous interrupt in response to
2443 * executing a VSX instruction with MSR[VSX]=0.
2444 * Similar to FP unavailable.
2446 INT_DEFINE_BEGIN(vsx_unavailable)
2448 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2452 INT_DEFINE_END(vsx_unavailable)
2454 EXC_REAL_BEGIN(vsx_unavailable, 0xf40, 0x20)
2455 GEN_INT_ENTRY vsx_unavailable, virt=0, ool=1
2456 EXC_REAL_END(vsx_unavailable, 0xf40, 0x20)
2457 EXC_VIRT_BEGIN(vsx_unavailable, 0x4f40, 0x20)
2458 GEN_INT_ENTRY vsx_unavailable, virt=1, ool=1
2459 EXC_VIRT_END(vsx_unavailable, 0x4f40, 0x20)
2460 EXC_COMMON_BEGIN(vsx_unavailable_common)
2461 GEN_COMMON vsx_unavailable
2465 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2466 BEGIN_FTR_SECTION_NESTED(69)
2467 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
2468 * transaction), go do TM stuff
2470 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
2472 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
2475 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2476 2: /* User process was in a transaction */
2477 addi r3,r1,STACK_INT_FRAME_REGS
2478 bl CFUNC(vsx_unavailable_tm)
2479 b interrupt_return_srr
2482 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2484 addi r3,r1,STACK_INT_FRAME_REGS
2485 bl CFUNC(vsx_unavailable_exception)
2486 b interrupt_return_srr
2490 * Interrupt 0xf60 - Facility Unavailable Interrupt.
2491 * This is a synchronous interrupt in response to
2492 * executing an instruction without access to the facility that can be
2493 * resolved by the OS (e.g., FSCR, MSR).
2494 * Similar to FP unavailable.
2496 INT_DEFINE_BEGIN(facility_unavailable)
2498 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2501 INT_DEFINE_END(facility_unavailable)
2503 EXC_REAL_BEGIN(facility_unavailable, 0xf60, 0x20)
2504 GEN_INT_ENTRY facility_unavailable, virt=0, ool=1
2505 EXC_REAL_END(facility_unavailable, 0xf60, 0x20)
2506 EXC_VIRT_BEGIN(facility_unavailable, 0x4f60, 0x20)
2507 GEN_INT_ENTRY facility_unavailable, virt=1, ool=1
2508 EXC_VIRT_END(facility_unavailable, 0x4f60, 0x20)
2509 EXC_COMMON_BEGIN(facility_unavailable_common)
2510 GEN_COMMON facility_unavailable
2511 addi r3,r1,STACK_INT_FRAME_REGS
2512 bl CFUNC(facility_unavailable_exception)
2513 HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
2514 b interrupt_return_srr
2518 * Interrupt 0xf60 - Hypervisor Facility Unavailable Interrupt.
2519 * This is a synchronous interrupt in response to
2520 * executing an instruction without access to the facility that can only
2521 * be resolved in HV mode (e.g., HFSCR).
2522 * Similar to FP unavailable.
2524 INT_DEFINE_BEGIN(h_facility_unavailable)
2529 INT_DEFINE_END(h_facility_unavailable)
2531 EXC_REAL_BEGIN(h_facility_unavailable, 0xf80, 0x20)
2532 GEN_INT_ENTRY h_facility_unavailable, virt=0, ool=1
2533 EXC_REAL_END(h_facility_unavailable, 0xf80, 0x20)
2534 EXC_VIRT_BEGIN(h_facility_unavailable, 0x4f80, 0x20)
2535 GEN_INT_ENTRY h_facility_unavailable, virt=1, ool=1
2536 EXC_VIRT_END(h_facility_unavailable, 0x4f80, 0x20)
2537 EXC_COMMON_BEGIN(h_facility_unavailable_common)
2538 GEN_COMMON h_facility_unavailable
2539 addi r3,r1,STACK_INT_FRAME_REGS
2540 bl CFUNC(facility_unavailable_exception)
2541 /* XXX Shouldn't be necessary in practice */
2542 HANDLER_RESTORE_NVGPRS()
2543 b interrupt_return_hsrr
2546 EXC_REAL_NONE(0xfa0, 0x20)
2547 EXC_VIRT_NONE(0x4fa0, 0x20)
2548 EXC_REAL_NONE(0xfc0, 0x20)
2549 EXC_VIRT_NONE(0x4fc0, 0x20)
2550 EXC_REAL_NONE(0xfe0, 0x20)
2551 EXC_VIRT_NONE(0x4fe0, 0x20)
2553 EXC_REAL_NONE(0x1000, 0x100)
2554 EXC_VIRT_NONE(0x5000, 0x100)
2555 EXC_REAL_NONE(0x1100, 0x100)
2556 EXC_VIRT_NONE(0x5100, 0x100)
2558 #ifdef CONFIG_CBE_RAS
2559 INT_DEFINE_BEGIN(cbe_system_error)
2562 INT_DEFINE_END(cbe_system_error)
2564 EXC_REAL_BEGIN(cbe_system_error, 0x1200, 0x100)
2565 GEN_INT_ENTRY cbe_system_error, virt=0
2566 EXC_REAL_END(cbe_system_error, 0x1200, 0x100)
2567 EXC_VIRT_NONE(0x5200, 0x100)
2568 EXC_COMMON_BEGIN(cbe_system_error_common)
2569 GEN_COMMON cbe_system_error
2570 addi r3,r1,STACK_INT_FRAME_REGS
2571 bl CFUNC(cbe_system_error_exception)
2572 b interrupt_return_hsrr
2574 #else /* CONFIG_CBE_RAS */
2575 EXC_REAL_NONE(0x1200, 0x100)
2576 EXC_VIRT_NONE(0x5200, 0x100)
2580 * Interrupt 0x1300 - Instruction Address Breakpoint Interrupt.
2581 * This has been removed from the ISA before 2.01, which is the earliest
2582 * 64-bit BookS ISA supported, however the G5 / 970 implements this
2583 * interrupt with a non-architected feature available through the support
2584 * processor interface.
2586 INT_DEFINE_BEGIN(instruction_breakpoint)
2588 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2591 INT_DEFINE_END(instruction_breakpoint)
2593 EXC_REAL_BEGIN(instruction_breakpoint, 0x1300, 0x100)
2594 GEN_INT_ENTRY instruction_breakpoint, virt=0
2595 EXC_REAL_END(instruction_breakpoint, 0x1300, 0x100)
2596 EXC_VIRT_BEGIN(instruction_breakpoint, 0x5300, 0x100)
2597 GEN_INT_ENTRY instruction_breakpoint, virt=1
2598 EXC_VIRT_END(instruction_breakpoint, 0x5300, 0x100)
2599 EXC_COMMON_BEGIN(instruction_breakpoint_common)
2600 GEN_COMMON instruction_breakpoint
2601 addi r3,r1,STACK_INT_FRAME_REGS
2602 bl CFUNC(instruction_breakpoint_exception)
2603 b interrupt_return_srr
2606 EXC_REAL_NONE(0x1400, 0x100)
2607 EXC_VIRT_NONE(0x5400, 0x100)
2610 * Interrupt 0x1500 - Soft Patch Interrupt
2613 * This is an implementation specific interrupt which can be used for a
2614 * range of exceptions.
2616 * This interrupt handler is unique in that it runs the denormal assist
2617 * code even for guests (and even in guest context) without going to KVM,
2618 * for speed. POWER9 does not raise denorm exceptions, so this special case
2619 * could be phased out in future to reduce special cases.
2621 INT_DEFINE_BEGIN(denorm_exception)
2626 INT_DEFINE_END(denorm_exception)
2628 EXC_REAL_BEGIN(denorm_exception, 0x1500, 0x100)
2629 GEN_INT_ENTRY denorm_exception, virt=0
2630 #ifdef CONFIG_PPC_DENORMALISATION
2631 andis. r10,r12,(HSRR1_DENORM)@h /* denorm? */
2634 GEN_BRANCH_TO_COMMON denorm_exception, virt=0
2635 EXC_REAL_END(denorm_exception, 0x1500, 0x100)
2636 #ifdef CONFIG_PPC_DENORMALISATION
2637 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
2638 GEN_INT_ENTRY denorm_exception, virt=1
2639 andis. r10,r12,(HSRR1_DENORM)@h /* denorm? */
2641 GEN_BRANCH_TO_COMMON denorm_exception, virt=1
2642 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
2644 EXC_VIRT_NONE(0x5500, 0x100)
2647 #ifdef CONFIG_PPC_DENORMALISATION
2648 TRAMP_REAL_BEGIN(denorm_assist)
2651 * To denormalise we need to move a copy of the register to itself.
2652 * For POWER6 do that here for all FP regs.
2655 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
2656 xori r10,r10,(MSR_FE0|MSR_FE1)
2668 * To denormalise we need to move a copy of the register to itself.
2669 * For POWER7 do that here for the first 32 VSX registers only.
2672 oris r10,r10,MSR_VSX@h
2678 XVCPSGNDP(.Lreg,.Lreg,.Lreg)
2682 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
2686 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
2688 * To denormalise we need to move a copy of the register to itself.
2689 * For POWER8 we need to do that for all 64 VSX registers
2693 XVCPSGNDP(.Lreg,.Lreg,.Lreg)
2698 mfspr r11,SPRN_HSRR0
2700 mtspr SPRN_HSRR0,r11
2702 ld r9,PACA_EXGEN+EX_R9(r13)
2704 ld r10,PACA_EXGEN+EX_PPR(r13)
2706 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
2708 ld r10,PACA_EXGEN+EX_CFAR(r13)
2710 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
2712 stb r10,PACAHSRR_VALID(r13)
2713 ld r10,PACA_EXGEN+EX_R10(r13)
2714 ld r11,PACA_EXGEN+EX_R11(r13)
2715 ld r12,PACA_EXGEN+EX_R12(r13)
2716 ld r13,PACA_EXGEN+EX_R13(r13)
2721 EXC_COMMON_BEGIN(denorm_exception_common)
2722 GEN_COMMON denorm_exception
2723 addi r3,r1,STACK_INT_FRAME_REGS
2724 bl CFUNC(unknown_exception)
2725 b interrupt_return_hsrr
2728 #ifdef CONFIG_CBE_RAS
2729 INT_DEFINE_BEGIN(cbe_maintenance)
2732 INT_DEFINE_END(cbe_maintenance)
2734 EXC_REAL_BEGIN(cbe_maintenance, 0x1600, 0x100)
2735 GEN_INT_ENTRY cbe_maintenance, virt=0
2736 EXC_REAL_END(cbe_maintenance, 0x1600, 0x100)
2737 EXC_VIRT_NONE(0x5600, 0x100)
2738 EXC_COMMON_BEGIN(cbe_maintenance_common)
2739 GEN_COMMON cbe_maintenance
2740 addi r3,r1,STACK_INT_FRAME_REGS
2741 bl CFUNC(cbe_maintenance_exception)
2742 b interrupt_return_hsrr
2744 #else /* CONFIG_CBE_RAS */
2745 EXC_REAL_NONE(0x1600, 0x100)
2746 EXC_VIRT_NONE(0x5600, 0x100)
2750 INT_DEFINE_BEGIN(altivec_assist)
2752 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2755 INT_DEFINE_END(altivec_assist)
2757 EXC_REAL_BEGIN(altivec_assist, 0x1700, 0x100)
2758 GEN_INT_ENTRY altivec_assist, virt=0
2759 EXC_REAL_END(altivec_assist, 0x1700, 0x100)
2760 EXC_VIRT_BEGIN(altivec_assist, 0x5700, 0x100)
2761 GEN_INT_ENTRY altivec_assist, virt=1
2762 EXC_VIRT_END(altivec_assist, 0x5700, 0x100)
2763 EXC_COMMON_BEGIN(altivec_assist_common)
2764 GEN_COMMON altivec_assist
2765 addi r3,r1,STACK_INT_FRAME_REGS
2766 #ifdef CONFIG_ALTIVEC
2767 bl CFUNC(altivec_assist_exception)
2768 HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
2770 bl CFUNC(unknown_exception)
2772 b interrupt_return_srr
2775 #ifdef CONFIG_CBE_RAS
2776 INT_DEFINE_BEGIN(cbe_thermal)
2779 INT_DEFINE_END(cbe_thermal)
2781 EXC_REAL_BEGIN(cbe_thermal, 0x1800, 0x100)
2782 GEN_INT_ENTRY cbe_thermal, virt=0
2783 EXC_REAL_END(cbe_thermal, 0x1800, 0x100)
2784 EXC_VIRT_NONE(0x5800, 0x100)
2785 EXC_COMMON_BEGIN(cbe_thermal_common)
2786 GEN_COMMON cbe_thermal
2787 addi r3,r1,STACK_INT_FRAME_REGS
2788 bl CFUNC(cbe_thermal_exception)
2789 b interrupt_return_hsrr
2791 #else /* CONFIG_CBE_RAS */
2792 EXC_REAL_NONE(0x1800, 0x100)
2793 EXC_VIRT_NONE(0x5800, 0x100)
2797 #ifdef CONFIG_PPC_WATCHDOG
2799 INT_DEFINE_BEGIN(soft_nmi)
2803 INT_DEFINE_END(soft_nmi)
2806 * Branch to soft_nmi_interrupt using the emergency stack. The emergency
2807 * stack is one that is usable by maskable interrupts so long as MSR_EE
2808 * remains off. It is used for recovery when something has corrupted the
2809 * normal kernel stack, for example. The "soft NMI" must not use the process
2810 * stack because we want irq disabled sections to avoid touching the stack
2811 * at all (other than PMU interrupts), so use the emergency stack for this,
2812 * and run it entirely with interrupts hard disabled.
2814 EXC_COMMON_BEGIN(soft_nmi_common)
2816 ld r1,PACAEMERGSP(r13)
2817 subi r1,r1,INT_FRAME_SIZE
2818 __GEN_COMMON_BODY soft_nmi
2820 addi r3,r1,STACK_INT_FRAME_REGS
2821 bl CFUNC(soft_nmi_interrupt)
2823 /* Clear MSR_RI before setting SRR0 and SRR1. */
2827 kuap_kernel_restore r9, r10
2829 EXCEPTION_RESTORE_REGS hsrr=0
2832 #endif /* CONFIG_PPC_WATCHDOG */
2835 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
2836 * - If it was a decrementer interrupt, we bump the dec to max and return.
2837 * - If it was a doorbell we return immediately since doorbells are edge
2838 * triggered and won't automatically refire.
2839 * - If it was a HMI we return immediately since we handled it in realmode
2840 * and it won't refire.
2841 * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return.
2842 * This is called with r10 containing the value to OR to the paca field.
2844 .macro MASKED_INTERRUPT hsrr=0
2850 stw r9,PACA_EXGEN+EX_CCR(r13)
2851 #ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG
2853 * Ensure there was no previous MUST_HARD_MASK interrupt or
2854 * HARD_DIS setting. If this does fire, the interrupt is still
2855 * masked and MSR[EE] will be cleared on return, so no need to
2856 * panic, but somebody probably enabled MSR[EE] under
2857 * PACA_IRQ_HARD_DIS, mtmsr(mfmsr() | MSR_x) being a common
2860 lbz r9,PACAIRQHAPPENED(r13)
2861 andi. r9,r9,(PACA_IRQ_MUST_HARD_MASK|PACA_IRQ_HARD_DIS)
2863 EMIT_WARN_ENTRY 0b,__FILE__,__LINE__,(BUGFLAG_WARNING | BUGFLAG_ONCE)
2865 lbz r9,PACAIRQHAPPENED(r13)
2867 stb r9,PACAIRQHAPPENED(r13)
2870 cmpwi r10,PACA_IRQ_DEC
2872 LOAD_REG_IMMEDIATE(r9, 0x7fffffff)
2874 #ifdef CONFIG_PPC_WATCHDOG
2875 lwz r9,PACA_EXGEN+EX_CCR(r13)
2882 1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK
2884 xori r12,r12,MSR_EE /* clear MSR_EE */
2886 mtspr SPRN_HSRR1,r12
2890 ori r9,r9,PACA_IRQ_HARD_DIS
2891 stb r9,PACAIRQHAPPENED(r13)
2895 stb r9,PACAHSRR_VALID(r13)
2897 stb r9,PACASRR_VALID(r13)
2900 SEARCH_RESTART_TABLE
2904 mtspr SPRN_HSRR0,r12
2910 ld r9,PACA_EXGEN+EX_CTR(r13)
2912 lwz r9,PACA_EXGEN+EX_CCR(r13)
2915 ld r9,PACA_EXGEN+EX_R9(r13)
2916 ld r10,PACA_EXGEN+EX_R10(r13)
2917 ld r11,PACA_EXGEN+EX_R11(r13)
2918 ld r12,PACA_EXGEN+EX_R12(r13)
2919 ld r13,PACA_EXGEN+EX_R13(r13)
2920 /* May return to masked low address where r13 is not set up */
2929 TRAMP_REAL_BEGIN(stf_barrier_fallback)
2930 std r9,PACA_EXRFI+EX_R9(r13)
2931 std r10,PACA_EXRFI+EX_R10(r13)
2933 ld r9,PACA_EXRFI+EX_R9(r13)
2934 ld r10,PACA_EXRFI+EX_R10(r13)
2942 /* Clobbers r10, r11, ctr */
2943 .macro L1D_DISPLACEMENT_FLUSH
2944 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
2945 ld r11,PACA_L1D_FLUSH_SIZE(r13)
2946 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
2948 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
2950 /* order ld/st prior to dcbt stop all streams with flushing */
2954 * The load addresses are at staggered offsets within cachelines,
2955 * which suits some pipelines better (on others it should not
2959 ld r11,(0x80 + 8)*0(r10)
2960 ld r11,(0x80 + 8)*1(r10)
2961 ld r11,(0x80 + 8)*2(r10)
2962 ld r11,(0x80 + 8)*3(r10)
2963 ld r11,(0x80 + 8)*4(r10)
2964 ld r11,(0x80 + 8)*5(r10)
2965 ld r11,(0x80 + 8)*6(r10)
2966 ld r11,(0x80 + 8)*7(r10)
2971 TRAMP_REAL_BEGIN(entry_flush_fallback)
2972 std r9,PACA_EXRFI+EX_R9(r13)
2973 std r10,PACA_EXRFI+EX_R10(r13)
2974 std r11,PACA_EXRFI+EX_R11(r13)
2976 L1D_DISPLACEMENT_FLUSH
2978 ld r9,PACA_EXRFI+EX_R9(r13)
2979 ld r10,PACA_EXRFI+EX_R10(r13)
2980 ld r11,PACA_EXRFI+EX_R11(r13)
2984 * The SCV entry flush happens with interrupts enabled, so it must disable
2985 * to prevent EXRFI being clobbered by NMIs (e.g., soft_nmi_common). r10
2986 * (containing LR) does not need to be preserved here because scv entry
2987 * puts 0 in the pt_regs, CTR can be clobbered for the same reason.
2989 TRAMP_REAL_BEGIN(scv_entry_flush_fallback)
2992 lbz r10,PACAIRQHAPPENED(r13)
2993 ori r10,r10,PACA_IRQ_HARD_DIS
2994 stb r10,PACAIRQHAPPENED(r13)
2995 std r11,PACA_EXRFI+EX_R11(r13)
2996 L1D_DISPLACEMENT_FLUSH
2997 ld r11,PACA_EXRFI+EX_R11(r13)
3002 TRAMP_REAL_BEGIN(rfi_flush_fallback)
3005 std r1,PACA_EXRFI+EX_R12(r13)
3006 ld r1,PACAKSAVE(r13)
3007 std r9,PACA_EXRFI+EX_R9(r13)
3008 std r10,PACA_EXRFI+EX_R10(r13)
3009 std r11,PACA_EXRFI+EX_R11(r13)
3011 L1D_DISPLACEMENT_FLUSH
3013 ld r9,PACA_EXRFI+EX_R9(r13)
3014 ld r10,PACA_EXRFI+EX_R10(r13)
3015 ld r11,PACA_EXRFI+EX_R11(r13)
3016 ld r1,PACA_EXRFI+EX_R12(r13)
3020 TRAMP_REAL_BEGIN(hrfi_flush_fallback)
3023 std r1,PACA_EXRFI+EX_R12(r13)
3024 ld r1,PACAKSAVE(r13)
3025 std r9,PACA_EXRFI+EX_R9(r13)
3026 std r10,PACA_EXRFI+EX_R10(r13)
3027 std r11,PACA_EXRFI+EX_R11(r13)
3029 L1D_DISPLACEMENT_FLUSH
3031 ld r9,PACA_EXRFI+EX_R9(r13)
3032 ld r10,PACA_EXRFI+EX_R10(r13)
3033 ld r11,PACA_EXRFI+EX_R11(r13)
3034 ld r1,PACA_EXRFI+EX_R12(r13)
3038 TRAMP_REAL_BEGIN(rfscv_flush_fallback)
3039 /* system call volatile */
3043 ld r1,PACAKSAVE(r13)
3045 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
3046 ld r11,PACA_L1D_FLUSH_SIZE(r13)
3047 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
3049 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
3051 /* order ld/st prior to dcbt stop all streams with flushing */
3055 * The load adresses are at staggered offsets within cachelines,
3056 * which suits some pipelines better (on others it should not
3060 ld r11,(0x80 + 8)*0(r10)
3061 ld r11,(0x80 + 8)*1(r10)
3062 ld r11,(0x80 + 8)*2(r10)
3063 ld r11,(0x80 + 8)*3(r10)
3064 ld r11,(0x80 + 8)*4(r10)
3065 ld r11,(0x80 + 8)*5(r10)
3066 ld r11,(0x80 + 8)*6(r10)
3067 ld r11,(0x80 + 8)*7(r10)
3081 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
3084 * The conditional branch in KVMTEST can't reach all the way,
3090 _GLOBAL(do_uaccess_flush)
3091 UACCESS_FLUSH_FIXUP_SECTION
3096 L1D_DISPLACEMENT_FLUSH
3098 _ASM_NOKPROBE_SYMBOL(do_uaccess_flush)
3099 EXPORT_SYMBOL(do_uaccess_flush)
3103 MASKED_INTERRUPT hsrr=1
3105 USE_FIXED_SECTION(virt_trampolines)
3107 * All code below __end_soft_masked is treated as soft-masked. If
3108 * any code runs here with MSR[EE]=1, it must then cope with pending
3109 * soft interrupt being raised (i.e., by ensuring it is replayed).
3111 * The __end_interrupts marker must be past the out-of-line (OOL)
3112 * handlers, so that they are copied to real address 0x100 when running
3113 * a relocatable kernel. This ensures they can be reached from the short
3114 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
3115 * directly, without using LOAD_HANDLER().
3118 .globl __end_interrupts
3120 DEFINE_FIXED_SYMBOL(__end_interrupts, virt_trampolines)
3122 CLOSE_FIXED_SECTION(real_vectors);
3123 CLOSE_FIXED_SECTION(real_trampolines);
3124 CLOSE_FIXED_SECTION(virt_vectors);
3125 CLOSE_FIXED_SECTION(virt_trampolines);
3129 /* MSR[RI] should be clear because this uses SRR[01] */
3130 _GLOBAL(enable_machine_check)
3134 addi r3,r3,(1f - 0b)
3143 /* MSR[RI] should be clear because this uses SRR[01] */
3144 SYM_FUNC_START_LOCAL(disable_machine_check)
3148 addi r3,r3,(1f - 0b)
3157 SYM_FUNC_END(disable_machine_check)