2 * This file contains the 64-bit "server" PowerPC variant
3 * of the low level exception handling including exception
4 * vectors, exception return, part of the slb and stab
5 * handling and other fixed offset specific things.
7 * This file is meant to be #included from head_64.S due to
8 * position dependent assembly.
10 * Most of this originates from head_64.S and thus has the same
15 #include <asm/hw_irq.h>
16 #include <asm/exception-64s.h>
17 #include <asm/ptrace.h>
18 #include <asm/cpuidle.h>
19 #include <asm/head-64.h>
22 * There are a few constraints to be concerned with.
23 * - Real mode exceptions code/data must be located at their physical location.
24 * - Virtual mode exceptions must be mapped at their 0xc000... location.
25 * - Fixed location code must not call directly beyond the __end_interrupts
26 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
28 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
30 * - Conditional branch targets must be within +/-32K of caller.
32 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
33 * therefore don't have to run in physically located code or rfid to
34 * virtual mode kernel code. However on relocatable kernels they do have
35 * to branch to KERNELBASE offset because the rest of the kernel (outside
36 * the exception vectors) may be located elsewhere.
38 * Virtual exceptions correspond with physical, except their entry points
39 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
40 * offset applied. Virtual exceptions are enabled with the Alternate
41 * Interrupt Location (AIL) bit set in the LPCR. However this does not
42 * guarantee they will be delivered virtually. Some conditions (see the ISA)
43 * cause exceptions to be delivered in real mode.
45 * It's impossible to receive interrupts below 0x300 via AIL.
47 * KVM: None of the virtual exceptions are from the guest. Anything that
48 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
51 * We layout physical memory as follows:
52 * 0x0000 - 0x00ff : Secondary processor spin code
53 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
54 * 0x1900 - 0x3fff : Real mode trampolines
55 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
56 * 0x5900 - 0x6fff : Relon mode trampolines
57 * 0x7000 - 0x7fff : FWNMI data area
58 * 0x8000 - .... : Common interrupt handlers, remaining early
59 * setup code, rest of kernel.
61 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
62 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
65 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
66 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000)
67 OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900)
68 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
69 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
71 * Data area reserved for FWNMI option.
72 * This address (0x7000) is fixed by the RPA.
73 * pseries and powernv need to keep the whole page from
74 * 0x7000 to 0x8000 free for use by the firmware
76 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
77 OPEN_TEXT_SECTION(0x8000)
79 OPEN_TEXT_SECTION(0x7000)
82 USE_FIXED_SECTION(real_vectors)
85 * This is the start of the interrupt handlers for pSeries
86 * This code runs with relocation off.
87 * Code from here to __end_interrupts gets copied down to real
88 * address 0x100 when we are running a relocatable kernel.
89 * Therefore any relative branches in this section must only
90 * branch to labels in this section.
92 .globl __start_interrupts
95 /* No virt vectors corresponding with 0x0..0x100 */
96 EXC_VIRT_NONE(0x4000, 0x4100)
99 #ifdef CONFIG_PPC_P7_NAP
101 * If running native on arch 2.06 or later, check if we are waking up
102 * from nap/sleep/winkle, and branch to idle handler.
104 #define IDLETEST(n) \
105 BEGIN_FTR_SECTION ; \
106 mfspr r10,SPRN_SRR1 ; \
107 rlwinm. r10,r10,47-31,30,31 ; \
110 BRANCH_TO_COMMON(r10, system_reset_idle_common) ; \
112 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
114 #define IDLETEST NOTEST
117 EXC_REAL_BEGIN(system_reset, 0x100, 0x200)
120 clrrdi r13,r13,1 /* Last bit of HSPRG0 is set if waking from winkle */
121 EXCEPTION_PROLOG_PSERIES_PACA(PACA_EXGEN, system_reset_common, EXC_STD,
124 EXC_REAL_END(system_reset, 0x100, 0x200)
125 EXC_VIRT_NONE(0x4100, 0x4200)
127 #ifdef CONFIG_PPC_P7_NAP
128 EXC_COMMON_BEGIN(system_reset_idle_common)
130 GET_PACA(r13) /* Restore HSPRG0 to get the winkle bit in r13 */
131 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
132 bl pnv_restore_hyp_resource
134 li r0,PNV_THREAD_RUNNING
135 stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */
137 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
138 li r0,KVM_HWTHREAD_IN_KERNEL
139 stb r0,HSTATE_HWTHREAD_STATE(r13)
140 /* Order setting hwthread_state vs. testing hwthread_req */
142 lbz r0,HSTATE_HWTHREAD_REQ(r13)
149 /* Return SRR1 from power7_nap() */
153 2: b pnv_wakeup_noloss
156 EXC_COMMON(system_reset_common, 0x100, system_reset_exception)
158 #ifdef CONFIG_PPC_PSERIES
160 * Vectors for the FWNMI option. Share common code.
162 TRAMP_REAL_BEGIN(system_reset_fwnmi)
163 SET_SCRATCH0(r13) /* save r13 */
164 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD,
166 #endif /* CONFIG_PPC_PSERIES */
169 EXC_REAL_BEGIN(machine_check, 0x200, 0x300)
170 /* This is moved out of line as it can be patched by FW, but
171 * some code path might still want to branch into the original
174 SET_SCRATCH0(r13) /* save r13 */
176 * Running native on arch 2.06 or later, we may wakeup from winkle
177 * inside machine check. If yes, then last bit of HSPRG0 would be set
178 * to 1. Hence clear it unconditionally.
183 EXCEPTION_PROLOG_0(PACA_EXMC)
185 b machine_check_powernv_early
187 b machine_check_pSeries_0
188 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
189 EXC_REAL_END(machine_check, 0x200, 0x300)
190 EXC_VIRT_NONE(0x4200, 0x4300)
191 TRAMP_REAL_BEGIN(machine_check_powernv_early)
193 EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200)
198 * Original R9 to R13 is saved on PACA_EXMC
200 * Switch to mc_emergency stack and handle re-entrancy (we limit
201 * the nested MCE upto level 4 to avoid stack overflow).
202 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
204 * We use paca->in_mce to check whether this is the first entry or
205 * nested machine check. We increment paca->in_mce to track nested
208 * If this is the first entry then set stack pointer to
209 * paca->mc_emergency_sp, otherwise r1 is already pointing to
210 * stack frame on mc_emergency stack.
212 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
213 * checkstop if we get another machine check exception before we do
214 * rfid with MSR_ME=1.
216 mr r11,r1 /* Save r1 */
217 lhz r10,PACA_IN_MCE(r13)
218 cmpwi r10,0 /* Are we in nested machine check */
219 bne 0f /* Yes, we are. */
220 /* First machine check entry */
221 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
222 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
223 addi r10,r10,1 /* increment paca->in_mce */
224 sth r10,PACA_IN_MCE(r13)
225 /* Limit nested MCE to level 4 to avoid stack overflow */
227 bgt 2f /* Check if we hit limit of 4 */
228 std r11,GPR1(r1) /* Save r1 on the stack. */
229 std r11,0(r1) /* make stack chain pointer */
230 mfspr r11,SPRN_SRR0 /* Save SRR0 */
232 mfspr r11,SPRN_SRR1 /* Save SRR1 */
234 mfspr r11,SPRN_DAR /* Save DAR */
236 mfspr r11,SPRN_DSISR /* Save DSISR */
238 std r9,_CCR(r1) /* Save CR in stackframe */
239 /* Save r9 through r13 from EXMC save area to stack frame. */
240 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
241 mfmsr r11 /* get MSR value */
242 ori r11,r11,MSR_ME /* turn on ME bit */
243 ori r11,r11,MSR_RI /* turn on RI bit */
244 LOAD_HANDLER(r12, machine_check_handle_early)
245 1: mtspr SPRN_SRR0,r12
248 b . /* prevent speculative execution */
250 /* Stack overflow. Stay on emergency stack and panic.
251 * Keep the ME bit off while panic-ing, so that if we hit
252 * another machine check we checkstop.
254 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */
256 LOAD_HANDLER(r12, unrecover_mce)
258 andc r11,r11,r10 /* Turn off MSR_ME */
260 b . /* prevent speculative execution */
261 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
263 TRAMP_REAL_BEGIN(machine_check_pSeries)
264 .globl machine_check_fwnmi
266 SET_SCRATCH0(r13) /* save r13 */
267 EXCEPTION_PROLOG_0(PACA_EXMC)
268 machine_check_pSeries_0:
269 EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200)
271 * The following is essentially EXCEPTION_PROLOG_PSERIES_1 with the
272 * difference that MSR_RI is not enabled, because PACA_EXMC is being
273 * used, so nested machine check corrupts it. machine_check_common
279 LOAD_HANDLER(r12, machine_check_common)
284 b . /* prevent speculative execution */
286 TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
288 EXC_COMMON_BEGIN(machine_check_common)
290 * Machine check is different because we use a different
291 * save area: PACA_EXMC instead of PACA_EXGEN.
294 std r10,PACA_EXMC+EX_DAR(r13)
296 stw r10,PACA_EXMC+EX_DSISR(r13)
297 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
299 RECONCILE_IRQ_STATE(r10, r11)
300 ld r3,PACA_EXMC+EX_DAR(r13)
301 lwz r4,PACA_EXMC+EX_DSISR(r13)
302 /* Enable MSR_RI when finished with PACA_EXMC */
308 addi r3,r1,STACK_FRAME_OVERHEAD
309 bl machine_check_exception
312 #define MACHINE_CHECK_HANDLER_WINDUP \
313 /* Clear MSR_RI before setting SRR0 and SRR1. */\
315 mfmsr r9; /* get MSR value */ \
317 mtmsrd r9,1; /* Clear MSR_RI */ \
318 /* Move original SRR0 and SRR1 into the respective regs */ \
320 mtspr SPRN_SRR1,r9; \
322 mtspr SPRN_SRR0,r3; \
334 /* Decrement paca->in_mce. */ \
335 lhz r12,PACA_IN_MCE(r13); \
337 sth r12,PACA_IN_MCE(r13); \
339 REST_2GPRS(12, r1); \
340 /* restore original r1. */ \
344 * Handle machine check early in real mode. We come here with
345 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
347 EXC_COMMON_BEGIN(machine_check_handle_early)
348 std r0,GPR0(r1) /* Save r0 */
349 EXCEPTION_PROLOG_COMMON_3(0x200)
351 addi r3,r1,STACK_FRAME_OVERHEAD
352 bl machine_check_early
353 std r3,RESULT(r1) /* Save result */
355 #ifdef CONFIG_PPC_P7_NAP
357 * Check if thread was in power saving mode. We come here when any
358 * of the following is true:
359 * a. thread wasn't in power saving mode
360 * b. thread was in power saving mode with no state loss,
361 * supervisor state loss or hypervisor state loss.
363 * Go back to nap/sleep/winkle mode again if (b) is true.
365 rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */
366 beq 4f /* No, it wasn;t */
367 /* Thread was in power saving mode. Go back to nap again. */
370 /* Supervisor/Hypervisor state loss */
372 stb r0,PACA_NAPSTATELOST(r13)
373 3: bl machine_check_queue_event
374 MACHINE_CHECK_HANDLER_WINDUP
378 * Check what idle state this CPU was in and go back to same mode
381 lbz r3,PACA_THREAD_IDLE_STATE(r13)
382 cmpwi r3,PNV_THREAD_NAP
384 IDLE_STATE_ENTER_SEQ(PPC_NAP)
387 cmpwi r3,PNV_THREAD_SLEEP
389 IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
394 * Go back to winkle. Please note that this thread was woken up in
395 * machine check from winkle and have not restored the per-subcore
396 * state. Hence before going back to winkle, set last bit of HSPRG0
397 * to 1. This will make sure that if this thread gets woken up
398 * again at reset vector 0x100 then it will get chance to restore
403 IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
408 * Check if we are coming from hypervisor userspace. If yes then we
409 * continue in host kernel in V mode to deliver the MC event.
411 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */
413 andi. r11,r12,MSR_PR /* See if coming from user. */
414 bne 9f /* continue in V mode if we are. */
417 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
419 * We are coming from kernel context. Check if we are coming from
420 * guest. if yes, then we can continue. We will fall through
421 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
423 lbz r11,HSTATE_IN_GUEST(r13)
424 cmpwi r11,0 /* Check if coming from guest */
425 bne 9f /* continue if we are. */
428 * At this point we are not sure about what context we come from.
429 * Queue up the MCE event and return from the interrupt.
430 * But before that, check if this is an un-recoverable exception.
431 * If yes, then stay on emergency stack and panic.
435 1: mfspr r11,SPRN_SRR0
436 LOAD_HANDLER(r10,unrecover_mce)
440 * We are going down. But there are chances that we might get hit by
441 * another MCE during panic path and we may run into unstable state
442 * with no way out. Hence, turn ME bit off while going down, so that
443 * when another MCE is hit during panic path, system will checkstop
444 * and hypervisor will get restarted cleanly by SP.
447 andc r10,r10,r3 /* Turn off MSR_ME */
453 * Check if we have successfully handled/recovered from error, if not
454 * then stay on emergency stack and panic.
456 ld r3,RESULT(r1) /* Load result */
457 cmpdi r3,0 /* see if we handled MCE successfully */
459 beq 1b /* if !handled then panic */
461 * Return from MC interrupt.
462 * Queue up the MCE event so that we can log it later, while
463 * returning from kernel or opal call.
465 bl machine_check_queue_event
466 MACHINE_CHECK_HANDLER_WINDUP
467 RFI_TO_USER_OR_KERNEL
469 /* Deliver the machine check to host kernel in V mode. */
473 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
474 MACHINE_CHECK_HANDLER_WINDUP
475 b machine_check_pSeries
477 EXC_COMMON_BEGIN(unrecover_mce)
478 /* Invoke machine_check_exception to print MCE event and panic. */
479 addi r3,r1,STACK_FRAME_OVERHEAD
480 bl machine_check_exception
482 * We will not reach here. Even if we did, there is no way out. Call
483 * unrecoverable_exception and die.
485 1: addi r3,r1,STACK_FRAME_OVERHEAD
486 bl unrecoverable_exception
490 EXC_REAL_OOL(data_access, 0x300, 0x380)
491 EXC_VIRT(data_access, 0x4300, 0x4380, 0x300)
492 TRAMP_KVM_SKIP(PACA_EXGEN, 0x300)
494 EXC_COMMON_BEGIN(data_access_common)
496 * Here r13 points to the paca, r9 contains the saved CR,
497 * SRR0 and SRR1 are saved in r11 and r12,
498 * r9 - r13 are saved in paca->exgen.
501 std r10,PACA_EXGEN+EX_DAR(r13)
503 stw r10,PACA_EXGEN+EX_DSISR(r13)
504 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
505 RECONCILE_IRQ_STATE(r10, r11)
507 ld r3,PACA_EXGEN+EX_DAR(r13)
508 lwz r4,PACA_EXGEN+EX_DSISR(r13)
512 BEGIN_MMU_FTR_SECTION
513 b do_hash_page /* Try to handle as hpte fault */
516 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
519 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x400)
521 EXCEPTION_PROLOG_0(PACA_EXSLB)
522 b tramp_data_access_slb
523 EXC_REAL_END(data_access_slb, 0x380, 0x400)
525 TRAMP_REAL_BEGIN(tramp_data_access_slb)
526 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
527 std r3,PACA_EXSLB+EX_R3(r13)
531 #ifndef CONFIG_RELOCATABLE
535 * We can't just use a direct branch to slb_miss_realmode
536 * because the distance from here to there depends on where
537 * the kernel ends up being put.
540 LOAD_HANDLER(r10, slb_miss_realmode)
545 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x4400)
547 EXCEPTION_PROLOG_0(PACA_EXSLB)
548 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380)
549 std r3,PACA_EXSLB+EX_R3(r13)
553 #ifndef CONFIG_RELOCATABLE
557 * We can't just use a direct branch to slb_miss_realmode
558 * because the distance from here to there depends on where
559 * the kernel ends up being put.
562 LOAD_HANDLER(r10, slb_miss_realmode)
566 EXC_VIRT_END(data_access_slb, 0x4380, 0x4400)
567 TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
570 EXC_REAL_OOL(instruction_access, 0x400, 0x480)
571 EXC_VIRT(instruction_access, 0x4400, 0x4480, 0x400)
572 TRAMP_KVM(PACA_EXGEN, 0x400)
574 EXC_COMMON_BEGIN(instruction_access_common)
575 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
576 RECONCILE_IRQ_STATE(r10, r11)
583 BEGIN_MMU_FTR_SECTION
584 b do_hash_page /* Try to handle as hpte fault */
587 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
590 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x500)
592 EXCEPTION_PROLOG_0(PACA_EXSLB)
593 b tramp_instruction_access_slb
594 EXC_REAL_END(instruction_access_slb, 0x480, 0x500)
596 TRAMP_REAL_BEGIN(tramp_instruction_access_slb)
597 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480)
598 std r3,PACA_EXSLB+EX_R3(r13)
599 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
602 #ifndef CONFIG_RELOCATABLE
606 LOAD_HANDLER(r10, slb_miss_realmode)
611 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x4500)
613 EXCEPTION_PROLOG_0(PACA_EXSLB)
614 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480)
615 std r3,PACA_EXSLB+EX_R3(r13)
616 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
619 #ifndef CONFIG_RELOCATABLE
623 LOAD_HANDLER(r10, slb_miss_realmode)
627 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x4500)
628 TRAMP_KVM(PACA_EXSLB, 0x480)
631 /* This handler is used by both 0x380 and 0x480 slb miss interrupts */
632 EXC_COMMON_BEGIN(slb_miss_realmode)
634 * r13 points to the PACA, r9 contains the saved CR,
635 * r12 contain the saved SRR1, SRR0 is still ready for return
636 * r3 has the faulting address
637 * r9 - r13 are saved in paca->exslb.
638 * r3 is saved in paca->slb_r3
639 * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss
640 * We assume we aren't going to take any exceptions during this
644 #ifdef CONFIG_RELOCATABLE
648 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
649 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
650 std r3,PACA_EXSLB+EX_DAR(r13)
653 #ifdef CONFIG_PPC_STD_MMU_64
654 BEGIN_MMU_FTR_SECTION
655 bl slb_allocate_realmode
656 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
659 ld r10,PACA_EXSLB+EX_LR(r13)
660 ld r3,PACA_EXSLB+EX_R3(r13)
661 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
664 beq 8f /* if bad address, make full stack frame */
666 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
668 andi. r10,r12,MSR_PR /* check for user mode (PR != 0) */
671 /* All done -- return from exception. */
676 mtcrf 0x02,r9 /* I/D indication is in cr6 */
677 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
680 RESTORE_PPR_PACA(PACA_EXSLB, r9)
681 ld r9,PACA_EXSLB+EX_R9(r13)
682 ld r10,PACA_EXSLB+EX_R10(r13)
683 ld r11,PACA_EXSLB+EX_R11(r13)
684 ld r12,PACA_EXSLB+EX_R12(r13)
685 ld r13,PACA_EXSLB+EX_R13(r13)
687 b . /* prevent speculative execution */
693 mtcrf 0x02,r9 /* I/D indication is in cr6 */
694 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
697 RESTORE_PPR_PACA(PACA_EXSLB, r9)
698 ld r9,PACA_EXSLB+EX_R9(r13)
699 ld r10,PACA_EXSLB+EX_R10(r13)
700 ld r11,PACA_EXSLB+EX_R11(r13)
701 ld r12,PACA_EXSLB+EX_R12(r13)
702 ld r13,PACA_EXSLB+EX_R13(r13)
704 b . /* prevent speculative execution */
706 2: mfspr r11,SPRN_SRR0
707 LOAD_HANDLER(r10,unrecov_slb)
714 8: mfspr r11,SPRN_SRR0
715 LOAD_HANDLER(r10,bad_addr_slb)
722 EXC_COMMON_BEGIN(unrecov_slb)
723 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
724 RECONCILE_IRQ_STATE(r10, r11)
726 1: addi r3,r1,STACK_FRAME_OVERHEAD
727 bl unrecoverable_exception
730 EXC_COMMON_BEGIN(bad_addr_slb)
731 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB)
732 RECONCILE_IRQ_STATE(r10, r11)
733 ld r3, PACA_EXSLB+EX_DAR(r13)
736 li r10, 0x481 /* fix trap number for I-SLB miss */
739 addi r3, r1, STACK_FRAME_OVERHEAD
743 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x600)
744 .globl hardware_interrupt_hv;
745 hardware_interrupt_hv:
747 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
748 EXC_HV, SOFTEN_TEST_HV)
750 KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x502)
752 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
753 EXC_STD, SOFTEN_TEST_PR)
755 KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500)
756 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
757 EXC_REAL_END(hardware_interrupt, 0x500, 0x600)
759 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x4600)
760 .globl hardware_interrupt_relon_hv;
761 hardware_interrupt_relon_hv:
763 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV)
765 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR)
766 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
767 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x4600)
769 EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
772 EXC_REAL(alignment, 0x600, 0x700)
773 EXC_VIRT(alignment, 0x4600, 0x4700, 0x600)
774 TRAMP_KVM(PACA_EXGEN, 0x600)
775 EXC_COMMON_BEGIN(alignment_common)
777 std r10,PACA_EXGEN+EX_DAR(r13)
779 stw r10,PACA_EXGEN+EX_DSISR(r13)
780 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
781 ld r3,PACA_EXGEN+EX_DAR(r13)
782 lwz r4,PACA_EXGEN+EX_DSISR(r13)
786 RECONCILE_IRQ_STATE(r10, r11)
787 addi r3,r1,STACK_FRAME_OVERHEAD
788 bl alignment_exception
792 EXC_REAL(program_check, 0x700, 0x800)
793 EXC_VIRT(program_check, 0x4700, 0x4800, 0x700)
794 TRAMP_KVM(PACA_EXGEN, 0x700)
795 EXC_COMMON_BEGIN(program_check_common)
797 * It's possible to receive a TM Bad Thing type program check with
798 * userspace register values (in particular r1), but with SRR1 reporting
799 * that we came from the kernel. Normally that would confuse the bad
800 * stack logic, and we would report a bad kernel stack pointer. Instead
801 * we switch to the emergency stack if we're taking a TM Bad Thing from
804 li r10,MSR_PR /* Build a mask of MSR_PR .. */
805 oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */
806 and r10,r10,r12 /* Mask SRR1 with that. */
807 srdi r10,r10,8 /* Shift it so we can compare */
808 cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */
809 bne 1f /* If != go to normal path. */
811 /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */
812 andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */
813 /* 3 in EXCEPTION_PROLOG_COMMON */
814 mr r10,r1 /* Save r1 */
815 ld r1,PACAEMERGSP(r13) /* Use emergency stack */
816 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
817 b 3f /* Jump into the macro !! */
818 1: EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
820 RECONCILE_IRQ_STATE(r10, r11)
821 addi r3,r1,STACK_FRAME_OVERHEAD
822 bl program_check_exception
826 EXC_REAL(fp_unavailable, 0x800, 0x900)
827 EXC_VIRT(fp_unavailable, 0x4800, 0x4900, 0x800)
828 TRAMP_KVM(PACA_EXGEN, 0x800)
829 EXC_COMMON_BEGIN(fp_unavailable_common)
830 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
831 bne 1f /* if from user, just load it up */
833 RECONCILE_IRQ_STATE(r10, r11)
834 addi r3,r1,STACK_FRAME_OVERHEAD
835 bl kernel_fp_unavailable_exception
838 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
840 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
841 * transaction), go do TM stuff
843 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
845 END_FTR_SECTION_IFSET(CPU_FTR_TM)
848 b fast_exception_return
849 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
850 2: /* User process was in a transaction */
852 RECONCILE_IRQ_STATE(r10, r11)
853 addi r3,r1,STACK_FRAME_OVERHEAD
859 EXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x980)
860 EXC_VIRT_OOL_MASKABLE(decrementer, 0x4900, 0x4980, 0x900)
861 TRAMP_KVM(PACA_EXGEN, 0x900)
862 EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
865 EXC_REAL_OOL_HV(hdecrementer, 0x980, 0xa00)
866 EXC_VIRT_OOL_HV(hdecrementer, 0x4980, 0x4a00, 0x980)
867 TRAMP_KVM_HV(PACA_EXGEN, 0x980)
868 EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
871 EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0xb00)
872 EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x4b00, 0xa00)
873 TRAMP_KVM(PACA_EXGEN, 0xa00)
874 #ifdef CONFIG_PPC_DOORBELL
875 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
877 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception)
881 EXC_REAL(trap_0b, 0xb00, 0xc00)
882 EXC_VIRT(trap_0b, 0x4b00, 0x4c00, 0xb00)
883 TRAMP_KVM(PACA_EXGEN, 0xb00)
884 EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
886 #define LOAD_SYSCALL_HANDLER(reg) \
887 __LOAD_HANDLER(reg, system_call_common)
889 /* Syscall routine is used twice, in reloc-off and reloc-on paths */
890 #define SYSCALL_PSERIES_1 \
894 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \
897 INTERRUPT_TO_KERNEL ; \
898 mfspr r11,SPRN_SRR0 ; \
901 #define SYSCALL_PSERIES_2_RFID \
902 mfspr r12,SPRN_SRR1 ; \
903 LOAD_SYSCALL_HANDLER(r10) ; \
904 mtspr SPRN_SRR0,r10 ; \
905 ld r10,PACAKMSR(r13) ; \
906 mtspr SPRN_SRR1,r10 ; \
908 b . ; /* prevent speculative execution */
910 #define SYSCALL_PSERIES_3 \
911 /* Fast LE/BE switch system call */ \
912 1: mfspr r12,SPRN_SRR1 ; \
913 xori r12,r12,MSR_LE ; \
914 mtspr SPRN_SRR1,r12 ; \
915 RFI_TO_USER ; /* return to userspace */ \
916 b . ; /* prevent speculative execution */
918 #if defined(CONFIG_RELOCATABLE)
920 * We can't branch directly so we do it via the CTR which
921 * is volatile across system calls.
923 #define SYSCALL_PSERIES_2_DIRECT \
924 LOAD_SYSCALL_HANDLER(r12) ; \
926 mfspr r12,SPRN_SRR1 ; \
931 /* We can branch directly */
932 #define SYSCALL_PSERIES_2_DIRECT \
933 mfspr r12,SPRN_SRR1 ; \
935 mtmsrd r10,1 ; /* Set RI (EE=0) */ \
936 b system_call_common ;
939 EXC_REAL_BEGIN(system_call, 0xc00, 0xd00)
941 * If CONFIG_KVM_BOOK3S_64_HANDLER is set, save the PPR (on systems
942 * that support it) before changing to HMT_MEDIUM. That allows the KVM
943 * code to save that value into the guest state (it is the guest's PPR
944 * value). Otherwise just change to HMT_MEDIUM as userspace has
945 * already saved the PPR.
947 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
950 std r9,PACA_EXGEN+EX_R9(r13)
951 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR);
953 std r10,PACA_EXGEN+EX_R10(r13)
954 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r9, CPU_FTR_HAS_PPR);
962 SYSCALL_PSERIES_2_RFID
964 EXC_REAL_END(system_call, 0xc00, 0xd00)
966 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x4d00)
969 SYSCALL_PSERIES_2_DIRECT
971 EXC_VIRT_END(system_call, 0x4c00, 0x4d00)
973 TRAMP_KVM(PACA_EXGEN, 0xc00)
976 EXC_REAL(single_step, 0xd00, 0xe00)
977 EXC_VIRT(single_step, 0x4d00, 0x4e00, 0xd00)
978 TRAMP_KVM(PACA_EXGEN, 0xd00)
979 EXC_COMMON(single_step_common, 0xd00, single_step_exception)
981 EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0xe20)
982 EXC_VIRT_NONE(0x4e00, 0x4e20)
983 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00)
984 EXC_COMMON_BEGIN(h_data_storage_common)
986 std r10,PACA_EXGEN+EX_DAR(r13)
987 mfspr r10,SPRN_HDSISR
988 stw r10,PACA_EXGEN+EX_DSISR(r13)
989 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
991 RECONCILE_IRQ_STATE(r10, r11)
992 addi r3,r1,STACK_FRAME_OVERHEAD
997 EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0xe40)
998 EXC_VIRT_NONE(0x4e20, 0x4e40)
999 TRAMP_KVM_HV(PACA_EXGEN, 0xe20)
1000 EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
1003 EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0xe60)
1004 EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x4e60, 0xe40)
1005 TRAMP_KVM_HV(PACA_EXGEN, 0xe40)
1006 EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
1010 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early
1011 * first, and then eventaully from there to the trampoline to get into virtual
1014 __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0xe80, hmi_exception_early)
1015 __TRAMP_REAL_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60)
1016 EXC_VIRT_NONE(0x4e60, 0x4e80)
1017 TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
1018 TRAMP_REAL_BEGIN(hmi_exception_early)
1019 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60)
1020 mr r10,r1 /* Save r1 */
1021 ld r1,PACAEMERGSP(r13) /* Use emergency stack */
1022 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1023 std r9,_CCR(r1) /* save CR in stackframe */
1024 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */
1025 std r11,_NIP(r1) /* save HSRR0 in stackframe */
1026 mfspr r12,SPRN_HSRR1 /* Save SRR1 */
1027 std r12,_MSR(r1) /* save SRR1 in stackframe */
1028 std r10,0(r1) /* make stack chain pointer */
1029 std r0,GPR0(r1) /* save r0 in stackframe */
1030 std r10,GPR1(r1) /* save r1 in stackframe */
1031 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
1032 EXCEPTION_PROLOG_COMMON_3(0xe60)
1033 addi r3,r1,STACK_FRAME_OVERHEAD
1034 bl hmi_exception_realmode
1035 /* Windup the stack. */
1036 /* Move original HSRR0 and HSRR1 into the respective regs */
1054 /* restore original r1. */
1058 * Go to virtual mode and pull the HMI event information from
1061 .globl hmi_exception_after_realmode
1062 hmi_exception_after_realmode:
1064 EXCEPTION_PROLOG_0(PACA_EXGEN)
1065 b tramp_real_hmi_exception
1067 EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception)
1070 EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0xea0)
1071 EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x4ea0, 0xe80)
1072 TRAMP_KVM_HV(PACA_EXGEN, 0xe80)
1073 #ifdef CONFIG_PPC_DOORBELL
1074 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
1076 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception)
1080 EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0xec0)
1081 EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x4ec0, 0xea0)
1082 TRAMP_KVM_HV(PACA_EXGEN, 0xea0)
1083 EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
1086 EXC_REAL_NONE(0xec0, 0xf00)
1087 EXC_VIRT_NONE(0x4ec0, 0x4f00)
1090 EXC_REAL_OOL(performance_monitor, 0xf00, 0xf20)
1091 EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x4f20, 0xf00)
1092 TRAMP_KVM(PACA_EXGEN, 0xf00)
1093 EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
1096 EXC_REAL_OOL(altivec_unavailable, 0xf20, 0xf40)
1097 EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x4f40, 0xf20)
1098 TRAMP_KVM(PACA_EXGEN, 0xf20)
1099 EXC_COMMON_BEGIN(altivec_unavailable_common)
1100 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1101 #ifdef CONFIG_ALTIVEC
1104 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1105 BEGIN_FTR_SECTION_NESTED(69)
1106 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1107 * transaction), go do TM stuff
1109 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1111 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1114 b fast_exception_return
1115 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1116 2: /* User process was in a transaction */
1118 RECONCILE_IRQ_STATE(r10, r11)
1119 addi r3,r1,STACK_FRAME_OVERHEAD
1120 bl altivec_unavailable_tm
1124 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1127 RECONCILE_IRQ_STATE(r10, r11)
1128 addi r3,r1,STACK_FRAME_OVERHEAD
1129 bl altivec_unavailable_exception
1133 EXC_REAL_OOL(vsx_unavailable, 0xf40, 0xf60)
1134 EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x4f60, 0xf40)
1135 TRAMP_KVM(PACA_EXGEN, 0xf40)
1136 EXC_COMMON_BEGIN(vsx_unavailable_common)
1137 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
1141 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1142 BEGIN_FTR_SECTION_NESTED(69)
1143 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1144 * transaction), go do TM stuff
1146 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1148 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1151 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1152 2: /* User process was in a transaction */
1154 RECONCILE_IRQ_STATE(r10, r11)
1155 addi r3,r1,STACK_FRAME_OVERHEAD
1156 bl vsx_unavailable_tm
1160 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1163 RECONCILE_IRQ_STATE(r10, r11)
1164 addi r3,r1,STACK_FRAME_OVERHEAD
1165 bl vsx_unavailable_exception
1169 EXC_REAL_OOL(facility_unavailable, 0xf60, 0xf80)
1170 EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x4f80, 0xf60)
1171 TRAMP_KVM(PACA_EXGEN, 0xf60)
1172 EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
1175 EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0xfa0)
1176 EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x4fa0, 0xf80)
1177 TRAMP_KVM_HV(PACA_EXGEN, 0xf80)
1178 EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
1181 EXC_REAL_NONE(0xfa0, 0x1200)
1182 EXC_VIRT_NONE(0x4fa0, 0x5200)
1184 #ifdef CONFIG_CBE_RAS
1185 EXC_REAL_HV(cbe_system_error, 0x1200, 0x1300)
1186 EXC_VIRT_NONE(0x5200, 0x5300)
1187 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200)
1188 EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
1189 #else /* CONFIG_CBE_RAS */
1190 EXC_REAL_NONE(0x1200, 0x1300)
1191 EXC_VIRT_NONE(0x5200, 0x5300)
1195 EXC_REAL(instruction_breakpoint, 0x1300, 0x1400)
1196 EXC_VIRT(instruction_breakpoint, 0x5300, 0x5400, 0x1300)
1197 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300)
1198 EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
1200 EXC_REAL_NONE(0x1400, 0x1500)
1201 EXC_VIRT_NONE(0x5400, 0x5500)
1203 EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x1600)
1204 mtspr SPRN_SPRG_HSCRATCH0,r13
1205 EXCEPTION_PROLOG_0(PACA_EXGEN)
1206 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500)
1208 #ifdef CONFIG_PPC_DENORMALISATION
1209 mfspr r10,SPRN_HSRR1
1210 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
1211 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */
1212 addi r11,r11,-4 /* HSRR0 is next instruction */
1217 EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV)
1218 EXC_REAL_END(denorm_exception_hv, 0x1500, 0x1600)
1220 #ifdef CONFIG_PPC_DENORMALISATION
1221 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x5600)
1222 b exc_real_0x1500_denorm_exception_hv
1223 EXC_VIRT_END(denorm_exception, 0x5500, 0x5600)
1225 EXC_VIRT_NONE(0x5500, 0x5600)
1228 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500)
1230 #ifdef CONFIG_PPC_DENORMALISATION
1231 TRAMP_REAL_BEGIN(denorm_assist)
1234 * To denormalise we need to move a copy of the register to itself.
1235 * For POWER6 do that here for all FP regs.
1238 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
1239 xori r10,r10,(MSR_FE0|MSR_FE1)
1243 #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1
1244 #define FMR4(n) FMR2(n) ; FMR2(n+2)
1245 #define FMR8(n) FMR4(n) ; FMR4(n+4)
1246 #define FMR16(n) FMR8(n) ; FMR8(n+8)
1247 #define FMR32(n) FMR16(n) ; FMR16(n+16)
1252 * To denormalise we need to move a copy of the register to itself.
1253 * For POWER7 do that here for the first 32 VSX registers only.
1256 oris r10,r10,MSR_VSX@h
1260 #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
1261 #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
1262 #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
1263 #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
1264 #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
1267 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
1271 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1273 * To denormalise we need to move a copy of the register to itself.
1274 * For POWER8 we need to do that for all 64 VSX registers
1278 mtspr SPRN_HSRR0,r11
1280 ld r9,PACA_EXGEN+EX_R9(r13)
1281 RESTORE_PPR_PACA(PACA_EXGEN, r10)
1283 ld r10,PACA_EXGEN+EX_CFAR(r13)
1285 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1286 ld r10,PACA_EXGEN+EX_R10(r13)
1287 ld r11,PACA_EXGEN+EX_R11(r13)
1288 ld r12,PACA_EXGEN+EX_R12(r13)
1289 ld r13,PACA_EXGEN+EX_R13(r13)
1294 EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception)
1297 #ifdef CONFIG_CBE_RAS
1298 EXC_REAL_HV(cbe_maintenance, 0x1600, 0x1700)
1299 EXC_VIRT_NONE(0x5600, 0x5700)
1300 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600)
1301 EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
1302 #else /* CONFIG_CBE_RAS */
1303 EXC_REAL_NONE(0x1600, 0x1700)
1304 EXC_VIRT_NONE(0x5600, 0x5700)
1308 EXC_REAL(altivec_assist, 0x1700, 0x1800)
1309 EXC_VIRT(altivec_assist, 0x5700, 0x5800, 0x1700)
1310 TRAMP_KVM(PACA_EXGEN, 0x1700)
1311 #ifdef CONFIG_ALTIVEC
1312 EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
1314 EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
1318 #ifdef CONFIG_CBE_RAS
1319 EXC_REAL_HV(cbe_thermal, 0x1800, 0x1900)
1320 EXC_VIRT_NONE(0x5800, 0x5900)
1321 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800)
1322 EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
1323 #else /* CONFIG_CBE_RAS */
1324 EXC_REAL_NONE(0x1800, 0x1900)
1325 EXC_VIRT_NONE(0x5800, 0x5900)
1330 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
1331 * - If it was a decrementer interrupt, we bump the dec to max and and return.
1332 * - If it was a doorbell we return immediately since doorbells are edge
1333 * triggered and won't automatically refire.
1334 * - If it was a HMI we return immediately since we handled it in realmode
1335 * and it won't refire.
1336 * - else we hard disable and return.
1337 * This is called with r10 containing the value to OR to the paca field.
1339 #define MASKED_INTERRUPT(_H) \
1340 masked_##_H##interrupt: \
1341 std r11,PACA_EXGEN+EX_R11(r13); \
1342 lbz r11,PACAIRQHAPPENED(r13); \
1344 stb r11,PACAIRQHAPPENED(r13); \
1345 cmpwi r10,PACA_IRQ_DEC; \
1348 ori r10,r10,0xffff; \
1349 mtspr SPRN_DEC,r10; \
1351 1: cmpwi r10,PACA_IRQ_DBELL; \
1353 cmpwi r10,PACA_IRQ_HMI; \
1355 mfspr r10,SPRN_##_H##SRR1; \
1356 rldicl r10,r10,48,1; /* clear MSR_EE */ \
1357 rotldi r10,r10,16; \
1358 mtspr SPRN_##_H##SRR1,r10; \
1360 ld r9,PACA_EXGEN+EX_R9(r13); \
1361 ld r10,PACA_EXGEN+EX_R10(r13); \
1362 ld r11,PACA_EXGEN+EX_R11(r13); \
1363 GET_SCRATCH0(r13); \
1364 ##_H##RFI_TO_KERNEL; \
1367 TRAMP_REAL_BEGIN(stf_barrier_fallback)
1368 std r9,PACA_EXRFI+EX_R9(r13)
1369 std r10,PACA_EXRFI+EX_R10(r13)
1371 ld r9,PACA_EXRFI+EX_R9(r13)
1372 ld r10,PACA_EXRFI+EX_R10(r13)
1380 /* Clobbers r10, r11, ctr */
1381 .macro L1D_DISPLACEMENT_FLUSH
1382 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
1383 ld r11,PACA_L1D_FLUSH_SIZE(r13)
1384 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
1386 DCBT_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
1388 /* order ld/st prior to dcbt stop all streams with flushing */
1392 * The load adresses are at staggered offsets within cachelines,
1393 * which suits some pipelines better (on others it should not
1397 ld r11,(0x80 + 8)*0(r10)
1398 ld r11,(0x80 + 8)*1(r10)
1399 ld r11,(0x80 + 8)*2(r10)
1400 ld r11,(0x80 + 8)*3(r10)
1401 ld r11,(0x80 + 8)*4(r10)
1402 ld r11,(0x80 + 8)*5(r10)
1403 ld r11,(0x80 + 8)*6(r10)
1404 ld r11,(0x80 + 8)*7(r10)
1411 _GLOBAL(do_uaccess_flush)
1412 UACCESS_FLUSH_FIXUP_SECTION
1417 L1D_DISPLACEMENT_FLUSH
1419 _ASM_NOKPROBE_SYMBOL(do_uaccess_flush)
1420 EXPORT_SYMBOL(do_uaccess_flush)
1423 * Real mode exceptions actually use this too, but alternate
1424 * instruction code patches (which end up in the common .text area)
1425 * cannot reach these if they are put there.
1427 USE_FIXED_SECTION(virt_trampolines)
1431 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1432 TRAMP_REAL_BEGIN(kvmppc_skip_interrupt)
1434 * Here all GPRs are unchanged from when the interrupt happened
1435 * except for r13, which is saved in SPRG_SCRATCH0.
1437 mfspr r13, SPRN_SRR0
1439 mtspr SPRN_SRR0, r13
1444 TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt)
1446 * Here all GPRs are unchanged from when the interrupt happened
1447 * except for r13, which is saved in SPRG_SCRATCH0.
1449 mfspr r13, SPRN_HSRR0
1451 mtspr SPRN_HSRR0, r13
1458 * Ensure that any handlers that get invoked from the exception prologs
1459 * above are below the first 64KB (0x10000) of the kernel image because
1460 * the prologs assemble the addresses of these handlers using the
1461 * LOAD_HANDLER macro, which uses an ori instruction.
1464 /*** Common interrupt handlers ***/
1468 * Relocation-on interrupts: A subset of the interrupts can be delivered
1469 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
1470 * it. Addresses are the same as the original interrupt addresses, but
1471 * offset by 0xc000000000004000.
1472 * It's impossible to receive interrupts below 0x300 via this mechanism.
1473 * KVM: None of these traps are from the guest ; anything that escalated
1474 * to HV=1 from HV=0 is delivered via real mode handlers.
1478 * This uses the standard macro, since the original 0x300 vector
1479 * only has extra guff for STAB-based processors -- which never
1483 EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
1484 b __ppc64_runlatch_on
1486 USE_FIXED_SECTION(virt_trampolines)
1488 * The __end_interrupts marker must be past the out-of-line (OOL)
1489 * handlers, so that they are copied to real address 0x100 when running
1490 * a relocatable kernel. This ensures they can be reached from the short
1491 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
1492 * directly, without using LOAD_HANDLER().
1495 .globl __end_interrupts
1497 DEFINE_FIXED_SYMBOL(__end_interrupts)
1499 #ifdef CONFIG_PPC_970_NAP
1500 EXC_COMMON_BEGIN(power4_fixup_nap)
1502 std r9,TI_LOCAL_FLAGS(r11)
1503 ld r10,_LINK(r1) /* make idle task do the */
1504 std r10,_NIP(r1) /* equivalent of a blr */
1508 CLOSE_FIXED_SECTION(real_vectors);
1509 CLOSE_FIXED_SECTION(real_trampolines);
1510 CLOSE_FIXED_SECTION(virt_vectors);
1511 CLOSE_FIXED_SECTION(virt_trampolines);
1520 #ifdef CONFIG_PPC_STD_MMU_64
1521 andis. r0,r4,0xa450 /* weird error? */
1522 bne- handle_page_fault /* if not, try to insert a HPTE */
1523 CURRENT_THREAD_INFO(r11, r1)
1524 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
1525 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */
1526 bne 77f /* then don't call hash_page now */
1529 * r3 contains the faulting address
1531 * r5 contains the trap number
1534 * at return r3 = 0 for success, 1 for page fault, negative for error
1538 bl __hash_page /* build HPTE if possible */
1539 cmpdi r3,0 /* see if __hash_page succeeded */
1542 beq fast_exc_return_irq /* Return from exception on success */
1547 /* Reload DSISR into r4 for the DABR check below */
1549 #endif /* CONFIG_PPC_STD_MMU_64 */
1551 /* Here we have a page fault that hash_page can't handle. */
1553 11: andis. r0,r4,DSISR_DABRMATCH@h
1554 bne- handle_dabr_fault
1557 addi r3,r1,STACK_FRAME_OVERHEAD
1560 beq+ ret_from_except_lite
1563 addi r3,r1,STACK_FRAME_OVERHEAD
1568 /* We have a data breakpoint exception - handle it */
1573 addi r3,r1,STACK_FRAME_OVERHEAD
1576 * do_break() may have changed the NV GPRS while handling a breakpoint.
1577 * If so, we need to restore them with their updated values. Don't use
1578 * ret_from_except_lite here.
1583 #ifdef CONFIG_PPC_STD_MMU_64
1584 /* We have a page fault that hash_page could handle but HV refused
1589 addi r3,r1,STACK_FRAME_OVERHEAD
1596 * We come here as a result of a DSI at a point where we don't want
1597 * to call hash_page, such as when we are accessing memory (possibly
1598 * user memory) inside a PMU interrupt that occurred while interrupts
1599 * were soft-disabled. We want to invoke the exception handler for
1600 * the access, or panic if there isn't a handler.
1604 addi r3,r1,STACK_FRAME_OVERHEAD
1610 * Here we have detected that the kernel stack pointer is bad.
1611 * R9 contains the saved CR, r13 points to the paca,
1612 * r10 contains the (bad) kernel stack pointer,
1613 * r11 and r12 contain the saved SRR0 and SRR1.
1614 * We switch to using an emergency stack, save the registers there,
1615 * and call kernel_bad_stack(), which panics.
1618 ld r1,PACAEMERGSP(r13)
1619 subi r1,r1,64+INT_FRAME_SIZE
1625 mfspr r12,SPRN_DSISR
1651 std r10,ORIG_GPR3(r1)
1652 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1655 lhz r12,PACA_TRAP_SAVE(r13)
1657 addi r11,r1,INT_FRAME_SIZE
1662 ld r11,exception_marker@toc(r2)
1664 std r11,STACK_FRAME_OVERHEAD-16(r1)
1665 1: addi r3,r1,STACK_FRAME_OVERHEAD
1669 .globl rfi_flush_fallback
1673 std r9,PACA_EXRFI+EX_R9(r13)
1674 std r10,PACA_EXRFI+EX_R10(r13)
1675 std r11,PACA_EXRFI+EX_R11(r13)
1677 L1D_DISPLACEMENT_FLUSH
1679 ld r9,PACA_EXRFI+EX_R9(r13)
1680 ld r10,PACA_EXRFI+EX_R10(r13)
1681 ld r11,PACA_EXRFI+EX_R11(r13)
1685 .globl hrfi_flush_fallback
1686 hrfi_flush_fallback:
1689 std r9,PACA_EXRFI+EX_R9(r13)
1690 std r10,PACA_EXRFI+EX_R10(r13)
1691 std r11,PACA_EXRFI+EX_R11(r13)
1693 L1D_DISPLACEMENT_FLUSH
1695 ld r9,PACA_EXRFI+EX_R9(r13)
1696 ld r10,PACA_EXRFI+EX_R10(r13)
1697 ld r11,PACA_EXRFI+EX_R11(r13)
1701 .globl entry_flush_fallback
1702 entry_flush_fallback:
1703 std r9,PACA_EXRFI+EX_R9(r13)
1704 std r10,PACA_EXRFI+EX_R10(r13)
1705 std r11,PACA_EXRFI+EX_R11(r13)
1707 L1D_DISPLACEMENT_FLUSH
1709 ld r9,PACA_EXRFI+EX_R9(r13)
1710 ld r10,PACA_EXRFI+EX_R10(r13)
1711 ld r11,PACA_EXRFI+EX_R11(r13)
1716 * Called from arch_local_irq_enable when an interrupt needs
1717 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate
1718 * which kind of interrupt. MSR:EE is already off. We generate a
1719 * stackframe like if a real interrupt had happened.
1721 * Note: While MSR:EE is off, we need to make sure that _MSR
1722 * in the generated frame has EE set to 1 or the exception
1723 * handler will not properly re-enable them.
1725 _GLOBAL(__replay_interrupt)
1726 /* We are going to jump to the exception common code which
1727 * will retrieve various register values from the PACA which
1728 * we don't give a damn about, so we don't bother storing them.
1735 beq decrementer_common
1737 beq hardware_interrupt_common
1740 beq h_doorbell_common
1742 beq h_virt_irq_common
1744 beq hmi_exception_common
1747 beq doorbell_super_common
1748 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)