1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Boot code and exception vectors for Book3E processors
5 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
8 #include <linux/linkage.h>
9 #include <linux/threads.h>
12 #include <asm/ppc_asm.h>
13 #include <asm/asm-offsets.h>
14 #include <asm/cputable.h>
15 #include <asm/setup.h>
16 #include <asm/thread_info.h>
17 #include <asm/reg_a2.h>
18 #include <asm/exception-64e.h>
20 #include <asm/irqflags.h>
21 #include <asm/ptrace.h>
22 #include <asm/ppc-opcode.h>
24 #include <asm/hw_irq.h>
25 #include <asm/kvm_asm.h>
26 #include <asm/kvm_booke_hv_asm.h>
27 #include <asm/feature-fixups.h>
28 #include <asm/context_tracking.h>
30 /* 64e interrupt returns always use SRR registers */
31 #define fast_interrupt_return fast_interrupt_return_srr
32 #define interrupt_return interrupt_return_srr
34 /* XXX This will ultimately add space for a special exception save
35 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
36 * when taking special interrupts. For now we don't support that,
37 * special interrupts from within a non-standard level will probably
40 #define SPECIAL_EXC_SRR0 0
41 #define SPECIAL_EXC_SRR1 1
42 #define SPECIAL_EXC_SPRG_GEN 2
43 #define SPECIAL_EXC_SPRG_TLB 3
44 #define SPECIAL_EXC_MAS0 4
45 #define SPECIAL_EXC_MAS1 5
46 #define SPECIAL_EXC_MAS2 6
47 #define SPECIAL_EXC_MAS3 7
48 #define SPECIAL_EXC_MAS6 8
49 #define SPECIAL_EXC_MAS7 9
50 #define SPECIAL_EXC_MAS5 10 /* E.HV only */
51 #define SPECIAL_EXC_MAS8 11 /* E.HV only */
52 #define SPECIAL_EXC_IRQHAPPENED 12
53 #define SPECIAL_EXC_DEAR 13
54 #define SPECIAL_EXC_ESR 14
55 #define SPECIAL_EXC_SOFTE 15
56 #define SPECIAL_EXC_CSRR0 16
57 #define SPECIAL_EXC_CSRR1 17
58 /* must be even to keep 16-byte stack alignment */
59 #define SPECIAL_EXC_END 18
61 #define SPECIAL_EXC_FRAME_SIZE (INT_FRAME_SIZE + SPECIAL_EXC_END * 8)
62 #define SPECIAL_EXC_FRAME_OFFS (INT_FRAME_SIZE - 288)
64 #define SPECIAL_EXC_STORE(reg, name) \
65 std reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
67 #define SPECIAL_EXC_LOAD(reg, name) \
68 ld reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
70 SYM_CODE_START_LOCAL(special_reg_save)
72 * We only need (or have stack space) to save this stuff if
73 * we interrupted the kernel.
80 * Advance to the next TLB exception frame for handler
81 * types that don't do it automatically.
83 LOAD_REG_ADDR(r11,extlb_level_exc)
85 mfspr r10,SPRN_SPRG_TLB_EXFRAME
87 mtspr SPRN_SPRG_TLB_EXFRAME,r10
90 * Save registers needed to allow nesting of certain exceptions
91 * (such as TLB misses) inside special exception levels
94 SPECIAL_EXC_STORE(r10,SRR0)
96 SPECIAL_EXC_STORE(r10,SRR1)
97 mfspr r10,SPRN_SPRG_GEN_SCRATCH
98 SPECIAL_EXC_STORE(r10,SPRG_GEN)
99 mfspr r10,SPRN_SPRG_TLB_SCRATCH
100 SPECIAL_EXC_STORE(r10,SPRG_TLB)
102 SPECIAL_EXC_STORE(r10,MAS0)
104 SPECIAL_EXC_STORE(r10,MAS1)
106 SPECIAL_EXC_STORE(r10,MAS2)
108 SPECIAL_EXC_STORE(r10,MAS3)
110 SPECIAL_EXC_STORE(r10,MAS6)
112 SPECIAL_EXC_STORE(r10,MAS7)
115 SPECIAL_EXC_STORE(r10,MAS5)
117 SPECIAL_EXC_STORE(r10,MAS8)
119 /* MAS5/8 could have inappropriate values if we interrupted KVM code */
123 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
125 SPECIAL_EXC_STORE(r10,DEAR)
127 SPECIAL_EXC_STORE(r10,ESR)
130 SPECIAL_EXC_STORE(r10,CSRR0)
132 SPECIAL_EXC_STORE(r10,CSRR1)
135 SYM_CODE_END(special_reg_save)
137 SYM_CODE_START_LOCAL(ret_from_level_except)
145 LOAD_REG_ADDR(r11,extlb_level_exc)
147 mfspr r10,SPRN_SPRG_TLB_EXFRAME
149 mtspr SPRN_SPRG_TLB_EXFRAME,r10
152 * It's possible that the special level exception interrupted a
153 * TLB miss handler, and inserted the same entry that the
154 * interrupted handler was about to insert. On CPUs without TLB
155 * write conditional, this can result in a duplicate TLB entry.
156 * Wipe all non-bolted entries to be safe.
158 * Note that this doesn't protect against any TLB misses
159 * we may take accessing the stack from here to the end of
160 * the special level exception. It's not clear how we can
161 * reasonably protect against that, but only CPUs with
162 * neither TLB write conditional nor bolted kernel memory
163 * are affected. Do any such CPUs even exist?
169 SPECIAL_EXC_LOAD(r10,SRR0)
171 SPECIAL_EXC_LOAD(r10,SRR1)
173 SPECIAL_EXC_LOAD(r10,SPRG_GEN)
174 mtspr SPRN_SPRG_GEN_SCRATCH,r10
175 SPECIAL_EXC_LOAD(r10,SPRG_TLB)
176 mtspr SPRN_SPRG_TLB_SCRATCH,r10
177 SPECIAL_EXC_LOAD(r10,MAS0)
179 SPECIAL_EXC_LOAD(r10,MAS1)
181 SPECIAL_EXC_LOAD(r10,MAS2)
183 SPECIAL_EXC_LOAD(r10,MAS3)
185 SPECIAL_EXC_LOAD(r10,MAS6)
187 SPECIAL_EXC_LOAD(r10,MAS7)
190 SPECIAL_EXC_LOAD(r10,MAS5)
192 SPECIAL_EXC_LOAD(r10,MAS8)
194 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
196 SPECIAL_EXC_LOAD(r10,DEAR)
198 SPECIAL_EXC_LOAD(r10,ESR)
201 stdcx. r0,0,r1 /* to clear the reservation */
211 SYM_CODE_END(ret_from_level_except)
213 .macro ret_from_level srr0 srr1 paca_ex scratch
214 bl ret_from_level_except
222 REST_GPRS(10, 12, r1)
225 std r10,\paca_ex+EX_R10(r13);
226 std r11,\paca_ex+EX_R11(r13);
233 ld r10,\paca_ex+EX_R10(r13)
234 ld r11,\paca_ex+EX_R11(r13)
238 SYM_CODE_START_LOCAL(ret_from_crit_except)
239 ret_from_level SPRN_CSRR0 SPRN_CSRR1 PACA_EXCRIT SPRN_SPRG_CRIT_SCRATCH
241 SYM_CODE_END(ret_from_crit_except)
243 SYM_CODE_START_LOCAL(ret_from_mc_except)
244 ret_from_level SPRN_MCSRR0 SPRN_MCSRR1 PACA_EXMC SPRN_SPRG_MC_SCRATCH
246 SYM_CODE_END(ret_from_mc_except)
248 /* Exception prolog code for all exceptions */
249 #define EXCEPTION_PROLOG(n, intnum, type, addition) \
250 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
251 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
252 std r10,PACA_EX##type+EX_R10(r13); \
253 std r11,PACA_EX##type+EX_R11(r13); \
254 mfcr r10; /* save CR */ \
255 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
256 DO_KVM intnum,SPRN_##type##_SRR1; /* KVM hook */ \
257 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
258 addition; /* additional code for that exc. */ \
259 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
260 type##_SET_KSTACK; /* get special stack if necessary */\
261 andi. r10,r11,MSR_PR; /* save stack pointer */ \
262 beq 1f; /* branch around if supervisor */ \
263 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\
264 1: type##_BTB_FLUSH \
265 cmpdi cr1,r1,0; /* check if SP makes sense */ \
266 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
267 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */
269 /* Exception type-specific macros */
270 #define GEN_SET_KSTACK \
271 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */
272 #define SPRN_GEN_SRR0 SPRN_SRR0
273 #define SPRN_GEN_SRR1 SPRN_SRR1
275 #define GDBELL_SET_KSTACK GEN_SET_KSTACK
276 #define SPRN_GDBELL_SRR0 SPRN_GSRR0
277 #define SPRN_GDBELL_SRR1 SPRN_GSRR1
279 #define CRIT_SET_KSTACK \
280 ld r1,PACA_CRIT_STACK(r13); \
281 subi r1,r1,SPECIAL_EXC_FRAME_SIZE
282 #define SPRN_CRIT_SRR0 SPRN_CSRR0
283 #define SPRN_CRIT_SRR1 SPRN_CSRR1
285 #define DBG_SET_KSTACK \
286 ld r1,PACA_DBG_STACK(r13); \
287 subi r1,r1,SPECIAL_EXC_FRAME_SIZE
288 #define SPRN_DBG_SRR0 SPRN_DSRR0
289 #define SPRN_DBG_SRR1 SPRN_DSRR1
291 #define MC_SET_KSTACK \
292 ld r1,PACA_MC_STACK(r13); \
293 subi r1,r1,SPECIAL_EXC_FRAME_SIZE
294 #define SPRN_MC_SRR0 SPRN_MCSRR0
295 #define SPRN_MC_SRR1 SPRN_MCSRR1
297 #define GEN_BTB_FLUSH \
298 START_BTB_FLUSH_SECTION \
302 END_BTB_FLUSH_SECTION
304 #define CRIT_BTB_FLUSH \
305 START_BTB_FLUSH_SECTION \
307 END_BTB_FLUSH_SECTION
309 #define DBG_BTB_FLUSH CRIT_BTB_FLUSH
310 #define MC_BTB_FLUSH CRIT_BTB_FLUSH
311 #define GDBELL_BTB_FLUSH GEN_BTB_FLUSH
313 #define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \
314 EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n))
316 #define CRIT_EXCEPTION_PROLOG(n, intnum, addition) \
317 EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n))
319 #define DBG_EXCEPTION_PROLOG(n, intnum, addition) \
320 EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n))
322 #define MC_EXCEPTION_PROLOG(n, intnum, addition) \
323 EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n))
325 #define GDBELL_EXCEPTION_PROLOG(n, intnum, addition) \
326 EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n))
328 /* Variants of the "addition" argument for the prolog
330 #define PROLOG_ADDITION_NONE_GEN(n)
331 #define PROLOG_ADDITION_NONE_GDBELL(n)
332 #define PROLOG_ADDITION_NONE_CRIT(n)
333 #define PROLOG_ADDITION_NONE_DBG(n)
334 #define PROLOG_ADDITION_NONE_MC(n)
336 #define PROLOG_ADDITION_MASKABLE_GEN(n) \
337 lbz r10,PACAIRQSOFTMASK(r13); /* are irqs soft-masked? */ \
338 andi. r10,r10,IRQS_DISABLED; /* yes -> go out of line */ \
339 bne masked_interrupt_book3e_##n
342 * Additional regs must be re-loaded from paca before EXCEPTION_COMMON* is
343 * called, because that does SAVE_NVGPRS which must see the original register
344 * values, otherwise the scratch values might be restored when exiting the
347 #define PROLOG_ADDITION_2REGS_GEN(n) \
348 std r14,PACA_EXGEN+EX_R14(r13); \
349 std r15,PACA_EXGEN+EX_R15(r13)
351 #define PROLOG_ADDITION_1REG_GEN(n) \
352 std r14,PACA_EXGEN+EX_R14(r13);
354 #define PROLOG_ADDITION_2REGS_CRIT(n) \
355 std r14,PACA_EXCRIT+EX_R14(r13); \
356 std r15,PACA_EXCRIT+EX_R15(r13)
358 #define PROLOG_ADDITION_2REGS_DBG(n) \
359 std r14,PACA_EXDBG+EX_R14(r13); \
360 std r15,PACA_EXDBG+EX_R15(r13)
362 #define PROLOG_ADDITION_2REGS_MC(n) \
363 std r14,PACA_EXMC+EX_R14(r13); \
364 std r15,PACA_EXMC+EX_R15(r13)
366 /* Core exception code for all exceptions except TLB misses. */
367 #define EXCEPTION_COMMON_LVL(n, scratch, excf) \
369 SAVE_GPR(0, r1); /* save r0 in stackframe */ \
370 SAVE_GPRS(2, 9, r1); /* save r2 - r9 in stackframe */ \
371 std r10,_NIP(r1); /* save SRR0 to stackframe */ \
372 std r11,_MSR(r1); /* save SRR1 to stackframe */ \
373 beq 2f; /* if from kernel mode */ \
374 2: ld r3,excf+EX_R10(r13); /* get back r10 */ \
375 ld r4,excf+EX_R11(r13); /* get back r11 */ \
376 mfspr r5,scratch; /* get back r13 */ \
377 SAVE_GPR(12, r1); /* save r12 in stackframe */ \
378 LOAD_PACA_TOC(); /* get kernel TOC into r2 */ \
379 mflr r6; /* save LR in stackframe */ \
380 mfctr r7; /* save CTR in stackframe */ \
381 mfspr r8,SPRN_XER; /* save XER in stackframe */ \
382 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \
383 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \
384 lbz r11,PACAIRQSOFTMASK(r13); /* get current IRQ softe */ \
385 LOAD_REG_IMMEDIATE(r12, STACK_FRAME_REGS_MARKER); \
387 std r3,GPR10(r1); /* save r10 to stackframe */ \
388 std r4,GPR11(r1); /* save r11 to stackframe */ \
389 std r5,GPR13(r1); /* save it to stackframe */ \
393 li r3,(n); /* regs.trap vector */ \
394 std r9,0(r1); /* store stack frame back link */ \
395 std r10,_CCR(r1); /* store orig CR in stackframe */ \
396 std r9,GPR1(r1); /* store stack frame back link */ \
397 std r11,SOFTE(r1); /* and save it to stackframe */ \
398 std r12,STACK_INT_FRAME_MARKER(r1); /* mark the frame */ \
399 std r3,_TRAP(r1); /* set trap number */ \
400 std r0,RESULT(r1); /* clear regs->result */ \
402 SANITIZE_NVGPRS(); /* minimise speculation influence */
404 #define EXCEPTION_COMMON(n) \
405 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_GEN_SCRATCH, PACA_EXGEN)
406 #define EXCEPTION_COMMON_CRIT(n) \
407 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_CRIT_SCRATCH, PACA_EXCRIT)
408 #define EXCEPTION_COMMON_MC(n) \
409 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_MC_SCRATCH, PACA_EXMC)
410 #define EXCEPTION_COMMON_DBG(n) \
411 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_DBG_SCRATCH, PACA_EXDBG)
413 /* XXX FIXME: Restore r14/r15 when necessary */
414 #define BAD_STACK_TRAMPOLINE(n) \
415 exc_##n##_bad_stack: \
416 li r1,(n); /* get exception number */ \
417 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \
418 b bad_stack_book3e; /* bad stack error */
420 /* WARNING: If you change the layout of this stub, make sure you check
421 * the debug exception handler which handles single stepping
422 * into exceptions from userspace, and the MM code in
423 * arch/powerpc/mm/tlb_nohash.c which patches the branch here
424 * and would need to be updated if that branch is moved
426 #define EXCEPTION_STUB(loc, label) \
427 . = interrupt_base_book3e + loc; \
428 nop; /* To make debug interrupts happy */ \
429 b exc_##label##_book3e;
439 /* Used by asynchronous interrupt that may happen in the idle loop.
441 * This check if the thread was in the idle loop, and if yes, returns
442 * to the caller rather than the PC. This is to avoid a race if
443 * interrupts happen before the wait instruction.
445 #define CHECK_NAPPING() \
446 ld r11, PACA_THREAD_INFO(r13); \
447 ld r10,TI_LOCAL_FLAGS(r11); \
448 andi. r9,r10,_TLF_NAPPING; \
451 rlwinm r7,r10,0,~_TLF_NAPPING; \
453 std r7,TI_LOCAL_FLAGS(r11); \
457 #define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack) \
458 START_EXCEPTION(label); \
459 NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\
460 EXCEPTION_COMMON(trapnum) \
463 addi r3,r1,STACK_INT_FRAME_REGS; \
468 * And here we have the exception vectors !
473 .globl interrupt_base_book3e
474 interrupt_base_book3e: /* fake trap */
475 EXCEPTION_STUB(0x000, machine_check)
476 EXCEPTION_STUB(0x020, critical_input) /* 0x0100 */
477 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */
478 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */
479 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */
480 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */
481 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */
482 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */
483 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */
484 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */
485 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */
486 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */
487 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */
488 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
489 EXCEPTION_STUB(0x1c0, data_tlb_miss)
490 EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
491 EXCEPTION_STUB(0x200, altivec_unavailable)
492 EXCEPTION_STUB(0x220, altivec_assist)
493 EXCEPTION_STUB(0x260, perfmon)
494 EXCEPTION_STUB(0x280, doorbell)
495 EXCEPTION_STUB(0x2a0, doorbell_crit)
496 EXCEPTION_STUB(0x2c0, guest_doorbell)
497 EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
498 EXCEPTION_STUB(0x300, hypercall)
499 EXCEPTION_STUB(0x320, ehpriv)
500 EXCEPTION_STUB(0x340, lrat_error)
502 .globl __end_interrupts
505 /* Critical Input Interrupt */
506 START_EXCEPTION(critical_input);
507 CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL,
508 PROLOG_ADDITION_NONE)
509 EXCEPTION_COMMON_CRIT(0x100)
512 addi r3,r1,STACK_INT_FRAME_REGS
513 bl unknown_nmi_exception
514 b ret_from_crit_except
516 /* Machine Check Interrupt */
517 START_EXCEPTION(machine_check);
518 MC_EXCEPTION_PROLOG(0x000, BOOKE_INTERRUPT_MACHINE_CHECK,
519 PROLOG_ADDITION_NONE)
520 EXCEPTION_COMMON_MC(0x000)
523 addi r3,r1,STACK_INT_FRAME_REGS
524 bl machine_check_exception
527 /* Data Storage Interrupt */
528 START_EXCEPTION(data_storage)
529 NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE,
530 PROLOG_ADDITION_2REGS)
535 ld r14,PACA_EXGEN+EX_R14(r13)
536 ld r15,PACA_EXGEN+EX_R15(r13)
537 EXCEPTION_COMMON(0x300)
538 b storage_fault_common
540 /* Instruction Storage Interrupt */
541 START_EXCEPTION(instruction_storage);
542 NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE,
543 PROLOG_ADDITION_2REGS)
548 ld r14,PACA_EXGEN+EX_R14(r13)
549 ld r15,PACA_EXGEN+EX_R15(r13)
550 EXCEPTION_COMMON(0x400)
551 b storage_fault_common
553 /* External Input Interrupt */
554 MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL,
555 external_input, do_IRQ, ACK_NONE)
558 START_EXCEPTION(alignment);
559 NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT,
560 PROLOG_ADDITION_2REGS)
565 ld r14,PACA_EXGEN+EX_R14(r13)
566 ld r15,PACA_EXGEN+EX_R15(r13)
567 EXCEPTION_COMMON(0x600)
568 b alignment_more /* no room, go out of line */
570 /* Program Interrupt */
571 START_EXCEPTION(program);
572 NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM,
573 PROLOG_ADDITION_1REG)
576 ld r14,PACA_EXGEN+EX_R14(r13)
577 EXCEPTION_COMMON(0x700)
578 addi r3,r1,STACK_INT_FRAME_REGS
579 bl program_check_exception
583 /* Floating Point Unavailable Interrupt */
584 START_EXCEPTION(fp_unavailable);
585 NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL,
586 PROLOG_ADDITION_NONE)
587 /* we can probably do a shorter exception entry for that one... */
588 EXCEPTION_COMMON(0x800)
593 b fast_interrupt_return
594 1: addi r3,r1,STACK_INT_FRAME_REGS
595 bl kernel_fp_unavailable_exception
598 /* Altivec Unavailable Interrupt */
599 START_EXCEPTION(altivec_unavailable);
600 NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL,
601 PROLOG_ADDITION_NONE)
602 /* we can probably do a shorter exception entry for that one... */
603 EXCEPTION_COMMON(0x200)
604 #ifdef CONFIG_ALTIVEC
610 b fast_interrupt_return
612 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
614 addi r3,r1,STACK_INT_FRAME_REGS
615 bl altivec_unavailable_exception
619 START_EXCEPTION(altivec_assist);
620 NORMAL_EXCEPTION_PROLOG(0x220,
621 BOOKE_INTERRUPT_ALTIVEC_ASSIST,
622 PROLOG_ADDITION_NONE)
623 EXCEPTION_COMMON(0x220)
624 addi r3,r1,STACK_INT_FRAME_REGS
625 #ifdef CONFIG_ALTIVEC
627 bl altivec_assist_exception
628 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
636 /* Decrementer Interrupt */
637 MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
638 decrementer, timer_interrupt, ACK_DEC)
640 /* Fixed Interval Timer Interrupt */
641 MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT,
642 fixed_interval, unknown_exception, ACK_FIT)
644 /* Watchdog Timer Interrupt */
645 START_EXCEPTION(watchdog);
646 CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG,
647 PROLOG_ADDITION_NONE)
648 EXCEPTION_COMMON_CRIT(0x9f0)
651 addi r3,r1,STACK_INT_FRAME_REGS
652 #ifdef CONFIG_BOOKE_WDT
655 bl unknown_nmi_exception
657 b ret_from_crit_except
659 /* System Call Interrupt */
660 START_EXCEPTION(system_call)
661 mr r9,r13 /* keep a copy of userland r13 */
662 mfspr r11,SPRN_SRR0 /* get return address */
663 mfspr r12,SPRN_SRR1 /* get previous MSR */
664 mfspr r13,SPRN_SPRG_PACA /* get our PACA */
667 /* Auxiliary Processor Unavailable Interrupt */
668 START_EXCEPTION(ap_unavailable);
669 NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL,
670 PROLOG_ADDITION_NONE)
671 EXCEPTION_COMMON(0xf20)
672 addi r3,r1,STACK_INT_FRAME_REGS
676 /* Debug exception as a critical interrupt*/
677 START_EXCEPTION(debug_crit);
678 CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
679 PROLOG_ADDITION_2REGS)
682 * If there is a single step or branch-taken exception in an
683 * exception entry sequence, it was probably meant to apply to
684 * the code where the exception occurred (since exception entry
685 * doesn't turn off DE automatically). We simulate the effect
686 * of turning off DE on entry to an exception handler by turning
687 * off DE in the CSRR1 value and clearing the debug status.
690 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
691 andis. r15,r14,(DBSR_IC|DBSR_BT)@h
694 #ifdef CONFIG_RELOCATABLE
696 LOAD_REG_ADDR_ALTTOC(r14, r15, interrupt_base_book3e)
697 LOAD_REG_ADDR_ALTTOC(r15, r15, __end_interrupts)
701 LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e)
703 LOAD_REG_IMMEDIATE_SYM(r14, r15, __end_interrupts)
709 /* here it looks like we got an inappropriate debug exception. */
710 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */
711 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */
714 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */
715 ld r1,PACA_EXCRIT+EX_R1(r13)
716 ld r14,PACA_EXCRIT+EX_R14(r13)
717 ld r15,PACA_EXCRIT+EX_R15(r13)
719 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */
720 ld r11,PACA_EXCRIT+EX_R11(r13)
721 mfspr r13,SPRN_SPRG_CRIT_SCRATCH
724 /* Normal debug exception */
725 /* XXX We only handle coming from userspace for now since we can't
726 * quite save properly an interrupted kernel state yet
728 1: andi. r14,r11,MSR_PR; /* check for userspace again */
729 beq kernel_dbg_exc; /* if from kernel mode */
731 /* Now we mash up things to make it look like we are coming on a
736 ld r14,PACA_EXCRIT+EX_R14(r13)
737 ld r15,PACA_EXCRIT+EX_R15(r13)
738 EXCEPTION_COMMON_CRIT(0xd00)
739 addi r3,r1,STACK_INT_FRAME_REGS
747 /* Debug exception as a debug interrupt*/
748 START_EXCEPTION(debug_debug);
749 DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
750 PROLOG_ADDITION_2REGS)
753 * If there is a single step or branch-taken exception in an
754 * exception entry sequence, it was probably meant to apply to
755 * the code where the exception occurred (since exception entry
756 * doesn't turn off DE automatically). We simulate the effect
757 * of turning off DE on entry to an exception handler by turning
758 * off DE in the DSRR1 value and clearing the debug status.
761 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
762 andis. r15,r14,(DBSR_IC|DBSR_BT)@h
765 #ifdef CONFIG_RELOCATABLE
767 LOAD_REG_ADDR_ALTTOC(r14, r15, interrupt_base_book3e)
768 LOAD_REG_ADDR_ALTTOC(r15, r15, __end_interrupts)
772 LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e)
774 LOAD_REG_IMMEDIATE_SYM(r14, r15,__end_interrupts)
780 /* here it looks like we got an inappropriate debug exception. */
781 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */
782 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */
785 lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */
786 ld r1,PACA_EXDBG+EX_R1(r13)
787 ld r14,PACA_EXDBG+EX_R14(r13)
788 ld r15,PACA_EXDBG+EX_R15(r13)
790 ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */
791 ld r11,PACA_EXDBG+EX_R11(r13)
792 mfspr r13,SPRN_SPRG_DBG_SCRATCH
795 /* Normal debug exception */
796 /* XXX We only handle coming from userspace for now since we can't
797 * quite save properly an interrupted kernel state yet
799 1: andi. r14,r11,MSR_PR; /* check for userspace again */
800 beq kernel_dbg_exc; /* if from kernel mode */
802 /* Now we mash up things to make it look like we are coming on a
807 ld r14,PACA_EXDBG+EX_R14(r13)
808 ld r15,PACA_EXDBG+EX_R15(r13)
809 EXCEPTION_COMMON_DBG(0xd08)
810 addi r3,r1,STACK_INT_FRAME_REGS
815 START_EXCEPTION(perfmon);
816 NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR,
817 PROLOG_ADDITION_NONE)
818 EXCEPTION_COMMON(0x260)
820 addi r3,r1,STACK_INT_FRAME_REGS
822 * XXX: Returning from performance_monitor_exception taken as a
823 * soft-NMI (Linux irqs disabled) may be risky to use interrupt_return
824 * and could cause bugs in return or elsewhere. That case should just
825 * restore registers and return. There is a workaround for one known
826 * problem in interrupt_exit_kernel_prepare().
828 bl performance_monitor_exception
831 /* Doorbell interrupt */
832 MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL,
833 doorbell, doorbell_exception, ACK_NONE)
835 /* Doorbell critical Interrupt */
836 START_EXCEPTION(doorbell_crit);
837 CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL,
838 PROLOG_ADDITION_NONE)
839 EXCEPTION_COMMON_CRIT(0x2a0)
842 addi r3,r1,STACK_INT_FRAME_REGS
843 bl unknown_nmi_exception
844 b ret_from_crit_except
847 * Guest doorbell interrupt
848 * This general exception use GSRRx save/restore registers
850 START_EXCEPTION(guest_doorbell);
851 GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL,
852 PROLOG_ADDITION_NONE)
853 EXCEPTION_COMMON(0x2c0)
854 addi r3,r1,STACK_INT_FRAME_REGS
858 /* Guest Doorbell critical Interrupt */
859 START_EXCEPTION(guest_doorbell_crit);
860 CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
861 PROLOG_ADDITION_NONE)
862 EXCEPTION_COMMON_CRIT(0x2e0)
865 addi r3,r1,STACK_INT_FRAME_REGS
866 bl unknown_nmi_exception
867 b ret_from_crit_except
869 /* Hypervisor call */
870 START_EXCEPTION(hypercall);
871 NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL,
872 PROLOG_ADDITION_NONE)
873 EXCEPTION_COMMON(0x310)
874 addi r3,r1,STACK_INT_FRAME_REGS
878 /* Embedded Hypervisor priviledged */
879 START_EXCEPTION(ehpriv);
880 NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV,
881 PROLOG_ADDITION_NONE)
882 EXCEPTION_COMMON(0x320)
883 addi r3,r1,STACK_INT_FRAME_REGS
887 /* LRAT Error interrupt */
888 START_EXCEPTION(lrat_error);
889 NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR,
890 PROLOG_ADDITION_NONE)
891 EXCEPTION_COMMON(0x340)
892 addi r3,r1,STACK_INT_FRAME_REGS
896 .macro SEARCH_RESTART_TABLE
897 #ifdef CONFIG_RELOCATABLE
899 LOAD_REG_ADDR_ALTTOC(r14, r11, __start___restart_table)
900 LOAD_REG_ADDR_ALTTOC(r15, r11, __stop___restart_table)
902 LOAD_REG_IMMEDIATE_SYM(r14, r11, __start___restart_table)
903 LOAD_REG_IMMEDIATE_SYM(r15, r11, __stop___restart_table)
925 * An interrupt came in while soft-disabled; We mark paca->irq_happened
926 * accordingly and if the interrupt is level sensitive, we hard disable
927 * hard disable (full_mask) corresponds to PACA_IRQ_MUST_HARD_MASK, so
928 * keep these in synch.
931 .macro masked_interrupt_book3e paca_irq full_mask
932 std r14,PACA_EXGEN+EX_R14(r13)
933 std r15,PACA_EXGEN+EX_R15(r13)
935 lbz r10,PACAIRQHAPPENED(r13)
937 ori r10,r10,\paca_irq | PACA_IRQ_HARD_DIS
939 ori r10,r10,\paca_irq
941 stb r10,PACAIRQHAPPENED(r13)
944 xori r11,r11,MSR_EE /* clear MSR_EE */
952 mtspr SPRN_SRR0,r11 /* return to restart address */
955 lwz r11,PACA_EXGEN+EX_CR(r13)
957 ld r10,PACA_EXGEN+EX_R10(r13)
958 ld r11,PACA_EXGEN+EX_R11(r13)
959 ld r14,PACA_EXGEN+EX_R14(r13)
960 ld r15,PACA_EXGEN+EX_R15(r13)
961 mfspr r13,SPRN_SPRG_GEN_SCRATCH
966 masked_interrupt_book3e_0x500:
967 masked_interrupt_book3e PACA_IRQ_EE 1
969 masked_interrupt_book3e_0x900:
971 masked_interrupt_book3e PACA_IRQ_DEC 0
973 masked_interrupt_book3e_0x980:
975 masked_interrupt_book3e PACA_IRQ_DEC 0
977 masked_interrupt_book3e_0x280:
978 masked_interrupt_book3e_0x2c0:
979 masked_interrupt_book3e PACA_IRQ_DBELL 0
982 * This is called from 0x300 and 0x400 handlers after the prologs with
983 * r14 and r15 containing the fault address and error code, with the
984 * original values stashed away in the PACA
986 SYM_CODE_START_LOCAL(storage_fault_common)
987 addi r3,r1,STACK_INT_FRAME_REGS
990 SYM_CODE_END(storage_fault_common)
993 * Alignment exception doesn't fit entirely in the 0x100 bytes so it
996 SYM_CODE_START_LOCAL(alignment_more)
997 addi r3,r1,STACK_INT_FRAME_REGS
998 bl alignment_exception
1001 SYM_CODE_END(alignment_more)
1004 * Trampolines used when spotting a bad kernel stack pointer in
1005 * the exception entry code.
1007 * TODO: move some bits like SRR0 read to trampoline, pass PACA
1008 * index around, etc... to handle crit & mcheck
1010 BAD_STACK_TRAMPOLINE(0x000)
1011 BAD_STACK_TRAMPOLINE(0x100)
1012 BAD_STACK_TRAMPOLINE(0x200)
1013 BAD_STACK_TRAMPOLINE(0x220)
1014 BAD_STACK_TRAMPOLINE(0x260)
1015 BAD_STACK_TRAMPOLINE(0x280)
1016 BAD_STACK_TRAMPOLINE(0x2a0)
1017 BAD_STACK_TRAMPOLINE(0x2c0)
1018 BAD_STACK_TRAMPOLINE(0x2e0)
1019 BAD_STACK_TRAMPOLINE(0x300)
1020 BAD_STACK_TRAMPOLINE(0x310)
1021 BAD_STACK_TRAMPOLINE(0x320)
1022 BAD_STACK_TRAMPOLINE(0x340)
1023 BAD_STACK_TRAMPOLINE(0x400)
1024 BAD_STACK_TRAMPOLINE(0x500)
1025 BAD_STACK_TRAMPOLINE(0x600)
1026 BAD_STACK_TRAMPOLINE(0x700)
1027 BAD_STACK_TRAMPOLINE(0x800)
1028 BAD_STACK_TRAMPOLINE(0x900)
1029 BAD_STACK_TRAMPOLINE(0x980)
1030 BAD_STACK_TRAMPOLINE(0x9f0)
1031 BAD_STACK_TRAMPOLINE(0xa00)
1032 BAD_STACK_TRAMPOLINE(0xb00)
1033 BAD_STACK_TRAMPOLINE(0xc00)
1034 BAD_STACK_TRAMPOLINE(0xd00)
1035 BAD_STACK_TRAMPOLINE(0xd08)
1036 BAD_STACK_TRAMPOLINE(0xe00)
1037 BAD_STACK_TRAMPOLINE(0xf00)
1038 BAD_STACK_TRAMPOLINE(0xf20)
1040 _GLOBAL(bad_stack_book3e)
1041 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
1042 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */
1043 ld r1,PACAEMERGSP(r13)
1044 subi r1,r1,64+INT_FRAME_SIZE
1047 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
1048 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
1055 SAVE_GPR(0, r1); /* save r0 in stackframe */ \
1056 SAVE_GPRS(2, 9, r1); /* save r2 - r9 in stackframe */ \
1057 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \
1058 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \
1059 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
1060 std r3,GPR10(r1); /* save r10 to stackframe */ \
1061 std r4,GPR11(r1); /* save r11 to stackframe */ \
1062 SAVE_GPR(12, r1); /* save r12 in stackframe */ \
1063 std r5,GPR13(r1); /* save it to stackframe */ \
1071 lhz r12,PACA_TRAP_SAVE(r13)
1073 addi r11,r1,INT_FRAME_SIZE
1078 1: addi r3,r1,STACK_INT_FRAME_REGS
1083 * Setup the initial TLB for a core. This current implementation
1084 * assume that whatever we are running off will not conflict with
1085 * the new mapping at PAGE_OFFSET.
1087 _GLOBAL(initial_tlb_book3e)
1089 /* Look for the first TLB with IPROT set */
1090 mfspr r4,SPRN_TLB0CFG
1091 andi. r3,r4,TLBnCFG_IPROT
1092 lis r3,MAS0_TLBSEL(0)@h
1095 mfspr r4,SPRN_TLB1CFG
1096 andi. r3,r4,TLBnCFG_IPROT
1097 lis r3,MAS0_TLBSEL(1)@h
1100 mfspr r4,SPRN_TLB2CFG
1101 andi. r3,r4,TLBnCFG_IPROT
1102 lis r3,MAS0_TLBSEL(2)@h
1105 lis r3,MAS0_TLBSEL(3)@h
1106 mfspr r4,SPRN_TLB3CFG
1110 andi. r5,r4,TLBnCFG_HES
1113 mflr r8 /* save LR */
1114 /* 1. Find the index of the entry we're executing in
1116 * r3 = MAS0_TLBSEL (for the iprot array)
1119 bcl 20,31,$+4 /* Find our address */
1120 invstr: mflr r6 /* Make it accessible */
1122 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */
1127 tlbsx 0,r6 /* search MSR[IS], SPID=PID */
1130 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */
1132 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
1133 oris r7,r7,MAS1_IPROT@h
1137 /* 2. Invalidate all entries except the entry we're executing in
1139 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1141 * r5 = ESEL of entry we are running in
1143 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */
1144 li r6,0 /* Set Entry counter to 0 */
1145 1: mr r7,r3 /* Set MAS0(TLBSEL) */
1146 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
1150 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
1152 beq skpinv /* Dont update the current execution TLB */
1156 skpinv: addi r6,r6,1 /* Increment */
1157 cmpw r6,r4 /* Are we done? */
1158 bne 1b /* If not, repeat */
1160 /* Invalidate all TLBs */
1161 PPC_TLBILX_ALL(0,R0)
1165 /* 3. Setup a temp mapping and jump to it
1167 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1168 * r5 = ESEL of entry we are running in
1170 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */
1172 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */
1176 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */
1180 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */
1188 bcl 20,31,$+4 /* Find our address */
1190 addi r6,r6,(2f - 1b)
1195 /* 4. Clear out PIDs & Search info
1197 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1198 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1205 /* 5. Invalidate mapping we started in
1207 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1208 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1214 rlwinm r6,r6,0,2,31 /* clear IPROT and VALID */
1220 /* 6. Setup KERNELBASE mapping in TLB[0]
1222 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1223 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1226 rlwinm r3,r3,0,16,3 /* clear ESEL */
1228 lis r6,(MAS1_VALID|MAS1_IPROT)@h
1229 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
1232 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | MAS2_M_IF_NEEDED)
1236 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
1243 /* 7. Jump to KERNELBASE mapping
1245 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1247 /* Now we branch the new virtual address mapped by this entry */
1248 bcl 20,31,$+4 /* Find our address */
1250 addi r6,r6,(2f - 1b)
1253 ori r7,r7,MSR_KERNEL@l
1256 rfi /* start execution out of TLB1[0] entry */
1259 /* 8. Clear out the temp mapping
1261 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1266 rlwinm r5,r5,0,2,31 /* clear IPROT and VALID */
1272 /* We translate LR and return */
1278 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
1279 * kernel linear mapping. We also set MAS8 once for all here though
1280 * that will have to be made dependent on whether we are running under
1281 * a hypervisor I suppose.
1285 * This code is called as an ordinary function on the boot CPU. But to
1286 * avoid duplication, this code is also used in SCOM bringup of
1287 * secondary CPUs. We read the code between the initial_tlb_code_start
1288 * and initial_tlb_code_end labels one instruction at a time and RAM it
1289 * into the new core via SCOM. That doesn't process branches, so there
1290 * must be none between those two labels. It also means if this code
1291 * ever takes any parameters, the SCOM code must also be updated to
1294 _GLOBAL(a2_tlbinit_code_start)
1296 ori r11,r3,MAS0_WQ_ALLWAYS
1297 oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
1299 lis r3,(MAS1_VALID | MAS1_IPROT)@h
1300 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
1302 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
1304 li r3,MAS3_SR | MAS3_SW | MAS3_SX
1305 mtspr SPRN_MAS7_MAS3,r3
1309 /* Write the TLB entry */
1312 .globl a2_tlbinit_after_linear_map
1313 a2_tlbinit_after_linear_map:
1315 /* Now we branch the new virtual address mapped by this entry */
1316 #ifdef CONFIG_RELOCATABLE
1318 LOAD_REG_ADDR_ALTTOC(r3, r5, 1f)
1320 LOAD_REG_IMMEDIATE_SYM(r3, r5, 1f)
1325 1: /* We are now running at PAGE_OFFSET, clean the TLB of everything
1326 * else (including IPROTed things left by firmware)
1328 * r3 = current address (more or less)
1335 rlwinm r9,r4,0,TLBnCFG_N_ENTRY
1336 rlwinm r10,r4,8,0xff
1337 addi r10,r10,-1 /* Get inner loop mask */
1342 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
1345 rldicr r6,r6,0,51 /* Extract EPN */
1348 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */
1350 rlwinm r8,r7,16,0xfff /* Extract ESEL */
1355 rlwimi r7,r4,16,MAS0_ESEL_MASK
1366 addis r6,r6,(1<<30)@h
1371 .globl a2_tlbinit_after_iprot_flush
1372 a2_tlbinit_after_iprot_flush:
1378 .globl a2_tlbinit_code_end
1379 a2_tlbinit_code_end:
1381 /* We translate LR and return */
1388 * Main entry (boot CPU, thread 0)
1390 * We enter here from head_64.S, possibly after the prom_init trampoline
1391 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
1392 * mode. Anything else is as it was left by the bootloader
1394 * Initial requirements of this port:
1396 * - Kernel loaded at 0 physical
1397 * - A good lump of memory mapped 0:0 by UTLB entry 0
1398 * - MSR:IS & MSR:DS set to 0
1400 * Note that some of the above requirements will be relaxed in the future
1401 * as the kernel becomes smarter at dealing with different initial conditions
1402 * but for now you have to be careful
1404 _GLOBAL(start_initialization_book3e)
1407 /* First, we need to setup some initial TLBs to map the kernel
1408 * text, data and bss at PAGE_OFFSET. We don't have a real mode
1409 * and always use AS 0, so we just set it up to match our link
1410 * address and never use 0 based addresses.
1412 bl initial_tlb_book3e
1414 /* Init global core bits */
1417 /* Init per-thread bits */
1418 bl init_thread_book3e
1420 /* Return to common init code */
1427 * Secondary core/processor entry
1429 * This is entered for thread 0 of a secondary core, all other threads
1430 * are expected to be stopped. It's similar to start_initialization_book3e
1431 * except that it's generally entered from the holding loop in head_64.S
1432 * after CPUs have been gathered by Open Firmware.
1434 * We assume we are in 32 bits mode running with whatever TLB entry was
1435 * set for us by the firmware or POR engine.
1437 _GLOBAL(book3e_secondary_core_init_tlb_set)
1439 b generic_secondary_smp_init
1441 _GLOBAL(book3e_secondary_core_init)
1444 /* Do we need to setup initial TLB entry ? */
1448 /* Setup TLB for this core */
1449 bl initial_tlb_book3e
1451 /* We can return from the above running at a different
1452 * address, so recalculate r2 (TOC)
1456 /* Init global core bits */
1457 2: bl init_core_book3e
1459 /* Init per-thread bits */
1460 3: bl init_thread_book3e
1462 /* Return to common init code at proper virtual address.
1464 * Due to various previous assumptions, we know we entered this
1465 * function at either the final PAGE_OFFSET mapping or using a
1466 * 1:1 mapping at 0, so we don't bother doing a complicated check
1467 * here, we just ensure the return address has the right top bits.
1469 * Note that if we ever want to be smarter about where we can be
1470 * started from, we have to be careful that by the time we reach
1471 * the code below we may already be running at a different location
1472 * than the one we were called from since initial_tlb_book3e can
1473 * have moved us already.
1477 lis r3,PAGE_OFFSET@highest
1483 _GLOBAL(book3e_secondary_thread_init)
1487 _GLOBAL(init_core_book3e)
1488 /* Establish the interrupt vector base */
1490 LOAD_REG_ADDR(r3, interrupt_base_book3e)
1495 SYM_CODE_START_LOCAL(init_thread_book3e)
1496 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
1499 /* Make sure interrupts are off */
1502 /* disable all timers and clear out status */
1509 SYM_CODE_END(init_thread_book3e)
1511 _GLOBAL(__setup_base_ivors)
1512 SET_IVOR(0, 0x020) /* Critical Input */
1513 SET_IVOR(1, 0x000) /* Machine Check */
1514 SET_IVOR(2, 0x060) /* Data Storage */
1515 SET_IVOR(3, 0x080) /* Instruction Storage */
1516 SET_IVOR(4, 0x0a0) /* External Input */
1517 SET_IVOR(5, 0x0c0) /* Alignment */
1518 SET_IVOR(6, 0x0e0) /* Program */
1519 SET_IVOR(7, 0x100) /* FP Unavailable */
1520 SET_IVOR(8, 0x120) /* System Call */
1521 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
1522 SET_IVOR(10, 0x160) /* Decrementer */
1523 SET_IVOR(11, 0x180) /* Fixed Interval Timer */
1524 SET_IVOR(12, 0x1a0) /* Watchdog Timer */
1525 SET_IVOR(13, 0x1c0) /* Data TLB Error */
1526 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
1527 SET_IVOR(15, 0x040) /* Debug */
1533 _GLOBAL(setup_altivec_ivors)
1534 SET_IVOR(32, 0x200) /* AltiVec Unavailable */
1535 SET_IVOR(33, 0x220) /* AltiVec Assist */
1538 _GLOBAL(setup_perfmon_ivor)
1539 SET_IVOR(35, 0x260) /* Performance Monitor */
1542 _GLOBAL(setup_doorbell_ivors)
1543 SET_IVOR(36, 0x280) /* Processor Doorbell */
1544 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
1547 _GLOBAL(setup_ehv_ivors)
1548 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
1549 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
1550 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1551 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
1554 _GLOBAL(setup_lrat_ivor)
1555 SET_IVOR(42, 0x340) /* LRAT Error */