3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <asm/unistd.h>
24 #include <asm/processor.h>
27 #include <asm/thread_info.h>
28 #include <asm/code-patching-asm.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/asm-offsets.h>
31 #include <asm/cputable.h>
32 #include <asm/firmware.h>
34 #include <asm/ptrace.h>
35 #include <asm/irqflags.h>
36 #include <asm/hw_irq.h>
37 #include <asm/context_tracking.h>
39 #include <asm/ppc-opcode.h>
40 #include <asm/barrier.h>
41 #include <asm/export.h>
42 #ifdef CONFIG_PPC_BOOK3S
43 #include <asm/exception-64s.h>
45 #include <asm/exception-64e.h>
53 .tc sys_call_table[TC],sys_call_table
55 /* This value is used to mark exception frames on the stack. */
57 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
62 .globl system_call_common
64 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
66 extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */
68 END_FTR_SECTION_IFSET(CPU_FTR_TM)
72 addi r1,r1,-INT_FRAME_SIZE
80 beq 2f /* if from kernel mode */
81 #ifdef CONFIG_PPC_FSL_BOOK3E
82 START_BTB_FLUSH_SECTION
86 ACCOUNT_CPU_USER_ENTRY(r13, r10, r11)
105 * This clears CR0.SO (bit 28), which is the error indication on
106 * return from this system call.
108 rldimi r2,r11,28,(63-28)
115 addi r9,r1,STACK_FRAME_OVERHEAD
116 ld r11,exception_marker@toc(r2)
117 std r11,-16(r9) /* "regshere" marker */
118 #if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR)
121 /* if from user, see if there are any DTL entries to process */
122 ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
123 ld r11,PACA_DTL_RIDX(r13) /* get log read index */
124 addi r10,r10,LPPACA_DTLIDX
125 LDX_BE r10,0,r10 /* get log write index */
128 bl accumulate_stolen_time
132 addi r9,r1,STACK_FRAME_OVERHEAD
134 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
135 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
138 * A syscall should always be called with interrupts enabled
139 * so we just unconditionally hard-enable here. When some kind
140 * of irq tracing is used, we additionally check that condition
143 #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
144 lbz r10,PACASOFTIRQEN(r13)
147 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
150 #ifdef CONFIG_PPC_BOOK3E
156 #endif /* CONFIG_PPC_BOOK3E */
158 system_call: /* label this so stack traces look sane */
159 /* We do need to set SOFTE in the stack frame or the return
160 * from interrupt will be painful
165 CURRENT_THREAD_INFO(r11, r1)
167 andi. r11,r10,_TIF_SYSCALL_DOTRACE
168 bne .Lsyscall_dotrace /* does not return */
169 cmpldi 0,r0,NR_syscalls
170 bge- .Lsyscall_enosys
174 * Need to vector to 32 Bit or default sys_call_table here,
175 * based on caller's run-mode / personality.
177 ld r11,SYS_CALL_TABLE@toc(2)
178 andi. r10,r10,_TIF_32BIT
180 addi r11,r11,8 /* use 32-bit syscall entries */
192 * Prevent the load of the handler below (based on the user-passed
193 * system call number) being speculatively executed until the test
194 * against NR_syscalls and branch to .Lsyscall_enosys above has
198 ldx r12,r11,r0 /* Fetch system call handler [ptr] */
200 bctrl /* Call handler */
204 CURRENT_THREAD_INFO(r12, r1)
207 #ifdef CONFIG_PPC_BOOK3S
208 /* No MSR:RI on BookE */
210 beq- .Lunrecov_restore
214 * This is a few instructions into the actual syscall exit path (which actually
215 * starts at .Lsyscall_exit) to cater to kprobe blacklisting and to reduce the
216 * number of visible symbols for profiling purposes.
218 * We can probe from system_call until this point as MSR_RI is set. But once it
219 * is cleared below, we won't be able to take a trap.
221 * This is blacklisted from kprobes further below with _ASM_NOKPROBE_SYMBOL().
225 * Disable interrupts so current_thread_info()->flags can't change,
226 * and so that we don't get interrupted after loading SRR0/1.
228 #ifdef CONFIG_PPC_BOOK3E
232 * For performance reasons we clear RI the same time that we
233 * clear EE. We only need to clear RI just before we restore r13
234 * below, but batching it with EE saves us one expensive mtmsrd call.
235 * We have to be careful to restore RI if we branch anywhere from
236 * here (eg syscall_exit_work).
240 #endif /* CONFIG_PPC_BOOK3E */
244 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
245 bne- .Lsyscall_exit_work
249 #ifdef CONFIG_ALTIVEC
250 andis. r0,r8,MSR_VEC@h
253 2: addi r3,r1,STACK_FRAME_OVERHEAD
254 #ifdef CONFIG_PPC_BOOK3S
256 mtmsrd r10,1 /* Restore RI */
259 #ifdef CONFIG_PPC_BOOK3S
270 .Lsyscall_error_cont:
273 stdcx. r0,0,r1 /* to clear the reservation */
274 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
279 ACCOUNT_CPU_USER_EXIT(r13, r11, r12)
283 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
285 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
293 b . /* prevent speculative execution */
303 b . /* prevent speculative execution */
306 oris r5,r5,0x1000 /* Set SO bit in CR */
309 b .Lsyscall_error_cont
311 /* Traced system call support */
314 addi r3,r1,STACK_FRAME_OVERHEAD
315 bl do_syscall_trace_enter
318 * We use the return value of do_syscall_trace_enter() as the syscall
319 * number. If the syscall was rejected for any reason do_syscall_trace_enter()
320 * returns an invalid syscall number and the test below against
321 * NR_syscalls will fail.
325 /* Restore argument registers just clobbered and/or possibly changed. */
333 /* Repopulate r9 and r10 for the syscall path */
334 addi r9,r1,STACK_FRAME_OVERHEAD
335 CURRENT_THREAD_INFO(r10, r1)
338 cmpldi r0,NR_syscalls
341 /* Return code is already in r3 thanks to do_syscall_trace_enter() */
350 #ifdef CONFIG_PPC_BOOK3S
352 mtmsrd r10,1 /* Restore RI */
354 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
355 If TIF_NOERROR is set, just save r3 as it is. */
357 andi. r0,r9,_TIF_RESTOREALL
361 0: cmpld r3,r11 /* r11 is -MAX_ERRNO */
363 andi. r0,r9,_TIF_NOERROR
367 oris r5,r5,0x1000 /* Set SO bit in CR */
370 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
373 /* Clear per-syscall TIF flags if any are set. */
375 li r11,_TIF_PERSYSCALL_MASK
376 addi r12,r12,TI_FLAGS
381 subi r12,r12,TI_FLAGS
383 4: /* Anything else left to do? */
385 lis r3,INIT_PPR@highest /* Set thread.ppr = 3 */
386 ld r10,PACACURRENT(r13)
387 sldi r3,r3,32 /* bits 11-13 are used for ppr */
388 std r3,TASKTHREADPPR(r10)
389 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
391 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
392 beq ret_from_except_lite
394 /* Re-enable interrupts */
395 #ifdef CONFIG_PPC_BOOK3E
401 #endif /* CONFIG_PPC_BOOK3E */
404 addi r3,r1,STACK_FRAME_OVERHEAD
405 bl do_syscall_trace_leave
408 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
410 /* Firstly we need to enable TM in the kernel */
413 rldimi r10, r9, MSR_TM_LG, 63-MSR_TM_LG
416 /* tabort, this dooms the transaction, nothing else */
417 li r9, (TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT)
421 * Return directly to userspace. We have corrupted user register state,
422 * but userspace will never see that register state. Execution will
423 * resume after the tbegin of the aborted transaction with the
424 * checkpointed register state.
432 b . /* prevent speculative execution */
434 _ASM_NOKPROBE_SYMBOL(system_call_common);
435 _ASM_NOKPROBE_SYMBOL(system_call_exit);
437 /* Save non-volatile GPRs, if not already saved. */
446 _ASM_NOKPROBE_SYMBOL(save_nvgprs);
450 * The sigsuspend and rt_sigsuspend system calls can call do_signal
451 * and thus put the process into the stopped state where we might
452 * want to examine its user state with ptrace. Therefore we need
453 * to save all the nonvolatile registers (r14 - r31) before calling
454 * the C code. Similarly, fork, vfork and clone need the full
455 * register state on the stack so that it can be copied to the child.
473 _GLOBAL(ppc32_swapcontext)
475 bl compat_sys_swapcontext
478 _GLOBAL(ppc64_swapcontext)
483 _GLOBAL(ppc_switch_endian)
488 _GLOBAL(ret_from_fork)
494 _GLOBAL(ret_from_kernel_thread)
499 #ifdef PPC64_ELF_ABI_v2
506 #ifdef CONFIG_PPC_BOOK3S_64
508 #define FLUSH_COUNT_CACHE \
510 patch_site 1b, patch__call_flush_count_cache
513 #define BCCTR_FLUSH .long 0x4c400420
522 .global flush_count_cache
524 /* Save LR into r9 */
527 // Flush the link stack
538 // If we're just flushing the link stack, return here
540 patch_site 3b patch__flush_link_stack_return
548 patch_site 2b patch__flush_count_cache_return
560 #define FLUSH_COUNT_CACHE
561 #endif /* CONFIG_PPC_BOOK3S_64 */
564 * This routine switches between two different tasks. The process
565 * state of one is saved on its kernel stack. Then the state
566 * of the other is restored from its kernel stack. The memory
567 * management hardware is updated to the second process's state.
568 * Finally, we can return to the second process, via ret_from_except.
569 * On entry, r3 points to the THREAD for the current task, r4
570 * points to the THREAD for the new task.
572 * Note: there are two ways to get to the "going out" portion
573 * of this code; either by coming in via the entry (_switch)
574 * or via "fork" which must set up an environment equivalent
575 * to the "_switch" path. If you change this you'll have to change
576 * the fork code also.
578 * The code which creates the new task context is in 'copy_thread'
579 * in arch/powerpc/kernel/process.c
585 stdu r1,-SWITCH_FRAME_SIZE(r1)
586 /* r3-r13 are caller saved -- Cort */
589 std r0,_NIP(r1) /* Return to switch caller */
592 std r1,KSP(r3) /* Set old stack pointer */
597 * On SMP kernels, care must be taken because a task may be
598 * scheduled off CPUx and on to CPUy. Memory ordering must be
601 * Cacheable stores on CPUx will be visible when the task is
602 * scheduled on CPUy by virtue of the core scheduler barriers
603 * (see "Notes on Program-Order guarantees on SMP systems." in
604 * kernel/sched/core.c).
606 * Uncacheable stores in the case of involuntary preemption must
607 * be taken care of. The smp_mb__before_spin_lock() in __schedule()
608 * is implemented as hwsync on powerpc, which orders MMIO too. So
609 * long as there is an hwsync in the context switch path, it will
610 * be executed on the source CPU after the task has performed
611 * all MMIO ops on that CPU, and on the destination CPU before the
612 * task performs any MMIO ops there.
616 * The kernel context switch path must contain a spin_lock,
617 * which contains larx/stcx, which will clear any reservation
618 * of the task being switched.
620 #ifdef CONFIG_PPC_BOOK3S
621 /* Cancel all explict user streams as they will have no use after context
622 * switch and will stop the HW from creating streams itself
624 DCBT_STOP_ALL_STREAM_IDS(r6)
627 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
628 std r6,PACACURRENT(r13) /* Set new 'current' */
630 ld r8,KSP(r4) /* new stack pointer */
631 #ifdef CONFIG_PPC_STD_MMU_64
632 BEGIN_MMU_FTR_SECTION
634 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
636 clrrdi r6,r8,28 /* get its ESID */
637 clrrdi r9,r1,28 /* get current sp ESID */
639 clrrdi r6,r8,40 /* get its 1T ESID */
640 clrrdi r9,r1,40 /* get current sp 1T ESID */
641 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_1T_SEGMENT)
642 clrldi. r0,r6,2 /* is new ESID c00000000? */
643 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
645 beq 2f /* if yes, don't slbie it */
647 /* Bolt in the new stack SLB entry */
648 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
649 oris r0,r6,(SLB_ESID_V)@h
650 ori r0,r0,(SLB_NUM_BOLTED-1)@l
652 li r9,MMU_SEGSIZE_1T /* insert B field */
653 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
654 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
655 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
657 /* Update the last bolted SLB. No write barriers are needed
658 * here, provided we only update the current CPU's SLB shadow
661 ld r9,PACA_SLBSHADOWPTR(r13)
663 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
664 li r12,SLBSHADOW_STACKVSID
665 STDX_BE r7,r12,r9 /* Save VSID */
666 li r12,SLBSHADOW_STACKESID
667 STDX_BE r0,r12,r9 /* Save ESID */
669 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
670 * we have 1TB segments, the only CPUs known to have the errata
671 * only support less than 1TB of system memory and we'll never
672 * actually hit this code path.
677 slbie r6 /* Workaround POWER5 < DD2.1 issue */
681 #endif /* CONFIG_PPC_STD_MMU_64 */
683 CURRENT_THREAD_INFO(r7, r8) /* base of new stack */
684 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
685 because we don't need to leave the 288-byte ABI gap at the
686 top of the kernel stack. */
687 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
690 * PMU interrupts in radix may come in here. They will use r1, not
691 * PACAKSAVE, so this stack switch will not cause a problem. They
692 * will store to the process stack, which may then be migrated to
693 * another CPU. However the rq lock release on this CPU paired with
694 * the rq lock acquire on the new CPU before the stack becomes
695 * active on the new CPU, will order those stores.
697 mr r1,r8 /* start using new stack pointer */
698 std r7,PACAKSAVE(r13)
703 /* r3-r13 are destroyed -- Cort */
707 /* convert old thread to its task_struct for return value */
709 ld r7,_NIP(r1) /* Return to _switch caller in new task */
711 addi r1,r1,SWITCH_FRAME_SIZE
715 _GLOBAL(ret_from_except)
718 bne ret_from_except_lite
721 _GLOBAL(ret_from_except_lite)
723 * Disable interrupts so that current_thread_info()->flags
724 * can't change between when we test it and when we return
725 * from the interrupt.
727 #ifdef CONFIG_PPC_BOOK3E
731 mtmsrd r10,1 /* Update machine state */
732 #endif /* CONFIG_PPC_BOOK3E */
734 CURRENT_THREAD_INFO(r9, r1)
736 #ifdef CONFIG_PPC_BOOK3E
737 ld r10,PACACURRENT(r13)
738 #endif /* CONFIG_PPC_BOOK3E */
742 #ifdef CONFIG_PPC_BOOK3E
743 lwz r3,(THREAD+THREAD_DBCR0)(r10)
744 #endif /* CONFIG_PPC_BOOK3E */
746 /* Check current_thread_info()->flags */
747 andi. r0,r4,_TIF_USER_WORK_MASK
749 #ifdef CONFIG_PPC_BOOK3E
751 * Check to see if the dbcr0 register is set up to debug.
752 * Use the internal debug mode bit to do this.
754 andis. r0,r3,DBCR0_IDM@h
757 rlwinm r0,r0,0,~MSR_DE /* Clear MSR.DE */
764 addi r3,r1,STACK_FRAME_OVERHEAD
768 1: andi. r0,r4,_TIF_NEED_RESCHED
770 bl restore_interrupts
772 b ret_from_except_lite
774 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
775 andi. r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM
776 bne 3f /* only restore TM if nothing else to do */
777 addi r3,r1,STACK_FRAME_OVERHEAD
784 * Use a non volatile GPR to save and restore our thread_info flags
785 * across the call to restore_interrupts.
788 bl restore_interrupts
790 addi r3,r1,STACK_FRAME_OVERHEAD
795 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
796 andis. r8,r4,_TIF_EMULATE_STACK_STORE@h
799 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
802 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
803 mr r4,r1 /* src: current exception frame */
804 mr r1,r3 /* Reroute the trampoline frame to r1 */
806 /* Copy from the original to the trampoline. */
807 li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */
808 li r6,0 /* start offset: 0 */
815 /* Do real store operation to complete stdu */
819 /* Clear _TIF_EMULATE_STACK_STORE flag */
820 lis r11,_TIF_EMULATE_STACK_STORE@h
828 #ifdef CONFIG_PREEMPT
829 /* Check if we need to preempt */
830 andi. r0,r4,_TIF_NEED_RESCHED
832 /* Check that preempt_count() == 0 and interrupts are enabled */
833 lwz r8,TI_PREEMPT(r9)
837 crandc eq,cr1*4+eq,eq
841 * Here we are preempting the current task. We want to make
842 * sure we are soft-disabled first and reconcile irq state.
844 RECONCILE_IRQ_STATE(r3,r4)
845 1: bl preempt_schedule_irq
847 /* Re-test flags and eventually loop */
848 CURRENT_THREAD_INFO(r9, r1)
850 andi. r0,r4,_TIF_NEED_RESCHED
854 * arch_local_irq_restore() from preempt_schedule_irq above may
855 * enable hard interrupt but we really should disable interrupts
856 * when we return from the interrupt, and so that we don't get
857 * interrupted after loading SRR0/1.
859 #ifdef CONFIG_PPC_BOOK3E
863 mtmsrd r10,1 /* Update machine state */
864 #endif /* CONFIG_PPC_BOOK3E */
865 #endif /* CONFIG_PREEMPT */
867 .globl fast_exc_return_irq
871 * This is the main kernel exit path. First we check if we
872 * are about to re-enable interrupts
875 lbz r6,PACASOFTIRQEN(r13)
877 beq .Lrestore_irq_off
879 /* We are enabling, were we already enabled ? Yes, just return */
884 * We are about to soft-enable interrupts (we are hard disabled
885 * at this point). We check if there's anything that needs to
888 lbz r0,PACAIRQHAPPENED(r13)
890 bne- .Lrestore_check_irq_replay
893 * Get here when nothing happened while soft-disabled, just
894 * soft-enable and move-on. We will hard-enable as a side
900 stb r0,PACASOFTIRQEN(r13);
903 * Final return path. BookE is handled in a different file
906 #ifdef CONFIG_PPC_BOOK3E
907 b exception_return_book3e
910 * Clear the reservation. If we know the CPU tracks the address of
911 * the reservation then we can potentially save some cycles and use
912 * a larx. On POWER6 and POWER7 this is significantly faster.
915 stdcx. r0,0,r1 /* to clear the reservation */
918 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
921 * Some code path such as load_up_fpu or altivec return directly
922 * here. They run entirely hard disabled and do not alter the
923 * interrupt state. They also don't use lwarx/stwcx. and thus
924 * are known not to leave dangling reservations.
926 .globl fast_exception_return
927 fast_exception_return:
939 beq- .Lunrecov_restore
941 /* Load PPR from thread struct before we clear MSR:RI */
943 ld r2,PACACURRENT(r13)
944 ld r2,TASKTHREADPPR(r2)
945 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
948 * Clear RI before restoring r13. If we are returning to
949 * userspace and we take an exception after restoring r13,
950 * we end up corrupting the userspace r13 value.
955 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
957 std r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */
960 * r13 is our per cpu area, only restore it if we are returning to
961 * userspace the value stored in the stack frame may belong to
967 mtspr SPRN_PPR,r2 /* Restore PPR */
968 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
969 ACCOUNT_CPU_USER_EXIT(r13, r2, r4)
985 b . /* prevent speculative execution */
987 1: mtspr SPRN_SRR1,r3
1000 b . /* prevent speculative execution */
1002 #endif /* CONFIG_PPC_BOOK3E */
1005 * We are returning to a context with interrupts soft disabled.
1007 * However, we may also about to hard enable, so we need to
1008 * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
1009 * or that bit can get out of sync and bad things will happen
1013 lbz r7,PACAIRQHAPPENED(r13)
1016 rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
1017 stb r7,PACAIRQHAPPENED(r13)
1019 #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
1020 /* The interrupt should not have soft enabled. */
1021 lbz r7,PACASOFTIRQEN(r13)
1023 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
1028 * Something did happen, check if a re-emit is needed
1029 * (this also clears paca->irq_happened)
1031 .Lrestore_check_irq_replay:
1032 /* XXX: We could implement a fast path here where we check
1033 * for irq_happened being just 0x01, in which case we can
1034 * clear it and return. That means that we would potentially
1035 * miss a decrementer having wrapped all the way around.
1037 * Still, this might be useful for things like hash_page
1039 bl __check_irq_replay
1041 beq .Lrestore_no_replay
1044 * We need to re-emit an interrupt. We do so by re-using our
1045 * existing exception frame. We first change the trap value,
1046 * but we need to ensure we preserve the low nibble of it
1054 * Then find the right handler and call it. Interrupts are
1055 * still soft-disabled and we keep them that way.
1059 addi r3,r1,STACK_FRAME_OVERHEAD;
1062 1: cmpwi cr0,r3,0xe60
1064 addi r3,r1,STACK_FRAME_OVERHEAD;
1065 bl handle_hmi_exception
1067 1: cmpwi cr0,r3,0x900
1069 addi r3,r1,STACK_FRAME_OVERHEAD;
1072 #ifdef CONFIG_PPC_DOORBELL
1074 #ifdef CONFIG_PPC_BOOK3E
1078 #endif /* CONFIG_PPC_BOOK3E */
1080 addi r3,r1,STACK_FRAME_OVERHEAD;
1081 bl doorbell_exception
1082 #endif /* CONFIG_PPC_DOORBELL */
1083 1: b ret_from_except /* What else to do here ? */
1086 addi r3,r1,STACK_FRAME_OVERHEAD
1087 bl unrecoverable_exception
1090 _ASM_NOKPROBE_SYMBOL(ret_from_except);
1091 _ASM_NOKPROBE_SYMBOL(ret_from_except_lite);
1092 _ASM_NOKPROBE_SYMBOL(resume_kernel);
1093 _ASM_NOKPROBE_SYMBOL(fast_exc_return_irq);
1094 _ASM_NOKPROBE_SYMBOL(restore);
1095 _ASM_NOKPROBE_SYMBOL(fast_exception_return);
1098 #ifdef CONFIG_PPC_RTAS
1100 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1101 * called with the MMU off.
1103 * In addition, we need to be in 32b mode, at least for now.
1105 * Note: r3 is an input parameter to rtas, so don't trash it...
1110 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
1112 /* Because RTAS is running in 32b mode, it clobbers the high order half
1113 * of all registers that it saves. We therefore save those registers
1114 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
1116 SAVE_GPR(2, r1) /* Save the TOC */
1117 SAVE_GPR(13, r1) /* Save paca */
1118 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
1119 SAVE_10GPRS(22, r1) /* ditto */
1132 /* Temporary workaround to clear CR until RTAS can be modified to
1139 /* There is no way it is acceptable to get here with interrupts enabled,
1140 * check it with the asm equivalent of WARN_ON
1142 lbz r0,PACASOFTIRQEN(r13)
1144 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
1147 /* Hard-disable interrupts */
1153 /* Unfortunately, the stack pointer and the MSR are also clobbered,
1154 * so they are saved in the PACA which allows us to restore
1155 * our original state after RTAS returns.
1158 std r6,PACASAVEDMSR(r13)
1160 /* Setup our real return addr */
1161 LOAD_REG_ADDR(r4,rtas_return_loc)
1162 clrldi r4,r4,2 /* convert to realmode address */
1166 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
1170 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
1171 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE
1175 sync /* disable interrupts so SRR0/1 */
1176 mtmsrd r0 /* don't get trashed */
1178 LOAD_REG_ADDR(r4, rtas)
1179 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
1180 ld r4,RTASBASE(r4) /* get the rtas->base value */
1185 b . /* prevent speculative execution */
1190 /* relocation is off at this point */
1192 clrldi r4,r4,2 /* convert to realmode address */
1196 ld r3,(1f-0b)(r3) /* get &rtas_restore_regs */
1204 ld r1,PACAR1(r4) /* Restore our SP */
1205 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
1210 b . /* prevent speculative execution */
1211 _ASM_NOKPROBE_SYMBOL(__enter_rtas)
1212 _ASM_NOKPROBE_SYMBOL(rtas_return_loc)
1215 1: .8byte rtas_restore_regs
1218 /* relocation is on at this point */
1219 REST_GPR(2, r1) /* Restore the TOC */
1220 REST_GPR(13, r1) /* Restore paca */
1221 REST_8GPRS(14, r1) /* Restore the non-volatiles */
1222 REST_10GPRS(22, r1) /* ditto */
1237 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
1238 ld r0,16(r1) /* get return address */
1241 blr /* return to caller */
1243 #endif /* CONFIG_PPC_RTAS */
1248 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
1250 /* Because PROM is running in 32b mode, it clobbers the high order half
1251 * of all registers that it saves. We therefore save those registers
1252 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
1263 /* Put PROM address in SRR0 */
1266 /* Setup our trampoline return addr in LR */
1269 addi r4,r4,(1f - 0b)
1272 /* Prepare a 32-bit mode big endian MSR
1274 #ifdef CONFIG_PPC_BOOK3E
1275 rlwinm r11,r11,0,1,31
1278 #else /* CONFIG_PPC_BOOK3E */
1279 LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_ISF | MSR_LE)
1283 #endif /* CONFIG_PPC_BOOK3E */
1285 1: /* Return from OF */
1288 /* Just make sure that r1 top 32 bits didn't get
1293 /* Restore the MSR (back to 64 bits) */
1298 /* Restore other registers */
1306 addi r1,r1,PROM_FRAME_SIZE