1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
13 * This file contains the system call entry code, context switch
14 * code, and exception/interrupt return code for PowerPC.
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/sys.h>
20 #include <linux/threads.h>
21 #include <linux/linkage.h>
26 #include <asm/cputable.h>
27 #include <asm/thread_info.h>
28 #include <asm/ppc_asm.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/unistd.h>
31 #include <asm/ptrace.h>
32 #include <asm/feature-fixups.h>
33 #include <asm/barrier.h>
36 #include <asm/interrupt.h>
41 * powerpc relies on return from interrupt/syscall being context synchronising
42 * (which rfi is) to support ARCH_HAS_MEMBARRIER_SYNC_CORE without additional
43 * synchronisation instructions.
47 * Align to 4k in order to ensure that all functions modyfing srr0/srr1
48 * fit into one page in order to not encounter a TLB miss between the
49 * modification of srr0/srr1 and the associated rfi.
53 #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_E500)
54 .globl prepare_transfer_to_handler
55 prepare_transfer_to_handler:
56 /* if from kernel, check interrupted DOZE/NAP mode */
57 lwz r12,TI_LOCAL_FLAGS(r2)
60 bt- 31-TLF_SLEEPING,7f
63 4: rlwinm r12,r12,0,~_TLF_NAPPING
64 stw r12,TI_LOCAL_FLAGS(r2)
65 b power_save_ppc32_restore
67 7: rlwinm r12,r12,0,~_TLF_SLEEPING
68 stw r12,TI_LOCAL_FLAGS(r2)
69 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
70 rlwinm r9,r9,0,~MSR_EE
71 lwz r12,_LINK(r11) /* and return to address in LR */
73 b fast_exception_return
74 _ASM_NOKPROBE_SYMBOL(prepare_transfer_to_handler)
75 #endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_PPC_E500 */
77 #if defined(CONFIG_PPC_KUEP) && defined(CONFIG_PPC_BOOK3S_32)
78 SYM_FUNC_START(__kuep_lock)
79 lwz r9, THREAD+THSR0(r2)
80 update_user_segments_by_4 r9, r10, r11, r12
82 SYM_FUNC_END(__kuep_lock)
84 SYM_FUNC_START_LOCAL(__kuep_unlock)
85 lwz r9, THREAD+THSR0(r2)
87 update_user_segments_by_4 r9, r10, r11, r12
89 SYM_FUNC_END(__kuep_unlock)
104 .globl transfer_to_syscall
106 stw r3, ORIG_GPR3(r1)
111 #ifdef CONFIG_BOOKE_OR_40x
112 rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */
114 lis r12,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
116 addi r12,r12,STACK_FRAME_REGS_MARKER@l
118 li r2, INTERRUPT_SYSCALL
119 stw r12,STACK_INT_FRAME_MARKER(r1)
127 /* Calling convention has r3 = regs, r4 = orig r0 */
128 addi r3,r1,STACK_INT_FRAME_REGS
130 bl system_call_exception
133 addi r4,r1,STACK_INT_FRAME_REGS
135 bl syscall_exit_prepare
136 #ifdef CONFIG_PPC_47x
137 lis r4,icache_44x_need_flush@ha
138 lwz r5,icache_44x_need_flush@l(r4)
140 bne- .L44x_icache_flush
141 #endif /* CONFIG_PPC_47x */
142 .L44x_icache_flush_return:
162 b . /* Prevent prefetch past rfi */
179 stw r7,icache_44x_need_flush@l(r4)
180 b .L44x_icache_flush_return
181 #endif /* CONFIG_44x */
187 li r3,0 /* fork() return value */
190 .globl ret_from_kernel_user_thread
191 ret_from_kernel_user_thread:
200 .globl start_kernel_thread
208 * This must not return. We actually want to BUG here, not WARN,
209 * because BUG will exit the process which is what the kernel thread
210 * should have done, which may give some hope of continuing.
213 EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,0
215 .globl fast_exception_return
216 fast_exception_return:
217 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
218 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
219 beq 3f /* if not, we've got problems */
227 /* Clear the exception marker on the stack to avoid confusing stacktrace */
231 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
241 b . /* Prevent prefetch past rfi */
243 _ASM_NOKPROBE_SYMBOL(fast_exception_return)
245 /* aargh, a nonrecoverable interrupt, panic */
246 /* aargh, we don't know which trap this is */
250 prepare_transfer_to_handler
251 bl unrecoverable_exception
252 trap /* should not get here */
254 .globl interrupt_return
257 addi r3,r1,STACK_INT_FRAME_REGS
259 beq .Lkernel_interrupt_return
260 bl interrupt_exit_user_prepare
263 bne- .Lrestore_nvgprs
265 .Lfast_user_interrupt_return:
272 stwcx. r0,0,r1 /* to clear the reservation */
275 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
284 * Leaving a stale exception marker on the stack can confuse
285 * the reliable stack unwinder later on. Clear it.
300 b . /* Prevent prefetch past rfi */
305 b .Lfast_user_interrupt_return
307 .Lkernel_interrupt_return:
308 bl interrupt_exit_kernel_prepare
310 .Lfast_kernel_interrupt_return:
318 stwcx. r0,0,r1 /* to clear the reservation */
321 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
336 * Leaving a stale exception marker on the stack can confuse
337 * the reliable stack unwinder later on. Clear it.
343 bne- cr1,1f /* emulate stack store */
350 b . /* Prevent prefetch past rfi */
354 * Emulate stack store with update. New r1 value was already calculated
355 * and updated in our interrupt regs by emulate_loadstore, but we can't
356 * store the previous value of r1 to the stack before re-loading our
357 * registers from it, otherwise they could be clobbered. Use
358 * SPRG Scratch0 as temporary storage to hold the store
359 * data, as interrupts are disabled here so it won't be clobbered.
363 mtspr SPRN_SPRG_WSCRATCH0, r9
365 mtspr SPRN_SPRG_SCRATCH0, r9
367 addi r9,r1,INT_FRAME_SIZE /* get original r1 */
371 stw r9,0(r1) /* perform store component of stwu */
373 mfspr r9, SPRN_SPRG_RSCRATCH0
375 mfspr r9, SPRN_SPRG_SCRATCH0
379 b . /* Prevent prefetch past rfi */
381 _ASM_NOKPROBE_SYMBOL(interrupt_return)
383 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
386 * Returning from a critical interrupt in user mode doesn't need
387 * to be any different from a normal exception. For a critical
388 * interrupt in the kernel, we just return (without checking for
389 * preemption) since the interrupt may have happened at some crucial
390 * place (e.g. inside the TLB miss handler), and because we will be
391 * running with r1 pointing into critical_stack, not the current
392 * process's kernel stack (and therefore current_thread_info() will
393 * give the wrong answer).
394 * We have to restore various SPRs that may have been in use at the
395 * time of the critical interrupt.
399 #define PPC_40x_TURN_OFF_MSR_DR \
400 /* avoid any possible TLB misses here by turning off MSR.DR, we \
401 * assume the instructions here are mapped by a pinned TLB entry */ \
407 #define PPC_40x_TURN_OFF_MSR_DR
410 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
413 andi. r3,r3,MSR_PR; \
414 bne interrupt_return; \
416 REST_GPRS(2, 8, r1); \
419 mtspr SPRN_XER,r10; \
421 stwcx. r0,0,r1; /* to clear the reservation */ \
426 PPC_40x_TURN_OFF_MSR_DR; \
429 mtspr SPRN_DEAR,r9; \
430 mtspr SPRN_ESR,r10; \
433 mtspr exc_lvl_srr0,r11; \
434 mtspr exc_lvl_srr1,r12; \
435 REST_GPRS(9, 12, r1); \
438 b .; /* prevent prefetch past exc_lvl_rfi */
440 #define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \
441 lwz r9,_##exc_lvl_srr0(r1); \
442 lwz r10,_##exc_lvl_srr1(r1); \
443 mtspr SPRN_##exc_lvl_srr0,r9; \
444 mtspr SPRN_##exc_lvl_srr1,r10;
446 #if defined(CONFIG_PPC_E500)
447 #ifdef CONFIG_PHYS_64BIT
448 #define RESTORE_MAS7 \
453 #endif /* CONFIG_PHYS_64BIT */
454 #define RESTORE_MMU_REGS \
458 mtspr SPRN_MAS0,r9; \
460 mtspr SPRN_MAS1,r10; \
462 mtspr SPRN_MAS2,r11; \
463 mtspr SPRN_MAS3,r9; \
464 mtspr SPRN_MAS6,r10; \
466 #elif defined(CONFIG_44x)
467 #define RESTORE_MMU_REGS \
471 #define RESTORE_MMU_REGS
475 .globl ret_from_crit_exc
478 lwz r9,crit_srr0@l(r9);
479 lis r10,crit_srr1@ha;
480 lwz r10,crit_srr1@l(r10);
483 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
484 _ASM_NOKPROBE_SYMBOL(ret_from_crit_exc)
485 #endif /* CONFIG_40x */
488 .globl ret_from_crit_exc
490 RESTORE_xSRR(SRR0,SRR1);
492 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
493 _ASM_NOKPROBE_SYMBOL(ret_from_crit_exc)
495 .globl ret_from_debug_exc
497 RESTORE_xSRR(SRR0,SRR1);
498 RESTORE_xSRR(CSRR0,CSRR1);
500 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
501 _ASM_NOKPROBE_SYMBOL(ret_from_debug_exc)
503 .globl ret_from_mcheck_exc
505 RESTORE_xSRR(SRR0,SRR1);
506 RESTORE_xSRR(CSRR0,CSRR1);
507 RESTORE_xSRR(DSRR0,DSRR1);
509 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
510 _ASM_NOKPROBE_SYMBOL(ret_from_mcheck_exc)
511 #endif /* CONFIG_BOOKE */
512 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */