1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
13 * This file contains the system call entry code, context switch
14 * code, and exception/interrupt return code for PowerPC.
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/sys.h>
20 #include <linux/threads.h>
24 #include <asm/cputable.h>
25 #include <asm/thread_info.h>
26 #include <asm/ppc_asm.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/unistd.h>
29 #include <asm/ptrace.h>
30 #include <asm/export.h>
31 #include <asm/asm-405.h>
32 #include <asm/feature-fixups.h>
33 #include <asm/barrier.h>
40 * Align to 4k in order to ensure that all functions modyfing srr0/srr1
41 * fit into one page in order to not encounter a TLB miss between the
42 * modification of srr0/srr1 and the associated rfi.
47 .globl mcheck_transfer_to_handler
48 mcheck_transfer_to_handler:
55 .globl debug_transfer_to_handler
56 debug_transfer_to_handler:
63 .globl crit_transfer_to_handler
64 crit_transfer_to_handler:
65 #ifdef CONFIG_PPC_BOOK3E_MMU
76 #ifdef CONFIG_PHYS_64BIT
79 #endif /* CONFIG_PHYS_64BIT */
80 #endif /* CONFIG_PPC_BOOK3E_MMU */
90 /* set the stack limit to the current stack */
91 mfspr r8,SPRN_SPRG_THREAD
93 stw r0,SAVED_KSP_LIMIT(r11)
94 rlwinm r0,r1,0,0,(31 - THREAD_SHIFT)
100 .globl crit_transfer_to_handler
101 crit_transfer_to_handler:
107 stw r0,crit_srr0@l(0)
109 stw r0,crit_srr1@l(0)
111 /* set the stack limit to the current stack */
112 mfspr r8,SPRN_SPRG_THREAD
114 stw r0,saved_ksp_limit@l(0)
115 rlwinm r0,r1,0,0,(31 - THREAD_SHIFT)
121 * This code finishes saving the registers to the exception frame
122 * and jumps to the appropriate handler for the exception, turning
123 * on address translation.
124 * Note that we rely on the caller having set cr0.eq iff the exception
125 * occurred in kernel mode (i.e. MSR:PR = 0).
127 .globl transfer_to_handler_full
128 transfer_to_handler_full:
132 .globl transfer_to_handler
142 mfspr r12,SPRN_SPRG_THREAD
143 beq 2f /* if from user, fix up THREAD.regs */
144 addi r2, r12, -THREAD
145 addi r11,r1,STACK_FRAME_OVERHEAD
147 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
148 /* Check to see if the dbcr0 register is set up to debug. Use the
149 internal debug mode bit to do this. */
150 lwz r12,THREAD_DBCR0(r12)
151 andis. r12,r12,DBCR0_IDM@h
153 ACCOUNT_CPU_USER_ENTRY(r2, r11, r12)
154 #ifdef CONFIG_PPC_BOOK3S_32
157 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
159 /* From user and task is ptraced - load up global dbcr0 */
160 li r12,-1 /* clear all pending debug events */
162 lis r11,global_dbcr0@ha
164 addi r11,r11,global_dbcr0@l
179 2: /* if from kernel, check interrupted DOZE/NAP mode and
180 * check for stack overflow
182 kuap_save_and_lock r11, r12, r9, r2, r6
183 addi r2, r12, -THREAD
184 lwz r9,KSP_LIMIT(r12)
185 cmplw r1,r9 /* if r1 <= ksp_limit */
186 ble- stack_ovf /* then the kernel stack overflowed */
188 #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500)
189 lwz r12,TI_LOCAL_FLAGS(r2)
191 bt- 31-TLF_NAPPING,4f
192 bt- 31-TLF_SLEEPING,7f
193 #endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_E500 */
194 .globl transfer_to_handler_cont
195 transfer_to_handler_cont:
198 tovirt(r2, r2) /* set r2 to current */
199 lwz r11,0(r9) /* virtual address of handler */
200 lwz r9,4(r9) /* where to go when done */
201 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
204 #ifdef CONFIG_TRACE_IRQFLAGS
206 * When tracing IRQ state (lockdep) we enable the MMU before we call
207 * the IRQ tracing functions as they might access vmalloc space or
208 * perform IOs for console output.
210 * To speed up the syscall path where interrupts stay on, let's check
211 * first if we are changing the MSR value at all.
218 /* MSR isn't changing, just transition directly */
224 RFI /* jump to handler, enable MMU */
226 #ifdef CONFIG_TRACE_IRQFLAGS
227 1: /* MSR is changing, re-enable MMU so we can notify lockdep. We need to
228 * keep interrupts disabled at this point otherwise we might risk
229 * taking an interrupt before we tell lockdep they are enabled.
231 lis r12,reenable_mmu@h
232 ori r12,r12,reenable_mmu@l
233 LOAD_REG_IMMEDIATE(r0, MSR_KERNEL)
241 * We save a bunch of GPRs,
242 * r3 can be different from GPR3(r1) at this point, r9 and r11
243 * contains the old MSR and handler address respectively,
244 * r4 & r5 can contain page fault arguments that need to be passed
245 * along as well. r12, CCR, CTR, XER etc... are left clobbered as
246 * they aren't useful past this point (aren't syscall arguments),
247 * the rest is restored from the exception frame.
257 /* If we are disabling interrupts (normal case), simply log it with
260 1: bl trace_hardirqs_off
273 bctr /* jump to handler */
274 #endif /* CONFIG_TRACE_IRQFLAGS */
276 #if defined (CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500)
277 4: rlwinm r12,r12,0,~_TLF_NAPPING
278 stw r12,TI_LOCAL_FLAGS(r2)
279 b power_save_ppc32_restore
281 7: rlwinm r12,r12,0,~_TLF_SLEEPING
282 stw r12,TI_LOCAL_FLAGS(r2)
283 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
284 rlwinm r9,r9,0,~MSR_EE
285 lwz r12,_LINK(r11) /* and return to address in LR */
286 kuap_restore r11, r2, r3, r4, r5
288 b fast_exception_return
292 * On kernel stack overflow, load up an initial stack pointer
293 * and call StackOverflow(regs), which should not return.
296 /* sometimes we use a statically-allocated stack, which is OK. */
300 ble 5b /* r1 <= &_end is OK */
302 addi r3,r1,STACK_FRAME_OVERHEAD
303 lis r1,init_thread_union@ha
304 addi r1,r1,init_thread_union@l
305 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
306 lis r9,StackOverflow@ha
307 addi r9,r9,StackOverflow@l
308 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL)
309 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
317 #ifdef CONFIG_TRACE_IRQFLAGS
318 trace_syscall_entry_irq_off:
320 * Syscall shouldn't happen while interrupts are disabled,
321 * so let's do a warning here.
324 EMIT_BUG_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING
327 /* Now enable for real */
328 LOAD_REG_IMMEDIATE(r10, MSR_KERNEL | MSR_EE)
335 #endif /* CONFIG_TRACE_IRQFLAGS */
337 .globl transfer_to_syscall
339 #ifdef CONFIG_PPC_BOOK3S_32
342 #ifdef CONFIG_TRACE_IRQFLAGS
344 beq- trace_syscall_entry_irq_off
345 #endif /* CONFIG_TRACE_IRQFLAGS */
348 * Handle a system call.
350 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
351 .stabs "entry_32.S",N_SO,0,0,0f
358 #ifdef CONFIG_TRACE_IRQFLAGS
359 /* Make sure interrupts are enabled */
362 /* We came in with interrupts disabled, we WARN and mark them enabled
365 EMIT_BUG_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING
366 #endif /* CONFIG_TRACE_IRQFLAGS */
368 andi. r11,r11,_TIF_SYSCALL_DOTRACE
370 syscall_dotrace_cont:
371 cmplwi 0,r0,NR_syscalls
372 lis r10,sys_call_table@h
373 ori r10,r10,sys_call_table@l
379 * Prevent the load of the handler below (based on the user-passed
380 * system call number) being speculatively executed until the test
381 * against NR_syscalls and branch to .66f above has
385 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
387 addi r9,r1,STACK_FRAME_OVERHEAD
389 blrl /* Call handler */
390 .globl ret_from_syscall
392 #ifdef CONFIG_DEBUG_RSEQ
393 /* Check whether the syscall is issued inside a restartable sequence */
395 addi r3,r1,STACK_FRAME_OVERHEAD
400 /* disable interrupts so current_thread_info()->flags can't change */
401 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL) /* doesn't include MSR_EE */
402 /* Note: We don't bother telling lockdep about it */
407 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
408 bne- syscall_exit_work
410 blt+ syscall_exit_cont
411 lwz r11,_CCR(r1) /* Load CR */
413 oris r11,r11,0x1000 /* Set SO bit in CR */
417 #ifdef CONFIG_TRACE_IRQFLAGS
418 /* If we are going to return from the syscall with interrupts
419 * off, we trace that here. It shouldn't normally happen.
424 bl trace_hardirqs_off
427 #endif /* CONFIG_TRACE_IRQFLAGS */
428 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
429 /* If the process has its own DBCR0 value, load it up. The internal
430 debug mode bit tells us that dbcr0 should be loaded. */
431 lwz r0,THREAD+THREAD_DBCR0(r2)
432 andis. r10,r0,DBCR0_IDM@h
436 BEGIN_MMU_FTR_SECTION
437 lis r4,icache_44x_need_flush@ha
438 lwz r5,icache_44x_need_flush@l(r4)
442 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x)
443 #endif /* CONFIG_44x */
446 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
447 stwcx. r0,0,r1 /* to clear the reservation */
448 ACCOUNT_CPU_USER_EXIT(r2, r5, r7)
449 #ifdef CONFIG_PPC_BOOK3S_32
460 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
470 stw r7,icache_44x_need_flush@l(r4)
472 #endif /* CONFIG_44x */
484 .globl ret_from_kernel_thread
485 ret_from_kernel_thread:
495 /* Traced system call support */
500 addi r3,r1,STACK_FRAME_OVERHEAD
501 bl do_syscall_trace_enter
503 * Restore argument registers possibly just changed.
504 * We use the return value of do_syscall_trace_enter
505 * for call number to look up in the table (r0).
516 cmplwi r0,NR_syscalls
517 /* Return code is already in r3 thanks to do_syscall_trace_enter() */
518 bge- ret_from_syscall
519 b syscall_dotrace_cont
522 andi. r0,r9,_TIF_RESTOREALL
528 andi. r0,r9,_TIF_NOERROR
530 lwz r11,_CCR(r1) /* Load CR */
532 oris r11,r11,0x1000 /* Set SO bit in CR */
535 1: stw r6,RESULT(r1) /* Save result */
536 stw r3,GPR3(r1) /* Update return value */
537 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
540 /* Clear per-syscall TIF flags if any are set. */
542 li r11,_TIF_PERSYSCALL_MASK
546 #ifdef CONFIG_IBM405_ERR77
552 4: /* Anything which requires enabling interrupts? */
553 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
556 /* Re-enable interrupts. There is no need to trace that with
557 * lockdep as we are supposed to have IRQs on at this point
563 /* Save NVGPRS if they're not saved already */
571 addi r3,r1,STACK_FRAME_OVERHEAD
572 bl do_syscall_trace_leave
573 b ret_from_except_full
576 * The fork/clone functions need to copy the full register set into
577 * the child process. Therefore we need to save all the nonvolatile
578 * registers (r13 - r31) before calling the C code.
584 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
585 stw r0,_TRAP(r1) /* register set saved */
592 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
593 stw r0,_TRAP(r1) /* register set saved */
600 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
601 stw r0,_TRAP(r1) /* register set saved */
608 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
609 stw r0,_TRAP(r1) /* register set saved */
612 .globl ppc_swapcontext
616 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
617 stw r0,_TRAP(r1) /* register set saved */
621 * Top-level page fault handling.
622 * This is in assembler because if do_page_fault tells us that
623 * it is a bad kernel page fault, we want to save the non-volatile
624 * registers before calling bad_page_fault.
626 .globl handle_page_fault
629 addi r3,r1,STACK_FRAME_OVERHEAD
630 #ifdef CONFIG_PPC_BOOK3S_32
631 andis. r0,r5,DSISR_DABRMATCH@h
632 bne- handle_dabr_fault
642 addi r3,r1,STACK_FRAME_OVERHEAD
645 b ret_from_except_full
647 #ifdef CONFIG_PPC_BOOK3S_32
648 /* We have a data breakpoint exception - handle it */
655 b ret_from_except_full
659 * This routine switches between two different tasks. The process
660 * state of one is saved on its kernel stack. Then the state
661 * of the other is restored from its kernel stack. The memory
662 * management hardware is updated to the second process's state.
663 * Finally, we can return to the second process.
664 * On entry, r3 points to the THREAD for the current task, r4
665 * points to the THREAD for the new task.
667 * This routine is always called with interrupts disabled.
669 * Note: there are two ways to get to the "going out" portion
670 * of this code; either by coming in via the entry (_switch)
671 * or via "fork" which must set up an environment equivalent
672 * to the "_switch" path. If you change this , you'll have to
673 * change the fork code also.
675 * The code which creates the new task context is in 'copy_thread'
676 * in arch/ppc/kernel/process.c
679 stwu r1,-INT_FRAME_SIZE(r1)
681 stw r0,INT_FRAME_SIZE+4(r1)
682 /* r3-r12 are caller saved -- Cort */
684 stw r0,_NIP(r1) /* Return to switch caller */
686 li r0,MSR_FP /* Disable floating-point */
687 #ifdef CONFIG_ALTIVEC
689 oris r0,r0,MSR_VEC@h /* Disable altivec */
690 mfspr r12,SPRN_VRSAVE /* save vrsave register value */
691 stw r12,THREAD+THREAD_VRSAVE(r2)
692 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
693 #endif /* CONFIG_ALTIVEC */
696 oris r0,r0,MSR_SPE@h /* Disable SPE */
697 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
698 stw r12,THREAD+THREAD_SPEFSCR(r2)
699 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
700 #endif /* CONFIG_SPE */
701 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
709 stw r1,KSP(r3) /* Set old stack pointer */
713 /* We need a sync somewhere here to make sure that if the
714 * previous task gets rescheduled on another CPU, it sees all
715 * stores it has performed on this one.
718 #endif /* CONFIG_SMP */
721 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */
722 lwz r1,KSP(r4) /* Load new stack pointer */
724 /* save the old current 'last' for return value */
726 addi r2,r4,-THREAD /* Update current */
728 #ifdef CONFIG_ALTIVEC
730 lwz r0,THREAD+THREAD_VRSAVE(r2)
731 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
732 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
733 #endif /* CONFIG_ALTIVEC */
736 lwz r0,THREAD+THREAD_SPEFSCR(r2)
737 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
738 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
739 #endif /* CONFIG_SPE */
743 /* r3-r12 are destroyed -- Cort */
746 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
748 addi r1,r1,INT_FRAME_SIZE
751 .globl fast_exception_return
752 fast_exception_return:
753 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
754 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
755 beq 1f /* if not, we've got problems */
758 2: REST_4GPRS(3, r11)
764 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
768 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
779 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
780 /* check if the exception happened in a restartable section */
781 1: lis r3,exc_exit_restart_end@ha
782 addi r3,r3,exc_exit_restart_end@l
784 #ifdef CONFIG_PPC_BOOK3S_601
789 lis r4,exc_exit_restart@ha
790 addi r4,r4,exc_exit_restart@l
792 #ifdef CONFIG_PPC_BOOK3S_601
797 lis r3,fee_restarts@ha
799 lwz r5,fee_restarts@l(r3)
801 stw r5,fee_restarts@l(r3)
802 mr r12,r4 /* restart at exc_exit_restart */
811 /* aargh, a nonrecoverable interrupt, panic */
812 /* aargh, we don't know which trap this is */
813 /* but the 601 doesn't implement the RI bit, so assume it's OK */
817 addi r3,r1,STACK_FRAME_OVERHEAD
819 ori r10,r10,MSR_KERNEL@l
820 bl transfer_to_handler_full
821 .long unrecoverable_exception
822 .long ret_from_except
825 .globl ret_from_except_full
826 ret_from_except_full:
830 .globl ret_from_except
832 /* Hard-disable interrupts so that current_thread_info()->flags
833 * can't change between when we test it and when we return
834 * from the interrupt. */
835 /* Note: We don't bother telling lockdep about it */
836 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL)
837 SYNC /* Some chip revs have problems here... */
838 MTMSRD(r10) /* disable interrupts */
840 lwz r3,_MSR(r1) /* Returning to user mode? */
844 user_exc_return: /* r10 contains MSR_KERNEL here */
845 /* Check current_thread_info()->flags */
847 andi. r0,r9,_TIF_USER_WORK_MASK
851 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
852 /* Check whether this process has its own DBCR0 value. The internal
853 debug mode bit tells us that dbcr0 should be loaded. */
854 lwz r0,THREAD+THREAD_DBCR0(r2)
855 andis. r10,r0,DBCR0_IDM@h
858 ACCOUNT_CPU_USER_EXIT(r2, r10, r11)
859 #ifdef CONFIG_PPC_BOOK3S_32
865 /* N.B. the only way to get here is from the beq following ret_from_except. */
867 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
869 andis. r0,r8,_TIF_EMULATE_STACK_STORE@h
872 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
875 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
876 mr r4,r1 /* src: current exception frame */
877 mr r1,r3 /* Reroute the trampoline frame to r1 */
879 /* Copy from the original to the trampoline. */
880 li r5,INT_FRAME_SIZE/4 /* size: INT_FRAME_SIZE */
881 li r6,0 /* start offset: 0 */
888 /* Do real store operation to complete stwu */
892 /* Clear _TIF_EMULATE_STACK_STORE flag */
893 lis r11,_TIF_EMULATE_STACK_STORE@h
897 #ifdef CONFIG_IBM405_ERR77
904 #ifdef CONFIG_PREEMPT
905 /* check current_thread_info->preempt_count */
906 lwz r0,TI_PREEMPT(r2)
907 cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
909 andi. r8,r8,_TIF_NEED_RESCHED
912 andi. r0,r3,MSR_EE /* interrupts off? */
913 beq restore_kuap /* don't schedule if so */
914 #ifdef CONFIG_TRACE_IRQFLAGS
915 /* Lockdep thinks irqs are enabled, we need to call
916 * preempt_schedule_irq with IRQs off, so we inform lockdep
917 * now that we -did- turn them off already
919 bl trace_hardirqs_off
921 bl preempt_schedule_irq
922 #ifdef CONFIG_TRACE_IRQFLAGS
923 /* And now, to properly rebalance the above, we tell lockdep they
924 * are being turned back on, which will happen when we return
928 #endif /* CONFIG_PREEMPT */
930 kuap_restore r1, r2, r9, r10, r0
932 /* interrupts are hard-disabled at this point */
935 BEGIN_MMU_FTR_SECTION
937 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
938 lis r4,icache_44x_need_flush@ha
939 lwz r5,icache_44x_need_flush@l(r4)
944 stw r6,icache_44x_need_flush@l(r4)
946 #endif /* CONFIG_44x */
949 #ifdef CONFIG_TRACE_IRQFLAGS
950 /* Lockdep doesn't know about the fact that IRQs are temporarily turned
951 * off in this assembly code while peeking at TI_FLAGS() and such. However
952 * we need to inform it if the exception turned interrupts off, and we
953 * are about to trun them back on.
964 #endif /* CONFIG_TRACE_IRQFLAGS */
979 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
980 stwcx. r0,0,r1 /* to clear the reservation */
982 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
983 andi. r10,r9,MSR_RI /* check if this exception occurred */
984 beql nonrecoverable /* at a bad place (MSR:RI = 0) */
991 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
995 * Once we put values in SRR0 and SRR1, we are in a state
996 * where exceptions are not recoverable, since taking an
997 * exception will trash SRR0 and SRR1. Therefore we clear the
998 * MSR:RI bit to indicate this. If we do take an exception,
999 * we can't return to the point of the exception but we
1000 * can restart the exception exit path at the label
1001 * exc_exit_restart below. -- paulus
1003 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL & ~MSR_RI)
1005 MTMSRD(r10) /* clear the RI bit */
1006 .globl exc_exit_restart
1013 .globl exc_exit_restart_end
1014 exc_exit_restart_end:
1018 #else /* !(CONFIG_4xx || CONFIG_BOOKE) */
1020 * This is a bit different on 4xx/Book-E because it doesn't have
1021 * the RI bit in the MSR.
1022 * The TLB miss handler checks if we have interrupted
1023 * the exception exit path and restarts it if so
1024 * (well maybe one day it will... :).
1030 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
1034 .globl exc_exit_restart
1043 .globl exc_exit_restart_end
1044 exc_exit_restart_end:
1047 b . /* prevent prefetch past rfi */
1050 * Returning from a critical interrupt in user mode doesn't need
1051 * to be any different from a normal exception. For a critical
1052 * interrupt in the kernel, we just return (without checking for
1053 * preemption) since the interrupt may have happened at some crucial
1054 * place (e.g. inside the TLB miss handler), and because we will be
1055 * running with r1 pointing into critical_stack, not the current
1056 * process's kernel stack (and therefore current_thread_info() will
1057 * give the wrong answer).
1058 * We have to restore various SPRs that may have been in use at the
1059 * time of the critical interrupt.
1063 #define PPC_40x_TURN_OFF_MSR_DR \
1064 /* avoid any possible TLB misses here by turning off MSR.DR, we \
1065 * assume the instructions here are mapped by a pinned TLB entry */ \
1071 #define PPC_40x_TURN_OFF_MSR_DR
1074 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
1077 andi. r3,r3,MSR_PR; \
1078 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL); \
1079 bne user_exc_return; \
1082 REST_4GPRS(3, r1); \
1083 REST_2GPRS(7, r1); \
1086 mtspr SPRN_XER,r10; \
1088 PPC405_ERR77(0,r1); \
1089 stwcx. r0,0,r1; /* to clear the reservation */ \
1090 lwz r11,_LINK(r1); \
1094 PPC_40x_TURN_OFF_MSR_DR; \
1097 mtspr SPRN_DEAR,r9; \
1098 mtspr SPRN_ESR,r10; \
1101 mtspr exc_lvl_srr0,r11; \
1102 mtspr exc_lvl_srr1,r12; \
1104 lwz r12,GPR12(r1); \
1105 lwz r10,GPR10(r1); \
1106 lwz r11,GPR11(r1); \
1108 PPC405_ERR77_SYNC; \
1110 b .; /* prevent prefetch past exc_lvl_rfi */
1112 #define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \
1113 lwz r9,_##exc_lvl_srr0(r1); \
1114 lwz r10,_##exc_lvl_srr1(r1); \
1115 mtspr SPRN_##exc_lvl_srr0,r9; \
1116 mtspr SPRN_##exc_lvl_srr1,r10;
1118 #if defined(CONFIG_PPC_BOOK3E_MMU)
1119 #ifdef CONFIG_PHYS_64BIT
1120 #define RESTORE_MAS7 \
1122 mtspr SPRN_MAS7,r11;
1124 #define RESTORE_MAS7
1125 #endif /* CONFIG_PHYS_64BIT */
1126 #define RESTORE_MMU_REGS \
1130 mtspr SPRN_MAS0,r9; \
1132 mtspr SPRN_MAS1,r10; \
1134 mtspr SPRN_MAS2,r11; \
1135 mtspr SPRN_MAS3,r9; \
1136 mtspr SPRN_MAS6,r10; \
1138 #elif defined(CONFIG_44x)
1139 #define RESTORE_MMU_REGS \
1141 mtspr SPRN_MMUCR,r9;
1143 #define RESTORE_MMU_REGS
1147 .globl ret_from_crit_exc
1149 mfspr r9,SPRN_SPRG_THREAD
1150 lis r10,saved_ksp_limit@ha;
1151 lwz r10,saved_ksp_limit@l(r10);
1153 stw r10,KSP_LIMIT(r9)
1154 lis r9,crit_srr0@ha;
1155 lwz r9,crit_srr0@l(r9);
1156 lis r10,crit_srr1@ha;
1157 lwz r10,crit_srr1@l(r10);
1159 mtspr SPRN_SRR1,r10;
1160 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1161 #endif /* CONFIG_40x */
1164 .globl ret_from_crit_exc
1166 mfspr r9,SPRN_SPRG_THREAD
1167 lwz r10,SAVED_KSP_LIMIT(r1)
1168 stw r10,KSP_LIMIT(r9)
1169 RESTORE_xSRR(SRR0,SRR1);
1171 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1173 .globl ret_from_debug_exc
1175 mfspr r9,SPRN_SPRG_THREAD
1176 lwz r10,SAVED_KSP_LIMIT(r1)
1177 stw r10,KSP_LIMIT(r9)
1178 RESTORE_xSRR(SRR0,SRR1);
1179 RESTORE_xSRR(CSRR0,CSRR1);
1181 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
1183 .globl ret_from_mcheck_exc
1184 ret_from_mcheck_exc:
1185 mfspr r9,SPRN_SPRG_THREAD
1186 lwz r10,SAVED_KSP_LIMIT(r1)
1187 stw r10,KSP_LIMIT(r9)
1188 RESTORE_xSRR(SRR0,SRR1);
1189 RESTORE_xSRR(CSRR0,CSRR1);
1190 RESTORE_xSRR(DSRR0,DSRR1);
1192 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
1193 #endif /* CONFIG_BOOKE */
1196 * Load the DBCR0 value for a task that is being ptraced,
1197 * having first saved away the global DBCR0. Note that r0
1198 * has the dbcr0 value to set upon entry to this.
1201 mfmsr r10 /* first disable debug exceptions */
1202 rlwinm r10,r10,0,~MSR_DE
1205 mfspr r10,SPRN_DBCR0
1206 lis r11,global_dbcr0@ha
1207 addi r11,r11,global_dbcr0@l
1219 mtspr SPRN_DBSR,r11 /* clear all pending debug events */
1224 .global global_dbcr0
1228 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
1230 do_work: /* r10 contains MSR_KERNEL here */
1231 andi. r0,r9,_TIF_NEED_RESCHED
1234 do_resched: /* r10 contains MSR_KERNEL here */
1235 #ifdef CONFIG_TRACE_IRQFLAGS
1236 bl trace_hardirqs_on
1241 MTMSRD(r10) /* hard-enable interrupts */
1244 /* Note: And we don't tell it we are disabling them again
1245 * neither. Those disable/enable cycles used to peek at
1246 * TI_FLAGS aren't advertised.
1248 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL)
1250 MTMSRD(r10) /* disable interrupts */
1252 andi. r0,r9,_TIF_NEED_RESCHED
1254 andi. r0,r9,_TIF_USER_WORK_MASK
1256 do_user_signal: /* r10 contains MSR_KERNEL here */
1259 MTMSRD(r10) /* hard-enable interrupts */
1260 /* save r13-r31 in the exception frame, if not already done */
1267 2: addi r3,r1,STACK_FRAME_OVERHEAD
1274 * We come here when we are at the end of handling an exception
1275 * that occurred at a place where taking an exception will lose
1276 * state information, such as the contents of SRR0 and SRR1.
1279 lis r10,exc_exit_restart_end@ha
1280 addi r10,r10,exc_exit_restart_end@l
1282 #ifdef CONFIG_PPC_BOOK3S_601
1287 lis r11,exc_exit_restart@ha
1288 addi r11,r11,exc_exit_restart@l
1290 #ifdef CONFIG_PPC_BOOK3S_601
1295 lis r10,ee_restarts@ha
1296 lwz r12,ee_restarts@l(r10)
1298 stw r12,ee_restarts@l(r10)
1299 mr r12,r11 /* restart at exc_exit_restart */
1301 3: /* OK, we can't recover, kill this process */
1302 /* but the 601 doesn't implement the RI bit, so assume it's OK */
1309 5: mfspr r2,SPRN_SPRG_THREAD
1311 tovirt(r2,r2) /* set back r2 to current */
1312 4: addi r3,r1,STACK_FRAME_OVERHEAD
1313 bl unrecoverable_exception
1314 /* shouldn't return */
1324 * PROM code for specific machines follows. Put it
1325 * here so it's easy to add arch-specific sections later.
1328 #ifdef CONFIG_PPC_RTAS
1330 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1331 * called with the MMU off.
1334 stwu r1,-INT_FRAME_SIZE(r1)
1336 stw r0,INT_FRAME_SIZE+4(r1)
1337 LOAD_REG_ADDR(r4, rtas)
1338 lis r6,1f@ha /* physical return address for rtas */
1342 lwz r8,RTASENTRY(r4)
1346 LOAD_REG_IMMEDIATE(r0,MSR_KERNEL)
1347 SYNC /* disable interrupts so SRR0/1 */
1348 MTMSRD(r0) /* don't get trashed */
1349 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1351 stw r7, THREAD + RTAS_SP(r2)
1356 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
1357 lwz r9,8(r9) /* original msr value */
1358 addi r1,r1,INT_FRAME_SIZE
1361 stw r0, THREAD + RTAS_SP(r7)
1364 RFI /* return to caller */
1366 .globl machine_check_in_rtas
1367 machine_check_in_rtas:
1369 /* XXX load up BATs and panic */
1371 #endif /* CONFIG_PPC_RTAS */