3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/errno.h>
23 #include <linux/err.h>
24 #include <linux/sys.h>
25 #include <linux/threads.h>
29 #include <asm/cputable.h>
30 #include <asm/thread_info.h>
31 #include <asm/ppc_asm.h>
32 #include <asm/asm-offsets.h>
33 #include <asm/unistd.h>
34 #include <asm/ftrace.h>
35 #include <asm/ptrace.h>
36 #include <asm/export.h>
37 #include <asm/barrier.h>
40 * MSR_KERNEL is > 0x10000 on 4xx/Book-E since it include MSR_CE.
42 #if MSR_KERNEL >= 0x10000
43 #define LOAD_MSR_KERNEL(r, x) lis r,(x)@h; ori r,r,(x)@l
45 #define LOAD_MSR_KERNEL(r, x) li r,(x)
49 .globl mcheck_transfer_to_handler
50 mcheck_transfer_to_handler:
57 .globl debug_transfer_to_handler
58 debug_transfer_to_handler:
65 .globl crit_transfer_to_handler
66 crit_transfer_to_handler:
67 #ifdef CONFIG_PPC_BOOK3E_MMU
78 #ifdef CONFIG_PHYS_64BIT
81 #endif /* CONFIG_PHYS_64BIT */
82 #endif /* CONFIG_PPC_BOOK3E_MMU */
92 /* set the stack limit to the current stack
93 * and set the limit to protect the thread_info
96 mfspr r8,SPRN_SPRG_THREAD
98 stw r0,SAVED_KSP_LIMIT(r11)
99 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
105 .globl crit_transfer_to_handler
106 crit_transfer_to_handler:
112 stw r0,crit_srr0@l(0)
114 stw r0,crit_srr1@l(0)
116 /* set the stack limit to the current stack
117 * and set the limit to protect the thread_info
120 mfspr r8,SPRN_SPRG_THREAD
122 stw r0,saved_ksp_limit@l(0)
123 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
129 * This code finishes saving the registers to the exception frame
130 * and jumps to the appropriate handler for the exception, turning
131 * on address translation.
132 * Note that we rely on the caller having set cr0.eq iff the exception
133 * occurred in kernel mode (i.e. MSR:PR = 0).
135 .globl transfer_to_handler_full
136 transfer_to_handler_full:
140 .globl transfer_to_handler
150 mfspr r12,SPRN_SPRG_THREAD
152 tovirt(r2,r2) /* set r2 to current */
153 beq 2f /* if from user, fix up THREAD.regs */
154 addi r11,r1,STACK_FRAME_OVERHEAD
156 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
157 /* Check to see if the dbcr0 register is set up to debug. Use the
158 internal debug mode bit to do this. */
159 lwz r12,THREAD_DBCR0(r12)
160 andis. r12,r12,DBCR0_IDM@h
162 /* From user and task is ptraced - load up global dbcr0 */
163 li r12,-1 /* clear all pending debug events */
165 lis r11,global_dbcr0@ha
167 addi r11,r11,global_dbcr0@l
169 CURRENT_THREAD_INFO(r9, r1)
180 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
181 CURRENT_THREAD_INFO(r9, r1)
183 ACCOUNT_CPU_USER_ENTRY(r9, r11, r12)
188 2: /* if from kernel, check interrupted DOZE/NAP mode and
189 * check for stack overflow
191 lwz r9,KSP_LIMIT(r12)
192 cmplw r1,r9 /* if r1 <= ksp_limit */
193 ble- stack_ovf /* then the kernel stack overflowed */
195 #if defined(CONFIG_6xx) || defined(CONFIG_E500)
196 CURRENT_THREAD_INFO(r9, r1)
197 tophys(r9,r9) /* check local flags */
198 lwz r12,TI_LOCAL_FLAGS(r9)
200 bt- 31-TLF_NAPPING,4f
201 bt- 31-TLF_SLEEPING,7f
202 #endif /* CONFIG_6xx || CONFIG_E500 */
203 .globl transfer_to_handler_cont
204 transfer_to_handler_cont:
207 lwz r11,0(r9) /* virtual address of handler */
208 lwz r9,4(r9) /* where to go when done */
209 #ifdef CONFIG_TRACE_IRQFLAGS
210 lis r12,reenable_mmu@h
211 ori r12,r12,reenable_mmu@l
216 reenable_mmu: /* re-enable mmu so we can */
220 andi. r10,r10,MSR_EE /* Did EE change? */
224 * The trace_hardirqs_off will use CALLER_ADDR0 and CALLER_ADDR1.
225 * If from user mode there is only one stack frame on the stack, and
226 * accessing CALLER_ADDR1 will cause oops. So we need create a dummy
227 * stack frame to make trace_hardirqs_off happy.
229 * This is handy because we also need to save a bunch of GPRs,
230 * r3 can be different from GPR3(r1) at this point, r9 and r11
231 * contains the old MSR and handler address respectively,
232 * r4 & r5 can contain page fault arguments that need to be passed
233 * along as well. r12, CCR, CTR, XER etc... are left clobbered as
234 * they aren't useful past this point (aren't syscall arguments),
235 * the rest is restored from the exception frame.
243 bl trace_hardirqs_off
256 bctr /* jump to handler */
257 #else /* CONFIG_TRACE_IRQFLAGS */
262 RFI /* jump to handler, enable MMU */
263 #endif /* CONFIG_TRACE_IRQFLAGS */
265 #if defined (CONFIG_6xx) || defined(CONFIG_E500)
266 4: rlwinm r12,r12,0,~_TLF_NAPPING
267 stw r12,TI_LOCAL_FLAGS(r9)
268 b power_save_ppc32_restore
270 7: rlwinm r12,r12,0,~_TLF_SLEEPING
271 stw r12,TI_LOCAL_FLAGS(r9)
272 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
273 rlwinm r9,r9,0,~MSR_EE
274 lwz r12,_LINK(r11) /* and return to address in LR */
275 b fast_exception_return
279 * On kernel stack overflow, load up an initial stack pointer
280 * and call StackOverflow(regs), which should not return.
283 /* sometimes we use a statically-allocated stack, which is OK. */
287 ble 5b /* r1 <= &_end is OK */
289 addi r3,r1,STACK_FRAME_OVERHEAD
290 lis r1,init_thread_union@ha
291 addi r1,r1,init_thread_union@l
292 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
293 lis r9,StackOverflow@ha
294 addi r9,r9,StackOverflow@l
295 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
303 * Handle a system call.
305 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
306 .stabs "entry_32.S",N_SO,0,0,0f
313 lwz r11,_CCR(r1) /* Clear SO bit in CR */
316 #ifdef CONFIG_TRACE_IRQFLAGS
317 /* Return from syscalls can (and generally will) hard enable
318 * interrupts. You aren't supposed to call a syscall with
319 * interrupts disabled in the first place. However, to ensure
320 * that we get it right vs. lockdep if it happens, we force
321 * that hard enable here with appropriate tracing if we see
322 * that we have been called with interrupts off
327 /* We came in with interrupts disabled, we enable them now */
340 #endif /* CONFIG_TRACE_IRQFLAGS */
341 CURRENT_THREAD_INFO(r10, r1)
342 lwz r11,TI_FLAGS(r10)
343 andi. r11,r11,_TIF_SYSCALL_DOTRACE
345 syscall_dotrace_cont:
346 cmplwi 0,r0,NR_syscalls
347 lis r10,sys_call_table@h
348 ori r10,r10,sys_call_table@l
354 * Prevent the load of the handler below (based on the user-passed
355 * system call number) being speculatively executed until the test
356 * against NR_syscalls and branch to .66f above has
360 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
362 addi r9,r1,STACK_FRAME_OVERHEAD
364 blrl /* Call handler */
365 .globl ret_from_syscall
368 CURRENT_THREAD_INFO(r12, r1)
369 /* disable interrupts so current_thread_info()->flags can't change */
370 LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
371 /* Note: We don't bother telling lockdep about it */
376 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
377 bne- syscall_exit_work
379 blt+ syscall_exit_cont
380 lwz r11,_CCR(r1) /* Load CR */
382 oris r11,r11,0x1000 /* Set SO bit in CR */
386 #ifdef CONFIG_TRACE_IRQFLAGS
387 /* If we are going to return from the syscall with interrupts
388 * off, we trace that here. It shouldn't happen though but we
389 * want to catch the bugger if it does right ?
394 bl trace_hardirqs_off
397 #endif /* CONFIG_TRACE_IRQFLAGS */
398 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
399 /* If the process has its own DBCR0 value, load it up. The internal
400 debug mode bit tells us that dbcr0 should be loaded. */
401 lwz r0,THREAD+THREAD_DBCR0(r2)
402 andis. r10,r0,DBCR0_IDM@h
406 BEGIN_MMU_FTR_SECTION
407 lis r4,icache_44x_need_flush@ha
408 lwz r5,icache_44x_need_flush@l(r4)
412 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x)
413 #endif /* CONFIG_44x */
416 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
417 stwcx. r0,0,r1 /* to clear the reservation */
418 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
421 CURRENT_THREAD_INFO(r4, r1)
422 ACCOUNT_CPU_USER_EXIT(r4, r5, r7)
440 stw r7,icache_44x_need_flush@l(r4)
442 #endif /* CONFIG_44x */
454 .globl ret_from_kernel_thread
455 ret_from_kernel_thread:
465 /* Traced system call support */
470 addi r3,r1,STACK_FRAME_OVERHEAD
471 bl do_syscall_trace_enter
473 * Restore argument registers possibly just changed.
474 * We use the return value of do_syscall_trace_enter
475 * for call number to look up in the table (r0).
486 cmplwi r0,NR_syscalls
487 /* Return code is already in r3 thanks to do_syscall_trace_enter() */
488 bge- ret_from_syscall
489 b syscall_dotrace_cont
492 andi. r0,r9,_TIF_RESTOREALL
498 andi. r0,r9,_TIF_NOERROR
500 lwz r11,_CCR(r1) /* Load CR */
502 oris r11,r11,0x1000 /* Set SO bit in CR */
505 1: stw r6,RESULT(r1) /* Save result */
506 stw r3,GPR3(r1) /* Update return value */
507 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
510 /* Clear per-syscall TIF flags if any are set. */
512 li r11,_TIF_PERSYSCALL_MASK
513 addi r12,r12,TI_FLAGS
516 #ifdef CONFIG_IBM405_ERR77
521 subi r12,r12,TI_FLAGS
523 4: /* Anything which requires enabling interrupts? */
524 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
527 /* Re-enable interrupts. There is no need to trace that with
528 * lockdep as we are supposed to have IRQs on at this point
534 /* Save NVGPRS if they're not saved already */
542 addi r3,r1,STACK_FRAME_OVERHEAD
543 bl do_syscall_trace_leave
544 b ret_from_except_full
547 * The fork/clone functions need to copy the full register set into
548 * the child process. Therefore we need to save all the nonvolatile
549 * registers (r13 - r31) before calling the C code.
555 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
556 stw r0,_TRAP(r1) /* register set saved */
563 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
564 stw r0,_TRAP(r1) /* register set saved */
571 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
572 stw r0,_TRAP(r1) /* register set saved */
575 .globl ppc_swapcontext
579 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
580 stw r0,_TRAP(r1) /* register set saved */
584 * Top-level page fault handling.
585 * This is in assembler because if do_page_fault tells us that
586 * it is a bad kernel page fault, we want to save the non-volatile
587 * registers before calling bad_page_fault.
589 .globl handle_page_fault
592 addi r3,r1,STACK_FRAME_OVERHEAD
601 addi r3,r1,STACK_FRAME_OVERHEAD
604 b ret_from_except_full
607 * This routine switches between two different tasks. The process
608 * state of one is saved on its kernel stack. Then the state
609 * of the other is restored from its kernel stack. The memory
610 * management hardware is updated to the second process's state.
611 * Finally, we can return to the second process.
612 * On entry, r3 points to the THREAD for the current task, r4
613 * points to the THREAD for the new task.
615 * This routine is always called with interrupts disabled.
617 * Note: there are two ways to get to the "going out" portion
618 * of this code; either by coming in via the entry (_switch)
619 * or via "fork" which must set up an environment equivalent
620 * to the "_switch" path. If you change this , you'll have to
621 * change the fork code also.
623 * The code which creates the new task context is in 'copy_thread'
624 * in arch/ppc/kernel/process.c
627 stwu r1,-INT_FRAME_SIZE(r1)
629 stw r0,INT_FRAME_SIZE+4(r1)
630 /* r3-r12 are caller saved -- Cort */
632 stw r0,_NIP(r1) /* Return to switch caller */
634 li r0,MSR_FP /* Disable floating-point */
635 #ifdef CONFIG_ALTIVEC
637 oris r0,r0,MSR_VEC@h /* Disable altivec */
638 mfspr r12,SPRN_VRSAVE /* save vrsave register value */
639 stw r12,THREAD+THREAD_VRSAVE(r2)
640 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
641 #endif /* CONFIG_ALTIVEC */
644 oris r0,r0,MSR_SPE@h /* Disable SPE */
645 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
646 stw r12,THREAD+THREAD_SPEFSCR(r2)
647 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
648 #endif /* CONFIG_SPE */
649 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
657 stw r1,KSP(r3) /* Set old stack pointer */
660 /* We need a sync somewhere here to make sure that if the
661 * previous task gets rescheduled on another CPU, it sees all
662 * stores it has performed on this one.
665 #endif /* CONFIG_SMP */
668 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */
669 lwz r1,KSP(r4) /* Load new stack pointer */
671 /* save the old current 'last' for return value */
673 addi r2,r4,-THREAD /* Update current */
675 #ifdef CONFIG_ALTIVEC
677 lwz r0,THREAD+THREAD_VRSAVE(r2)
678 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
679 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
680 #endif /* CONFIG_ALTIVEC */
683 lwz r0,THREAD+THREAD_SPEFSCR(r2)
684 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
685 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
686 #endif /* CONFIG_SPE */
690 /* r3-r12 are destroyed -- Cort */
693 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
695 addi r1,r1,INT_FRAME_SIZE
698 .globl fast_exception_return
699 fast_exception_return:
700 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
701 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
702 beq 1f /* if not, we've got problems */
705 2: REST_4GPRS(3, r11)
711 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
723 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
724 /* check if the exception happened in a restartable section */
725 1: lis r3,exc_exit_restart_end@ha
726 addi r3,r3,exc_exit_restart_end@l
729 lis r4,exc_exit_restart@ha
730 addi r4,r4,exc_exit_restart@l
733 lis r3,fee_restarts@ha
735 lwz r5,fee_restarts@l(r3)
737 stw r5,fee_restarts@l(r3)
738 mr r12,r4 /* restart at exc_exit_restart */
747 /* aargh, a nonrecoverable interrupt, panic */
748 /* aargh, we don't know which trap this is */
749 /* but the 601 doesn't implement the RI bit, so assume it's OK */
753 END_FTR_SECTION_IFSET(CPU_FTR_601)
756 addi r3,r1,STACK_FRAME_OVERHEAD
758 ori r10,r10,MSR_KERNEL@l
759 bl transfer_to_handler_full
760 .long nonrecoverable_exception
761 .long ret_from_except
764 .globl ret_from_except_full
765 ret_from_except_full:
769 .globl ret_from_except
771 /* Hard-disable interrupts so that current_thread_info()->flags
772 * can't change between when we test it and when we return
773 * from the interrupt. */
774 /* Note: We don't bother telling lockdep about it */
775 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
776 SYNC /* Some chip revs have problems here... */
777 MTMSRD(r10) /* disable interrupts */
779 lwz r3,_MSR(r1) /* Returning to user mode? */
783 user_exc_return: /* r10 contains MSR_KERNEL here */
784 /* Check current_thread_info()->flags */
785 CURRENT_THREAD_INFO(r9, r1)
787 andi. r0,r9,_TIF_USER_WORK_MASK
791 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
792 /* Check whether this process has its own DBCR0 value. The internal
793 debug mode bit tells us that dbcr0 should be loaded. */
794 lwz r0,THREAD+THREAD_DBCR0(r2)
795 andis. r10,r0,DBCR0_IDM@h
798 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
799 CURRENT_THREAD_INFO(r9, r1)
800 ACCOUNT_CPU_USER_EXIT(r9, r10, r11)
805 /* N.B. the only way to get here is from the beq following ret_from_except. */
807 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
808 CURRENT_THREAD_INFO(r9, r1)
810 andis. r0,r8,_TIF_EMULATE_STACK_STORE@h
813 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
816 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
817 mr r4,r1 /* src: current exception frame */
818 mr r1,r3 /* Reroute the trampoline frame to r1 */
820 /* Copy from the original to the trampoline. */
821 li r5,INT_FRAME_SIZE/4 /* size: INT_FRAME_SIZE */
822 li r6,0 /* start offset: 0 */
829 /* Do real store operation to complete stwu */
833 /* Clear _TIF_EMULATE_STACK_STORE flag */
834 lis r11,_TIF_EMULATE_STACK_STORE@h
838 #ifdef CONFIG_IBM405_ERR77
845 #ifdef CONFIG_PREEMPT
846 /* check current_thread_info->preempt_count */
847 lwz r0,TI_PREEMPT(r9)
848 cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
850 andi. r8,r8,_TIF_NEED_RESCHED
853 andi. r0,r3,MSR_EE /* interrupts off? */
854 beq restore /* don't schedule if so */
855 #ifdef CONFIG_TRACE_IRQFLAGS
856 /* Lockdep thinks irqs are enabled, we need to call
857 * preempt_schedule_irq with IRQs off, so we inform lockdep
858 * now that we -did- turn them off already
860 bl trace_hardirqs_off
862 1: bl preempt_schedule_irq
863 CURRENT_THREAD_INFO(r9, r1)
865 andi. r0,r3,_TIF_NEED_RESCHED
867 #ifdef CONFIG_TRACE_IRQFLAGS
868 /* And now, to properly rebalance the above, we tell lockdep they
869 * are being turned back on, which will happen when we return
873 #endif /* CONFIG_PREEMPT */
875 /* interrupts are hard-disabled at this point */
878 BEGIN_MMU_FTR_SECTION
880 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
881 lis r4,icache_44x_need_flush@ha
882 lwz r5,icache_44x_need_flush@l(r4)
887 stw r6,icache_44x_need_flush@l(r4)
889 #endif /* CONFIG_44x */
892 #ifdef CONFIG_TRACE_IRQFLAGS
893 /* Lockdep doesn't know about the fact that IRQs are temporarily turned
894 * off in this assembly code while peeking at TI_FLAGS() and such. However
895 * we need to inform it if the exception turned interrupts off, and we
896 * are about to trun them back on.
898 * The problem here sadly is that we don't know whether the exceptions was
899 * one that turned interrupts off or not. So we always tell lockdep about
900 * turning them on here when we go back to wherever we came from with EE
901 * on, even if that may meen some redudant calls being tracked. Maybe later
902 * we could encode what the exception did somewhere or test the exception
903 * type in the pt_regs but that sounds overkill
908 * Since the ftrace irqsoff latency trace checks CALLER_ADDR1,
909 * which is the stack frame here, we need to force a stack frame
910 * in case we came from user space.
921 #endif /* CONFIG_TRACE_IRQFLAGS */
936 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
937 stwcx. r0,0,r1 /* to clear the reservation */
939 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
940 andi. r10,r9,MSR_RI /* check if this exception occurred */
941 beql nonrecoverable /* at a bad place (MSR:RI = 0) */
948 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
952 * Once we put values in SRR0 and SRR1, we are in a state
953 * where exceptions are not recoverable, since taking an
954 * exception will trash SRR0 and SRR1. Therefore we clear the
955 * MSR:RI bit to indicate this. If we do take an exception,
956 * we can't return to the point of the exception but we
957 * can restart the exception exit path at the label
958 * exc_exit_restart below. -- paulus
960 LOAD_MSR_KERNEL(r10,MSR_KERNEL & ~MSR_RI)
962 MTMSRD(r10) /* clear the RI bit */
963 .globl exc_exit_restart
971 .globl exc_exit_restart_end
972 exc_exit_restart_end:
976 #else /* !(CONFIG_4xx || CONFIG_BOOKE) */
978 * This is a bit different on 4xx/Book-E because it doesn't have
979 * the RI bit in the MSR.
980 * The TLB miss handler checks if we have interrupted
981 * the exception exit path and restarts it if so
982 * (well maybe one day it will... :).
988 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
992 .globl exc_exit_restart
1001 .globl exc_exit_restart_end
1002 exc_exit_restart_end:
1005 b . /* prevent prefetch past rfi */
1008 * Returning from a critical interrupt in user mode doesn't need
1009 * to be any different from a normal exception. For a critical
1010 * interrupt in the kernel, we just return (without checking for
1011 * preemption) since the interrupt may have happened at some crucial
1012 * place (e.g. inside the TLB miss handler), and because we will be
1013 * running with r1 pointing into critical_stack, not the current
1014 * process's kernel stack (and therefore current_thread_info() will
1015 * give the wrong answer).
1016 * We have to restore various SPRs that may have been in use at the
1017 * time of the critical interrupt.
1021 #define PPC_40x_TURN_OFF_MSR_DR \
1022 /* avoid any possible TLB misses here by turning off MSR.DR, we \
1023 * assume the instructions here are mapped by a pinned TLB entry */ \
1029 #define PPC_40x_TURN_OFF_MSR_DR
1032 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
1035 andi. r3,r3,MSR_PR; \
1036 LOAD_MSR_KERNEL(r10,MSR_KERNEL); \
1037 bne user_exc_return; \
1040 REST_4GPRS(3, r1); \
1041 REST_2GPRS(7, r1); \
1044 mtspr SPRN_XER,r10; \
1046 PPC405_ERR77(0,r1); \
1047 stwcx. r0,0,r1; /* to clear the reservation */ \
1048 lwz r11,_LINK(r1); \
1052 PPC_40x_TURN_OFF_MSR_DR; \
1055 mtspr SPRN_DEAR,r9; \
1056 mtspr SPRN_ESR,r10; \
1059 mtspr exc_lvl_srr0,r11; \
1060 mtspr exc_lvl_srr1,r12; \
1062 lwz r12,GPR12(r1); \
1063 lwz r10,GPR10(r1); \
1064 lwz r11,GPR11(r1); \
1066 PPC405_ERR77_SYNC; \
1068 b .; /* prevent prefetch past exc_lvl_rfi */
1070 #define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \
1071 lwz r9,_##exc_lvl_srr0(r1); \
1072 lwz r10,_##exc_lvl_srr1(r1); \
1073 mtspr SPRN_##exc_lvl_srr0,r9; \
1074 mtspr SPRN_##exc_lvl_srr1,r10;
1076 #if defined(CONFIG_PPC_BOOK3E_MMU)
1077 #ifdef CONFIG_PHYS_64BIT
1078 #define RESTORE_MAS7 \
1080 mtspr SPRN_MAS7,r11;
1082 #define RESTORE_MAS7
1083 #endif /* CONFIG_PHYS_64BIT */
1084 #define RESTORE_MMU_REGS \
1088 mtspr SPRN_MAS0,r9; \
1090 mtspr SPRN_MAS1,r10; \
1092 mtspr SPRN_MAS2,r11; \
1093 mtspr SPRN_MAS3,r9; \
1094 mtspr SPRN_MAS6,r10; \
1096 #elif defined(CONFIG_44x)
1097 #define RESTORE_MMU_REGS \
1099 mtspr SPRN_MMUCR,r9;
1101 #define RESTORE_MMU_REGS
1105 .globl ret_from_crit_exc
1107 mfspr r9,SPRN_SPRG_THREAD
1108 lis r10,saved_ksp_limit@ha;
1109 lwz r10,saved_ksp_limit@l(r10);
1111 stw r10,KSP_LIMIT(r9)
1112 lis r9,crit_srr0@ha;
1113 lwz r9,crit_srr0@l(r9);
1114 lis r10,crit_srr1@ha;
1115 lwz r10,crit_srr1@l(r10);
1117 mtspr SPRN_SRR1,r10;
1118 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1119 #endif /* CONFIG_40x */
1122 .globl ret_from_crit_exc
1124 mfspr r9,SPRN_SPRG_THREAD
1125 lwz r10,SAVED_KSP_LIMIT(r1)
1126 stw r10,KSP_LIMIT(r9)
1127 RESTORE_xSRR(SRR0,SRR1);
1129 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1131 .globl ret_from_debug_exc
1133 mfspr r9,SPRN_SPRG_THREAD
1134 lwz r10,SAVED_KSP_LIMIT(r1)
1135 stw r10,KSP_LIMIT(r9)
1136 lwz r9,THREAD_INFO-THREAD(r9)
1137 CURRENT_THREAD_INFO(r10, r1)
1138 lwz r10,TI_PREEMPT(r10)
1139 stw r10,TI_PREEMPT(r9)
1140 RESTORE_xSRR(SRR0,SRR1);
1141 RESTORE_xSRR(CSRR0,CSRR1);
1143 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
1145 .globl ret_from_mcheck_exc
1146 ret_from_mcheck_exc:
1147 mfspr r9,SPRN_SPRG_THREAD
1148 lwz r10,SAVED_KSP_LIMIT(r1)
1149 stw r10,KSP_LIMIT(r9)
1150 RESTORE_xSRR(SRR0,SRR1);
1151 RESTORE_xSRR(CSRR0,CSRR1);
1152 RESTORE_xSRR(DSRR0,DSRR1);
1154 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
1155 #endif /* CONFIG_BOOKE */
1158 * Load the DBCR0 value for a task that is being ptraced,
1159 * having first saved away the global DBCR0. Note that r0
1160 * has the dbcr0 value to set upon entry to this.
1163 mfmsr r10 /* first disable debug exceptions */
1164 rlwinm r10,r10,0,~MSR_DE
1167 mfspr r10,SPRN_DBCR0
1168 lis r11,global_dbcr0@ha
1169 addi r11,r11,global_dbcr0@l
1171 CURRENT_THREAD_INFO(r9, r1)
1182 mtspr SPRN_DBSR,r11 /* clear all pending debug events */
1190 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
1192 do_work: /* r10 contains MSR_KERNEL here */
1193 andi. r0,r9,_TIF_NEED_RESCHED
1196 do_resched: /* r10 contains MSR_KERNEL here */
1197 /* Note: We don't need to inform lockdep that we are enabling
1198 * interrupts here. As far as it knows, they are already enabled
1202 MTMSRD(r10) /* hard-enable interrupts */
1205 /* Note: And we don't tell it we are disabling them again
1206 * neither. Those disable/enable cycles used to peek at
1207 * TI_FLAGS aren't advertised.
1209 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
1211 MTMSRD(r10) /* disable interrupts */
1212 CURRENT_THREAD_INFO(r9, r1)
1214 andi. r0,r9,_TIF_NEED_RESCHED
1216 andi. r0,r9,_TIF_USER_WORK_MASK
1218 do_user_signal: /* r10 contains MSR_KERNEL here */
1221 MTMSRD(r10) /* hard-enable interrupts */
1222 /* save r13-r31 in the exception frame, if not already done */
1229 2: addi r3,r1,STACK_FRAME_OVERHEAD
1236 * We come here when we are at the end of handling an exception
1237 * that occurred at a place where taking an exception will lose
1238 * state information, such as the contents of SRR0 and SRR1.
1241 lis r10,exc_exit_restart_end@ha
1242 addi r10,r10,exc_exit_restart_end@l
1245 lis r11,exc_exit_restart@ha
1246 addi r11,r11,exc_exit_restart@l
1249 lis r10,ee_restarts@ha
1250 lwz r12,ee_restarts@l(r10)
1252 stw r12,ee_restarts@l(r10)
1253 mr r12,r11 /* restart at exc_exit_restart */
1255 3: /* OK, we can't recover, kill this process */
1256 /* but the 601 doesn't implement the RI bit, so assume it's OK */
1259 END_FTR_SECTION_IFSET(CPU_FTR_601)
1266 4: addi r3,r1,STACK_FRAME_OVERHEAD
1267 bl nonrecoverable_exception
1268 /* shouldn't return */
1278 * PROM code for specific machines follows. Put it
1279 * here so it's easy to add arch-specific sections later.
1282 #ifdef CONFIG_PPC_RTAS
1284 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1285 * called with the MMU off.
1288 stwu r1,-INT_FRAME_SIZE(r1)
1290 stw r0,INT_FRAME_SIZE+4(r1)
1291 LOAD_REG_ADDR(r4, rtas)
1292 lis r6,1f@ha /* physical return address for rtas */
1296 lwz r8,RTASENTRY(r4)
1300 LOAD_MSR_KERNEL(r0,MSR_KERNEL)
1301 SYNC /* disable interrupts so SRR0/1 */
1302 MTMSRD(r0) /* don't get trashed */
1303 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1305 mtspr SPRN_SPRG_RTAS,r7
1310 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
1311 lwz r9,8(r9) /* original msr value */
1313 addi r1,r1,INT_FRAME_SIZE
1315 mtspr SPRN_SPRG_RTAS,r0
1318 RFI /* return to caller */
1320 .globl machine_check_in_rtas
1321 machine_check_in_rtas:
1323 /* XXX load up BATs and panic */
1325 #endif /* CONFIG_PPC_RTAS */
1327 #ifdef CONFIG_FUNCTION_TRACER
1328 #ifdef CONFIG_DYNAMIC_FTRACE
1332 * It is required that _mcount on PPC32 must preserve the
1333 * link register. But we have r0 to play with. We use r0
1334 * to push the return address back to the caller of mcount
1335 * into the ctr register, restore the link register and
1336 * then jump back using the ctr register.
1344 _GLOBAL(ftrace_caller)
1346 /* r3 ends up with link register */
1347 subi r3, r3, MCOUNT_INSN_SIZE
1352 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1353 .globl ftrace_graph_call
1356 _GLOBAL(ftrace_graph_stub)
1358 MCOUNT_RESTORE_FRAME
1359 /* old link register ends up in ctr reg */
1367 subi r3, r3, MCOUNT_INSN_SIZE
1368 LOAD_REG_ADDR(r5, ftrace_trace_function)
1375 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1376 b ftrace_graph_caller
1378 MCOUNT_RESTORE_FRAME
1381 EXPORT_SYMBOL(_mcount)
1383 _GLOBAL(ftrace_stub)
1386 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1387 _GLOBAL(ftrace_graph_caller)
1388 /* load r4 with local address */
1390 subi r4, r4, MCOUNT_INSN_SIZE
1392 /* Grab the LR out of the caller stack frame */
1395 bl prepare_ftrace_return
1399 * prepare_ftrace_return gives us the address we divert to.
1400 * Change the LR in the callers stack frame to this.
1404 MCOUNT_RESTORE_FRAME
1405 /* old link register ends up in ctr reg */
1408 _GLOBAL(return_to_handler)
1409 /* need to save return values */
1416 bl ftrace_return_to_handler
1419 /* return value has real return address */
1427 /* Jump back to real return address */
1429 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1431 #endif /* CONFIG_FUNCTION_TRACER */