3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/errno.h>
23 #include <linux/err.h>
24 #include <linux/sys.h>
25 #include <linux/threads.h>
29 #include <asm/cputable.h>
30 #include <asm/thread_info.h>
31 #include <asm/ppc_asm.h>
32 #include <asm/asm-offsets.h>
33 #include <asm/unistd.h>
34 #include <asm/ptrace.h>
35 #include <asm/export.h>
36 #include <asm/barrier.h>
39 * MSR_KERNEL is > 0x10000 on 4xx/Book-E since it include MSR_CE.
41 #if MSR_KERNEL >= 0x10000
42 #define LOAD_MSR_KERNEL(r, x) lis r,(x)@h; ori r,r,(x)@l
44 #define LOAD_MSR_KERNEL(r, x) li r,(x)
48 * Align to 4k in order to ensure that all functions modyfing srr0/srr1
49 * fit into one page in order to not encounter a TLB miss between the
50 * modification of srr0/srr1 and the associated rfi.
55 .globl mcheck_transfer_to_handler
56 mcheck_transfer_to_handler:
63 .globl debug_transfer_to_handler
64 debug_transfer_to_handler:
71 .globl crit_transfer_to_handler
72 crit_transfer_to_handler:
73 #ifdef CONFIG_PPC_BOOK3E_MMU
84 #ifdef CONFIG_PHYS_64BIT
87 #endif /* CONFIG_PHYS_64BIT */
88 #endif /* CONFIG_PPC_BOOK3E_MMU */
98 /* set the stack limit to the current stack
99 * and set the limit to protect the thread_info
102 mfspr r8,SPRN_SPRG_THREAD
104 stw r0,SAVED_KSP_LIMIT(r11)
105 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
111 .globl crit_transfer_to_handler
112 crit_transfer_to_handler:
118 stw r0,crit_srr0@l(0)
120 stw r0,crit_srr1@l(0)
122 /* set the stack limit to the current stack
123 * and set the limit to protect the thread_info
126 mfspr r8,SPRN_SPRG_THREAD
128 stw r0,saved_ksp_limit@l(0)
129 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
135 * This code finishes saving the registers to the exception frame
136 * and jumps to the appropriate handler for the exception, turning
137 * on address translation.
138 * Note that we rely on the caller having set cr0.eq iff the exception
139 * occurred in kernel mode (i.e. MSR:PR = 0).
141 .globl transfer_to_handler_full
142 transfer_to_handler_full:
146 .globl transfer_to_handler
156 mfspr r12,SPRN_SPRG_THREAD
158 tovirt(r2,r2) /* set r2 to current */
159 beq 2f /* if from user, fix up THREAD.regs */
160 addi r11,r1,STACK_FRAME_OVERHEAD
162 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
163 /* Check to see if the dbcr0 register is set up to debug. Use the
164 internal debug mode bit to do this. */
165 lwz r12,THREAD_DBCR0(r12)
166 andis. r12,r12,DBCR0_IDM@h
168 /* From user and task is ptraced - load up global dbcr0 */
169 li r12,-1 /* clear all pending debug events */
171 lis r11,global_dbcr0@ha
173 addi r11,r11,global_dbcr0@l
175 CURRENT_THREAD_INFO(r9, r1)
186 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
187 CURRENT_THREAD_INFO(r9, r1)
189 ACCOUNT_CPU_USER_ENTRY(r9, r11, r12)
194 2: /* if from kernel, check interrupted DOZE/NAP mode and
195 * check for stack overflow
197 lwz r9,KSP_LIMIT(r12)
198 cmplw r1,r9 /* if r1 <= ksp_limit */
199 ble- stack_ovf /* then the kernel stack overflowed */
201 #if defined(CONFIG_6xx) || defined(CONFIG_E500)
202 CURRENT_THREAD_INFO(r9, r1)
203 tophys(r9,r9) /* check local flags */
204 lwz r12,TI_LOCAL_FLAGS(r9)
206 bt- 31-TLF_NAPPING,4f
207 bt- 31-TLF_SLEEPING,7f
208 #endif /* CONFIG_6xx || CONFIG_E500 */
209 .globl transfer_to_handler_cont
210 transfer_to_handler_cont:
213 lwz r11,0(r9) /* virtual address of handler */
214 lwz r9,4(r9) /* where to go when done */
215 #ifdef CONFIG_PPC_8xx_PERF_EVENT
218 #ifdef CONFIG_TRACE_IRQFLAGS
219 lis r12,reenable_mmu@h
220 ori r12,r12,reenable_mmu@l
225 reenable_mmu: /* re-enable mmu so we can */
229 andi. r10,r10,MSR_EE /* Did EE change? */
233 * The trace_hardirqs_off will use CALLER_ADDR0 and CALLER_ADDR1.
234 * If from user mode there is only one stack frame on the stack, and
235 * accessing CALLER_ADDR1 will cause oops. So we need create a dummy
236 * stack frame to make trace_hardirqs_off happy.
238 * This is handy because we also need to save a bunch of GPRs,
239 * r3 can be different from GPR3(r1) at this point, r9 and r11
240 * contains the old MSR and handler address respectively,
241 * r4 & r5 can contain page fault arguments that need to be passed
242 * along as well. r12, CCR, CTR, XER etc... are left clobbered as
243 * they aren't useful past this point (aren't syscall arguments),
244 * the rest is restored from the exception frame.
252 bl trace_hardirqs_off
265 bctr /* jump to handler */
266 #else /* CONFIG_TRACE_IRQFLAGS */
271 RFI /* jump to handler, enable MMU */
272 #endif /* CONFIG_TRACE_IRQFLAGS */
274 #if defined (CONFIG_6xx) || defined(CONFIG_E500)
275 4: rlwinm r12,r12,0,~_TLF_NAPPING
276 stw r12,TI_LOCAL_FLAGS(r9)
277 b power_save_ppc32_restore
279 7: rlwinm r12,r12,0,~_TLF_SLEEPING
280 stw r12,TI_LOCAL_FLAGS(r9)
281 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
282 rlwinm r9,r9,0,~MSR_EE
283 lwz r12,_LINK(r11) /* and return to address in LR */
284 b fast_exception_return
288 * On kernel stack overflow, load up an initial stack pointer
289 * and call StackOverflow(regs), which should not return.
292 /* sometimes we use a statically-allocated stack, which is OK. */
296 ble 5b /* r1 <= &_end is OK */
298 addi r3,r1,STACK_FRAME_OVERHEAD
299 lis r1,init_thread_union@ha
300 addi r1,r1,init_thread_union@l
301 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
302 lis r9,StackOverflow@ha
303 addi r9,r9,StackOverflow@l
304 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
305 #ifdef CONFIG_PPC_8xx_PERF_EVENT
314 * Handle a system call.
316 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
317 .stabs "entry_32.S",N_SO,0,0,0f
324 lwz r11,_CCR(r1) /* Clear SO bit in CR */
327 #ifdef CONFIG_TRACE_IRQFLAGS
328 /* Return from syscalls can (and generally will) hard enable
329 * interrupts. You aren't supposed to call a syscall with
330 * interrupts disabled in the first place. However, to ensure
331 * that we get it right vs. lockdep if it happens, we force
332 * that hard enable here with appropriate tracing if we see
333 * that we have been called with interrupts off
338 /* We came in with interrupts disabled, we enable them now */
351 #endif /* CONFIG_TRACE_IRQFLAGS */
352 CURRENT_THREAD_INFO(r10, r1)
353 lwz r11,TI_FLAGS(r10)
354 andi. r11,r11,_TIF_SYSCALL_DOTRACE
356 syscall_dotrace_cont:
357 cmplwi 0,r0,NR_syscalls
358 lis r10,sys_call_table@h
359 ori r10,r10,sys_call_table@l
365 * Prevent the load of the handler below (based on the user-passed
366 * system call number) being speculatively executed until the test
367 * against NR_syscalls and branch to .66f above has
371 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
373 addi r9,r1,STACK_FRAME_OVERHEAD
375 blrl /* Call handler */
376 .globl ret_from_syscall
379 CURRENT_THREAD_INFO(r12, r1)
380 /* disable interrupts so current_thread_info()->flags can't change */
381 LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
382 /* Note: We don't bother telling lockdep about it */
387 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
388 bne- syscall_exit_work
390 blt+ syscall_exit_cont
391 lwz r11,_CCR(r1) /* Load CR */
393 oris r11,r11,0x1000 /* Set SO bit in CR */
397 #ifdef CONFIG_TRACE_IRQFLAGS
398 /* If we are going to return from the syscall with interrupts
399 * off, we trace that here. It shouldn't happen though but we
400 * want to catch the bugger if it does right ?
405 bl trace_hardirqs_off
408 #endif /* CONFIG_TRACE_IRQFLAGS */
409 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
410 /* If the process has its own DBCR0 value, load it up. The internal
411 debug mode bit tells us that dbcr0 should be loaded. */
412 lwz r0,THREAD+THREAD_DBCR0(r2)
413 andis. r10,r0,DBCR0_IDM@h
417 BEGIN_MMU_FTR_SECTION
418 lis r4,icache_44x_need_flush@ha
419 lwz r5,icache_44x_need_flush@l(r4)
423 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x)
424 #endif /* CONFIG_44x */
427 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
428 stwcx. r0,0,r1 /* to clear the reservation */
429 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
432 CURRENT_THREAD_INFO(r4, r1)
433 ACCOUNT_CPU_USER_EXIT(r4, r5, r7)
443 #ifdef CONFIG_PPC_8xx_PERF_EVENT
453 stw r7,icache_44x_need_flush@l(r4)
455 #endif /* CONFIG_44x */
467 .globl ret_from_kernel_thread
468 ret_from_kernel_thread:
478 /* Traced system call support */
483 addi r3,r1,STACK_FRAME_OVERHEAD
484 bl do_syscall_trace_enter
486 * Restore argument registers possibly just changed.
487 * We use the return value of do_syscall_trace_enter
488 * for call number to look up in the table (r0).
499 cmplwi r0,NR_syscalls
500 /* Return code is already in r3 thanks to do_syscall_trace_enter() */
501 bge- ret_from_syscall
502 b syscall_dotrace_cont
505 andi. r0,r9,_TIF_RESTOREALL
511 andi. r0,r9,_TIF_NOERROR
513 lwz r11,_CCR(r1) /* Load CR */
515 oris r11,r11,0x1000 /* Set SO bit in CR */
518 1: stw r6,RESULT(r1) /* Save result */
519 stw r3,GPR3(r1) /* Update return value */
520 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
523 /* Clear per-syscall TIF flags if any are set. */
525 li r11,_TIF_PERSYSCALL_MASK
526 addi r12,r12,TI_FLAGS
529 #ifdef CONFIG_IBM405_ERR77
534 subi r12,r12,TI_FLAGS
536 4: /* Anything which requires enabling interrupts? */
537 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
540 /* Re-enable interrupts. There is no need to trace that with
541 * lockdep as we are supposed to have IRQs on at this point
547 /* Save NVGPRS if they're not saved already */
555 addi r3,r1,STACK_FRAME_OVERHEAD
556 bl do_syscall_trace_leave
557 b ret_from_except_full
560 * The fork/clone functions need to copy the full register set into
561 * the child process. Therefore we need to save all the nonvolatile
562 * registers (r13 - r31) before calling the C code.
568 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
569 stw r0,_TRAP(r1) /* register set saved */
576 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
577 stw r0,_TRAP(r1) /* register set saved */
584 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
585 stw r0,_TRAP(r1) /* register set saved */
588 .globl ppc_swapcontext
592 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
593 stw r0,_TRAP(r1) /* register set saved */
597 * Top-level page fault handling.
598 * This is in assembler because if do_page_fault tells us that
599 * it is a bad kernel page fault, we want to save the non-volatile
600 * registers before calling bad_page_fault.
602 .globl handle_page_fault
605 addi r3,r1,STACK_FRAME_OVERHEAD
607 andis. r0,r5,DSISR_DABRMATCH@h
608 bne- handle_dabr_fault
618 addi r3,r1,STACK_FRAME_OVERHEAD
621 b ret_from_except_full
624 /* We have a data breakpoint exception - handle it */
631 b ret_from_except_full
635 * This routine switches between two different tasks. The process
636 * state of one is saved on its kernel stack. Then the state
637 * of the other is restored from its kernel stack. The memory
638 * management hardware is updated to the second process's state.
639 * Finally, we can return to the second process.
640 * On entry, r3 points to the THREAD for the current task, r4
641 * points to the THREAD for the new task.
643 * This routine is always called with interrupts disabled.
645 * Note: there are two ways to get to the "going out" portion
646 * of this code; either by coming in via the entry (_switch)
647 * or via "fork" which must set up an environment equivalent
648 * to the "_switch" path. If you change this , you'll have to
649 * change the fork code also.
651 * The code which creates the new task context is in 'copy_thread'
652 * in arch/ppc/kernel/process.c
655 stwu r1,-INT_FRAME_SIZE(r1)
657 stw r0,INT_FRAME_SIZE+4(r1)
658 /* r3-r12 are caller saved -- Cort */
660 stw r0,_NIP(r1) /* Return to switch caller */
662 li r0,MSR_FP /* Disable floating-point */
663 #ifdef CONFIG_ALTIVEC
665 oris r0,r0,MSR_VEC@h /* Disable altivec */
666 mfspr r12,SPRN_VRSAVE /* save vrsave register value */
667 stw r12,THREAD+THREAD_VRSAVE(r2)
668 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
669 #endif /* CONFIG_ALTIVEC */
672 oris r0,r0,MSR_SPE@h /* Disable SPE */
673 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
674 stw r12,THREAD+THREAD_SPEFSCR(r2)
675 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
676 #endif /* CONFIG_SPE */
677 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
685 stw r1,KSP(r3) /* Set old stack pointer */
688 /* We need a sync somewhere here to make sure that if the
689 * previous task gets rescheduled on another CPU, it sees all
690 * stores it has performed on this one.
693 #endif /* CONFIG_SMP */
696 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */
697 lwz r1,KSP(r4) /* Load new stack pointer */
699 /* save the old current 'last' for return value */
701 addi r2,r4,-THREAD /* Update current */
703 #ifdef CONFIG_ALTIVEC
705 lwz r0,THREAD+THREAD_VRSAVE(r2)
706 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
707 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
708 #endif /* CONFIG_ALTIVEC */
711 lwz r0,THREAD+THREAD_SPEFSCR(r2)
712 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
713 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
714 #endif /* CONFIG_SPE */
718 /* r3-r12 are destroyed -- Cort */
721 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
723 addi r1,r1,INT_FRAME_SIZE
726 .globl fast_exception_return
727 fast_exception_return:
728 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
729 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
730 beq 1f /* if not, we've got problems */
733 2: REST_4GPRS(3, r11)
739 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
743 #ifdef CONFIG_PPC_8xx_PERF_EVENT
754 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
755 /* check if the exception happened in a restartable section */
756 1: lis r3,exc_exit_restart_end@ha
757 addi r3,r3,exc_exit_restart_end@l
760 lis r4,exc_exit_restart@ha
761 addi r4,r4,exc_exit_restart@l
764 lis r3,fee_restarts@ha
766 lwz r5,fee_restarts@l(r3)
768 stw r5,fee_restarts@l(r3)
769 mr r12,r4 /* restart at exc_exit_restart */
778 /* aargh, a nonrecoverable interrupt, panic */
779 /* aargh, we don't know which trap this is */
780 /* but the 601 doesn't implement the RI bit, so assume it's OK */
784 END_FTR_SECTION_IFSET(CPU_FTR_601)
787 addi r3,r1,STACK_FRAME_OVERHEAD
789 ori r10,r10,MSR_KERNEL@l
790 bl transfer_to_handler_full
791 .long nonrecoverable_exception
792 .long ret_from_except
795 .globl ret_from_except_full
796 ret_from_except_full:
800 .globl ret_from_except
802 /* Hard-disable interrupts so that current_thread_info()->flags
803 * can't change between when we test it and when we return
804 * from the interrupt. */
805 /* Note: We don't bother telling lockdep about it */
806 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
807 SYNC /* Some chip revs have problems here... */
808 MTMSRD(r10) /* disable interrupts */
810 lwz r3,_MSR(r1) /* Returning to user mode? */
814 user_exc_return: /* r10 contains MSR_KERNEL here */
815 /* Check current_thread_info()->flags */
816 CURRENT_THREAD_INFO(r9, r1)
818 andi. r0,r9,_TIF_USER_WORK_MASK
822 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
823 /* Check whether this process has its own DBCR0 value. The internal
824 debug mode bit tells us that dbcr0 should be loaded. */
825 lwz r0,THREAD+THREAD_DBCR0(r2)
826 andis. r10,r0,DBCR0_IDM@h
829 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
830 CURRENT_THREAD_INFO(r9, r1)
831 ACCOUNT_CPU_USER_EXIT(r9, r10, r11)
836 /* N.B. the only way to get here is from the beq following ret_from_except. */
838 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
839 CURRENT_THREAD_INFO(r9, r1)
841 andis. r0,r8,_TIF_EMULATE_STACK_STORE@h
844 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
847 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
848 mr r4,r1 /* src: current exception frame */
849 mr r1,r3 /* Reroute the trampoline frame to r1 */
851 /* Copy from the original to the trampoline. */
852 li r5,INT_FRAME_SIZE/4 /* size: INT_FRAME_SIZE */
853 li r6,0 /* start offset: 0 */
860 /* Do real store operation to complete stwu */
864 /* Clear _TIF_EMULATE_STACK_STORE flag */
865 lis r11,_TIF_EMULATE_STACK_STORE@h
869 #ifdef CONFIG_IBM405_ERR77
876 #ifdef CONFIG_PREEMPT
877 /* check current_thread_info->preempt_count */
878 lwz r0,TI_PREEMPT(r9)
879 cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
881 andi. r8,r8,_TIF_NEED_RESCHED
884 andi. r0,r3,MSR_EE /* interrupts off? */
885 beq restore /* don't schedule if so */
886 #ifdef CONFIG_TRACE_IRQFLAGS
887 /* Lockdep thinks irqs are enabled, we need to call
888 * preempt_schedule_irq with IRQs off, so we inform lockdep
889 * now that we -did- turn them off already
891 bl trace_hardirqs_off
893 1: bl preempt_schedule_irq
894 CURRENT_THREAD_INFO(r9, r1)
896 andi. r0,r3,_TIF_NEED_RESCHED
898 #ifdef CONFIG_TRACE_IRQFLAGS
899 /* And now, to properly rebalance the above, we tell lockdep they
900 * are being turned back on, which will happen when we return
904 #endif /* CONFIG_PREEMPT */
906 /* interrupts are hard-disabled at this point */
909 BEGIN_MMU_FTR_SECTION
911 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
912 lis r4,icache_44x_need_flush@ha
913 lwz r5,icache_44x_need_flush@l(r4)
918 stw r6,icache_44x_need_flush@l(r4)
920 #endif /* CONFIG_44x */
923 #ifdef CONFIG_TRACE_IRQFLAGS
924 /* Lockdep doesn't know about the fact that IRQs are temporarily turned
925 * off in this assembly code while peeking at TI_FLAGS() and such. However
926 * we need to inform it if the exception turned interrupts off, and we
927 * are about to trun them back on.
929 * The problem here sadly is that we don't know whether the exceptions was
930 * one that turned interrupts off or not. So we always tell lockdep about
931 * turning them on here when we go back to wherever we came from with EE
932 * on, even if that may meen some redudant calls being tracked. Maybe later
933 * we could encode what the exception did somewhere or test the exception
934 * type in the pt_regs but that sounds overkill
939 * Since the ftrace irqsoff latency trace checks CALLER_ADDR1,
940 * which is the stack frame here, we need to force a stack frame
941 * in case we came from user space.
952 #endif /* CONFIG_TRACE_IRQFLAGS */
967 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
968 stwcx. r0,0,r1 /* to clear the reservation */
970 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
971 andi. r10,r9,MSR_RI /* check if this exception occurred */
972 beql nonrecoverable /* at a bad place (MSR:RI = 0) */
979 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
983 * Once we put values in SRR0 and SRR1, we are in a state
984 * where exceptions are not recoverable, since taking an
985 * exception will trash SRR0 and SRR1. Therefore we clear the
986 * MSR:RI bit to indicate this. If we do take an exception,
987 * we can't return to the point of the exception but we
988 * can restart the exception exit path at the label
989 * exc_exit_restart below. -- paulus
991 LOAD_MSR_KERNEL(r10,MSR_KERNEL & ~MSR_RI)
993 MTMSRD(r10) /* clear the RI bit */
994 .globl exc_exit_restart
997 #ifdef CONFIG_PPC_8xx_PERF_EVENT
1004 .globl exc_exit_restart_end
1005 exc_exit_restart_end:
1009 #else /* !(CONFIG_4xx || CONFIG_BOOKE) */
1011 * This is a bit different on 4xx/Book-E because it doesn't have
1012 * the RI bit in the MSR.
1013 * The TLB miss handler checks if we have interrupted
1014 * the exception exit path and restarts it if so
1015 * (well maybe one day it will... :).
1021 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
1025 .globl exc_exit_restart
1034 .globl exc_exit_restart_end
1035 exc_exit_restart_end:
1038 b . /* prevent prefetch past rfi */
1041 * Returning from a critical interrupt in user mode doesn't need
1042 * to be any different from a normal exception. For a critical
1043 * interrupt in the kernel, we just return (without checking for
1044 * preemption) since the interrupt may have happened at some crucial
1045 * place (e.g. inside the TLB miss handler), and because we will be
1046 * running with r1 pointing into critical_stack, not the current
1047 * process's kernel stack (and therefore current_thread_info() will
1048 * give the wrong answer).
1049 * We have to restore various SPRs that may have been in use at the
1050 * time of the critical interrupt.
1054 #define PPC_40x_TURN_OFF_MSR_DR \
1055 /* avoid any possible TLB misses here by turning off MSR.DR, we \
1056 * assume the instructions here are mapped by a pinned TLB entry */ \
1062 #define PPC_40x_TURN_OFF_MSR_DR
1065 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
1068 andi. r3,r3,MSR_PR; \
1069 LOAD_MSR_KERNEL(r10,MSR_KERNEL); \
1070 bne user_exc_return; \
1073 REST_4GPRS(3, r1); \
1074 REST_2GPRS(7, r1); \
1077 mtspr SPRN_XER,r10; \
1079 PPC405_ERR77(0,r1); \
1080 stwcx. r0,0,r1; /* to clear the reservation */ \
1081 lwz r11,_LINK(r1); \
1085 PPC_40x_TURN_OFF_MSR_DR; \
1088 mtspr SPRN_DEAR,r9; \
1089 mtspr SPRN_ESR,r10; \
1092 mtspr exc_lvl_srr0,r11; \
1093 mtspr exc_lvl_srr1,r12; \
1095 lwz r12,GPR12(r1); \
1096 lwz r10,GPR10(r1); \
1097 lwz r11,GPR11(r1); \
1099 PPC405_ERR77_SYNC; \
1101 b .; /* prevent prefetch past exc_lvl_rfi */
1103 #define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \
1104 lwz r9,_##exc_lvl_srr0(r1); \
1105 lwz r10,_##exc_lvl_srr1(r1); \
1106 mtspr SPRN_##exc_lvl_srr0,r9; \
1107 mtspr SPRN_##exc_lvl_srr1,r10;
1109 #if defined(CONFIG_PPC_BOOK3E_MMU)
1110 #ifdef CONFIG_PHYS_64BIT
1111 #define RESTORE_MAS7 \
1113 mtspr SPRN_MAS7,r11;
1115 #define RESTORE_MAS7
1116 #endif /* CONFIG_PHYS_64BIT */
1117 #define RESTORE_MMU_REGS \
1121 mtspr SPRN_MAS0,r9; \
1123 mtspr SPRN_MAS1,r10; \
1125 mtspr SPRN_MAS2,r11; \
1126 mtspr SPRN_MAS3,r9; \
1127 mtspr SPRN_MAS6,r10; \
1129 #elif defined(CONFIG_44x)
1130 #define RESTORE_MMU_REGS \
1132 mtspr SPRN_MMUCR,r9;
1134 #define RESTORE_MMU_REGS
1138 .globl ret_from_crit_exc
1140 mfspr r9,SPRN_SPRG_THREAD
1141 lis r10,saved_ksp_limit@ha;
1142 lwz r10,saved_ksp_limit@l(r10);
1144 stw r10,KSP_LIMIT(r9)
1145 lis r9,crit_srr0@ha;
1146 lwz r9,crit_srr0@l(r9);
1147 lis r10,crit_srr1@ha;
1148 lwz r10,crit_srr1@l(r10);
1150 mtspr SPRN_SRR1,r10;
1151 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1152 #endif /* CONFIG_40x */
1155 .globl ret_from_crit_exc
1157 mfspr r9,SPRN_SPRG_THREAD
1158 lwz r10,SAVED_KSP_LIMIT(r1)
1159 stw r10,KSP_LIMIT(r9)
1160 RESTORE_xSRR(SRR0,SRR1);
1162 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1164 .globl ret_from_debug_exc
1166 mfspr r9,SPRN_SPRG_THREAD
1167 lwz r10,SAVED_KSP_LIMIT(r1)
1168 stw r10,KSP_LIMIT(r9)
1169 lwz r9,THREAD_INFO-THREAD(r9)
1170 CURRENT_THREAD_INFO(r10, r1)
1171 lwz r10,TI_PREEMPT(r10)
1172 stw r10,TI_PREEMPT(r9)
1173 RESTORE_xSRR(SRR0,SRR1);
1174 RESTORE_xSRR(CSRR0,CSRR1);
1176 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
1178 .globl ret_from_mcheck_exc
1179 ret_from_mcheck_exc:
1180 mfspr r9,SPRN_SPRG_THREAD
1181 lwz r10,SAVED_KSP_LIMIT(r1)
1182 stw r10,KSP_LIMIT(r9)
1183 RESTORE_xSRR(SRR0,SRR1);
1184 RESTORE_xSRR(CSRR0,CSRR1);
1185 RESTORE_xSRR(DSRR0,DSRR1);
1187 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
1188 #endif /* CONFIG_BOOKE */
1191 * Load the DBCR0 value for a task that is being ptraced,
1192 * having first saved away the global DBCR0. Note that r0
1193 * has the dbcr0 value to set upon entry to this.
1196 mfmsr r10 /* first disable debug exceptions */
1197 rlwinm r10,r10,0,~MSR_DE
1200 mfspr r10,SPRN_DBCR0
1201 lis r11,global_dbcr0@ha
1202 addi r11,r11,global_dbcr0@l
1204 CURRENT_THREAD_INFO(r9, r1)
1215 mtspr SPRN_DBSR,r11 /* clear all pending debug events */
1223 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
1225 do_work: /* r10 contains MSR_KERNEL here */
1226 andi. r0,r9,_TIF_NEED_RESCHED
1229 do_resched: /* r10 contains MSR_KERNEL here */
1230 /* Note: We don't need to inform lockdep that we are enabling
1231 * interrupts here. As far as it knows, they are already enabled
1235 MTMSRD(r10) /* hard-enable interrupts */
1238 /* Note: And we don't tell it we are disabling them again
1239 * neither. Those disable/enable cycles used to peek at
1240 * TI_FLAGS aren't advertised.
1242 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
1244 MTMSRD(r10) /* disable interrupts */
1245 CURRENT_THREAD_INFO(r9, r1)
1247 andi. r0,r9,_TIF_NEED_RESCHED
1249 andi. r0,r9,_TIF_USER_WORK_MASK
1251 do_user_signal: /* r10 contains MSR_KERNEL here */
1254 MTMSRD(r10) /* hard-enable interrupts */
1255 /* save r13-r31 in the exception frame, if not already done */
1262 2: addi r3,r1,STACK_FRAME_OVERHEAD
1269 * We come here when we are at the end of handling an exception
1270 * that occurred at a place where taking an exception will lose
1271 * state information, such as the contents of SRR0 and SRR1.
1274 lis r10,exc_exit_restart_end@ha
1275 addi r10,r10,exc_exit_restart_end@l
1278 lis r11,exc_exit_restart@ha
1279 addi r11,r11,exc_exit_restart@l
1282 lis r10,ee_restarts@ha
1283 lwz r12,ee_restarts@l(r10)
1285 stw r12,ee_restarts@l(r10)
1286 mr r12,r11 /* restart at exc_exit_restart */
1288 3: /* OK, we can't recover, kill this process */
1289 /* but the 601 doesn't implement the RI bit, so assume it's OK */
1292 END_FTR_SECTION_IFSET(CPU_FTR_601)
1299 4: addi r3,r1,STACK_FRAME_OVERHEAD
1300 bl nonrecoverable_exception
1301 /* shouldn't return */
1311 * PROM code for specific machines follows. Put it
1312 * here so it's easy to add arch-specific sections later.
1315 #ifdef CONFIG_PPC_RTAS
1317 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1318 * called with the MMU off.
1321 stwu r1,-INT_FRAME_SIZE(r1)
1323 stw r0,INT_FRAME_SIZE+4(r1)
1324 LOAD_REG_ADDR(r4, rtas)
1325 lis r6,1f@ha /* physical return address for rtas */
1329 lwz r8,RTASENTRY(r4)
1333 LOAD_MSR_KERNEL(r0,MSR_KERNEL)
1334 SYNC /* disable interrupts so SRR0/1 */
1335 MTMSRD(r0) /* don't get trashed */
1336 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1338 mtspr SPRN_SPRG_RTAS,r7
1343 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
1344 lwz r9,8(r9) /* original msr value */
1345 addi r1,r1,INT_FRAME_SIZE
1347 mtspr SPRN_SPRG_RTAS,r0
1350 RFI /* return to caller */
1352 .globl machine_check_in_rtas
1353 machine_check_in_rtas:
1355 /* XXX load up BATs and panic */
1357 #endif /* CONFIG_PPC_RTAS */