3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/errno.h>
23 #include <linux/err.h>
24 #include <linux/sys.h>
25 #include <linux/threads.h>
29 #include <asm/cputable.h>
30 #include <asm/thread_info.h>
31 #include <asm/ppc_asm.h>
32 #include <asm/asm-offsets.h>
33 #include <asm/unistd.h>
34 #include <asm/ftrace.h>
35 #include <asm/ptrace.h>
36 #include <asm/barrier.h>
39 * MSR_KERNEL is > 0x10000 on 4xx/Book-E since it include MSR_CE.
41 #if MSR_KERNEL >= 0x10000
42 #define LOAD_MSR_KERNEL(r, x) lis r,(x)@h; ori r,r,(x)@l
44 #define LOAD_MSR_KERNEL(r, x) li r,(x)
48 .globl mcheck_transfer_to_handler
49 mcheck_transfer_to_handler:
56 .globl debug_transfer_to_handler
57 debug_transfer_to_handler:
64 .globl crit_transfer_to_handler
65 crit_transfer_to_handler:
66 #ifdef CONFIG_PPC_BOOK3E_MMU
77 #ifdef CONFIG_PHYS_64BIT
80 #endif /* CONFIG_PHYS_64BIT */
81 #endif /* CONFIG_PPC_BOOK3E_MMU */
91 /* set the stack limit to the current stack
92 * and set the limit to protect the thread_info
95 mfspr r8,SPRN_SPRG_THREAD
97 stw r0,SAVED_KSP_LIMIT(r11)
98 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
104 .globl crit_transfer_to_handler
105 crit_transfer_to_handler:
111 stw r0,crit_srr0@l(0)
113 stw r0,crit_srr1@l(0)
115 /* set the stack limit to the current stack
116 * and set the limit to protect the thread_info
119 mfspr r8,SPRN_SPRG_THREAD
121 stw r0,saved_ksp_limit@l(0)
122 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
128 * This code finishes saving the registers to the exception frame
129 * and jumps to the appropriate handler for the exception, turning
130 * on address translation.
131 * Note that we rely on the caller having set cr0.eq iff the exception
132 * occurred in kernel mode (i.e. MSR:PR = 0).
134 .globl transfer_to_handler_full
135 transfer_to_handler_full:
139 .globl transfer_to_handler
149 mfspr r12,SPRN_SPRG_THREAD
151 tovirt(r2,r2) /* set r2 to current */
152 beq 2f /* if from user, fix up THREAD.regs */
153 addi r11,r1,STACK_FRAME_OVERHEAD
155 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
156 /* Check to see if the dbcr0 register is set up to debug. Use the
157 internal debug mode bit to do this. */
158 lwz r12,THREAD_DBCR0(r12)
159 andis. r12,r12,DBCR0_IDM@h
161 /* From user and task is ptraced - load up global dbcr0 */
162 li r12,-1 /* clear all pending debug events */
164 lis r11,global_dbcr0@ha
166 addi r11,r11,global_dbcr0@l
168 CURRENT_THREAD_INFO(r9, r1)
181 2: /* if from kernel, check interrupted DOZE/NAP mode and
182 * check for stack overflow
184 lwz r9,KSP_LIMIT(r12)
185 cmplw r1,r9 /* if r1 <= ksp_limit */
186 ble- stack_ovf /* then the kernel stack overflowed */
188 #if defined(CONFIG_6xx) || defined(CONFIG_E500)
189 CURRENT_THREAD_INFO(r9, r1)
190 tophys(r9,r9) /* check local flags */
191 lwz r12,TI_LOCAL_FLAGS(r9)
193 bt- 31-TLF_NAPPING,4f
194 bt- 31-TLF_SLEEPING,7f
195 #endif /* CONFIG_6xx || CONFIG_E500 */
196 .globl transfer_to_handler_cont
197 transfer_to_handler_cont:
200 lwz r11,0(r9) /* virtual address of handler */
201 lwz r9,4(r9) /* where to go when done */
202 #ifdef CONFIG_TRACE_IRQFLAGS
203 lis r12,reenable_mmu@h
204 ori r12,r12,reenable_mmu@l
209 reenable_mmu: /* re-enable mmu so we can */
213 andi. r10,r10,MSR_EE /* Did EE change? */
217 * The trace_hardirqs_off will use CALLER_ADDR0 and CALLER_ADDR1.
218 * If from user mode there is only one stack frame on the stack, and
219 * accessing CALLER_ADDR1 will cause oops. So we need create a dummy
220 * stack frame to make trace_hardirqs_off happy.
222 * This is handy because we also need to save a bunch of GPRs,
223 * r3 can be different from GPR3(r1) at this point, r9 and r11
224 * contains the old MSR and handler address respectively,
225 * r4 & r5 can contain page fault arguments that need to be passed
226 * along as well. r12, CCR, CTR, XER etc... are left clobbered as
227 * they aren't useful past this point (aren't syscall arguments),
228 * the rest is restored from the exception frame.
236 bl trace_hardirqs_off
249 bctr /* jump to handler */
250 #else /* CONFIG_TRACE_IRQFLAGS */
255 RFI /* jump to handler, enable MMU */
256 #endif /* CONFIG_TRACE_IRQFLAGS */
258 #if defined (CONFIG_6xx) || defined(CONFIG_E500)
259 4: rlwinm r12,r12,0,~_TLF_NAPPING
260 stw r12,TI_LOCAL_FLAGS(r9)
261 b power_save_ppc32_restore
263 7: rlwinm r12,r12,0,~_TLF_SLEEPING
264 stw r12,TI_LOCAL_FLAGS(r9)
265 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
266 rlwinm r9,r9,0,~MSR_EE
267 lwz r12,_LINK(r11) /* and return to address in LR */
268 b fast_exception_return
272 * On kernel stack overflow, load up an initial stack pointer
273 * and call StackOverflow(regs), which should not return.
276 /* sometimes we use a statically-allocated stack, which is OK. */
280 ble 5b /* r1 <= &_end is OK */
282 addi r3,r1,STACK_FRAME_OVERHEAD
283 lis r1,init_thread_union@ha
284 addi r1,r1,init_thread_union@l
285 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
286 lis r9,StackOverflow@ha
287 addi r9,r9,StackOverflow@l
288 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
296 * Handle a system call.
298 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
299 .stabs "entry_32.S",N_SO,0,0,0f
306 lwz r11,_CCR(r1) /* Clear SO bit in CR */
309 #ifdef CONFIG_TRACE_IRQFLAGS
310 /* Return from syscalls can (and generally will) hard enable
311 * interrupts. You aren't supposed to call a syscall with
312 * interrupts disabled in the first place. However, to ensure
313 * that we get it right vs. lockdep if it happens, we force
314 * that hard enable here with appropriate tracing if we see
315 * that we have been called with interrupts off
320 /* We came in with interrupts disabled, we enable them now */
333 #endif /* CONFIG_TRACE_IRQFLAGS */
334 CURRENT_THREAD_INFO(r10, r1)
335 lwz r11,TI_FLAGS(r10)
336 andi. r11,r11,_TIF_SYSCALL_DOTRACE
338 syscall_dotrace_cont:
339 cmplwi 0,r0,NR_syscalls
340 lis r10,sys_call_table@h
341 ori r10,r10,sys_call_table@l
347 * Prevent the load of the handler below (based on the user-passed
348 * system call number) being speculatively executed until the test
349 * against NR_syscalls and branch to .66f above has
353 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
355 addi r9,r1,STACK_FRAME_OVERHEAD
357 blrl /* Call handler */
358 .globl ret_from_syscall
361 CURRENT_THREAD_INFO(r12, r1)
362 /* disable interrupts so current_thread_info()->flags can't change */
363 LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
364 /* Note: We don't bother telling lockdep about it */
369 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
370 bne- syscall_exit_work
372 blt+ syscall_exit_cont
373 lwz r11,_CCR(r1) /* Load CR */
375 oris r11,r11,0x1000 /* Set SO bit in CR */
379 #ifdef CONFIG_TRACE_IRQFLAGS
380 /* If we are going to return from the syscall with interrupts
381 * off, we trace that here. It shouldn't happen though but we
382 * want to catch the bugger if it does right ?
387 bl trace_hardirqs_off
390 #endif /* CONFIG_TRACE_IRQFLAGS */
391 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
392 /* If the process has its own DBCR0 value, load it up. The internal
393 debug mode bit tells us that dbcr0 should be loaded. */
394 lwz r0,THREAD+THREAD_DBCR0(r2)
395 andis. r10,r0,DBCR0_IDM@h
399 BEGIN_MMU_FTR_SECTION
400 lis r4,icache_44x_need_flush@ha
401 lwz r5,icache_44x_need_flush@l(r4)
405 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x)
406 #endif /* CONFIG_44x */
409 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
410 stwcx. r0,0,r1 /* to clear the reservation */
426 stw r7,icache_44x_need_flush@l(r4)
428 #endif /* CONFIG_44x */
440 .globl ret_from_kernel_thread
441 ret_from_kernel_thread:
451 /* Traced system call support */
456 addi r3,r1,STACK_FRAME_OVERHEAD
457 bl do_syscall_trace_enter
459 * Restore argument registers possibly just changed.
460 * We use the return value of do_syscall_trace_enter
461 * for call number to look up in the table (r0).
472 cmplwi r0,NR_syscalls
473 /* Return code is already in r3 thanks to do_syscall_trace_enter() */
474 bge- ret_from_syscall
475 b syscall_dotrace_cont
478 andi. r0,r9,_TIF_RESTOREALL
484 andi. r0,r9,_TIF_NOERROR
486 lwz r11,_CCR(r1) /* Load CR */
488 oris r11,r11,0x1000 /* Set SO bit in CR */
491 1: stw r6,RESULT(r1) /* Save result */
492 stw r3,GPR3(r1) /* Update return value */
493 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
496 /* Clear per-syscall TIF flags if any are set. */
498 li r11,_TIF_PERSYSCALL_MASK
499 addi r12,r12,TI_FLAGS
502 #ifdef CONFIG_IBM405_ERR77
507 subi r12,r12,TI_FLAGS
509 4: /* Anything which requires enabling interrupts? */
510 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
513 /* Re-enable interrupts. There is no need to trace that with
514 * lockdep as we are supposed to have IRQs on at this point
520 /* Save NVGPRS if they're not saved already */
528 addi r3,r1,STACK_FRAME_OVERHEAD
529 bl do_syscall_trace_leave
530 b ret_from_except_full
533 * The fork/clone functions need to copy the full register set into
534 * the child process. Therefore we need to save all the nonvolatile
535 * registers (r13 - r31) before calling the C code.
541 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
542 stw r0,_TRAP(r1) /* register set saved */
549 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
550 stw r0,_TRAP(r1) /* register set saved */
557 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
558 stw r0,_TRAP(r1) /* register set saved */
561 .globl ppc_swapcontext
565 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
566 stw r0,_TRAP(r1) /* register set saved */
570 * Top-level page fault handling.
571 * This is in assembler because if do_page_fault tells us that
572 * it is a bad kernel page fault, we want to save the non-volatile
573 * registers before calling bad_page_fault.
575 .globl handle_page_fault
578 addi r3,r1,STACK_FRAME_OVERHEAD
587 addi r3,r1,STACK_FRAME_OVERHEAD
590 b ret_from_except_full
593 * This routine switches between two different tasks. The process
594 * state of one is saved on its kernel stack. Then the state
595 * of the other is restored from its kernel stack. The memory
596 * management hardware is updated to the second process's state.
597 * Finally, we can return to the second process.
598 * On entry, r3 points to the THREAD for the current task, r4
599 * points to the THREAD for the new task.
601 * This routine is always called with interrupts disabled.
603 * Note: there are two ways to get to the "going out" portion
604 * of this code; either by coming in via the entry (_switch)
605 * or via "fork" which must set up an environment equivalent
606 * to the "_switch" path. If you change this , you'll have to
607 * change the fork code also.
609 * The code which creates the new task context is in 'copy_thread'
610 * in arch/ppc/kernel/process.c
613 stwu r1,-INT_FRAME_SIZE(r1)
615 stw r0,INT_FRAME_SIZE+4(r1)
616 /* r3-r12 are caller saved -- Cort */
618 stw r0,_NIP(r1) /* Return to switch caller */
620 li r0,MSR_FP /* Disable floating-point */
621 #ifdef CONFIG_ALTIVEC
623 oris r0,r0,MSR_VEC@h /* Disable altivec */
624 mfspr r12,SPRN_VRSAVE /* save vrsave register value */
625 stw r12,THREAD+THREAD_VRSAVE(r2)
626 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
627 #endif /* CONFIG_ALTIVEC */
630 oris r0,r0,MSR_SPE@h /* Disable SPE */
631 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
632 stw r12,THREAD+THREAD_SPEFSCR(r2)
633 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
634 #endif /* CONFIG_SPE */
635 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
643 stw r1,KSP(r3) /* Set old stack pointer */
646 /* We need a sync somewhere here to make sure that if the
647 * previous task gets rescheduled on another CPU, it sees all
648 * stores it has performed on this one.
651 #endif /* CONFIG_SMP */
655 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */
656 lwz r1,KSP(r4) /* Load new stack pointer */
658 /* save the old current 'last' for return value */
660 addi r2,r4,-THREAD /* Update current */
662 #ifdef CONFIG_ALTIVEC
664 lwz r0,THREAD+THREAD_VRSAVE(r2)
665 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
666 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
667 #endif /* CONFIG_ALTIVEC */
670 lwz r0,THREAD+THREAD_SPEFSCR(r2)
671 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
672 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
673 #endif /* CONFIG_SPE */
677 /* r3-r12 are destroyed -- Cort */
680 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
682 addi r1,r1,INT_FRAME_SIZE
685 .globl fast_exception_return
686 fast_exception_return:
687 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
688 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
689 beq 1f /* if not, we've got problems */
692 2: REST_4GPRS(3, r11)
698 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
710 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
711 /* check if the exception happened in a restartable section */
712 1: lis r3,exc_exit_restart_end@ha
713 addi r3,r3,exc_exit_restart_end@l
716 lis r4,exc_exit_restart@ha
717 addi r4,r4,exc_exit_restart@l
720 lis r3,fee_restarts@ha
722 lwz r5,fee_restarts@l(r3)
724 stw r5,fee_restarts@l(r3)
725 mr r12,r4 /* restart at exc_exit_restart */
734 /* aargh, a nonrecoverable interrupt, panic */
735 /* aargh, we don't know which trap this is */
736 /* but the 601 doesn't implement the RI bit, so assume it's OK */
740 END_FTR_SECTION_IFSET(CPU_FTR_601)
743 addi r3,r1,STACK_FRAME_OVERHEAD
745 ori r10,r10,MSR_KERNEL@l
746 bl transfer_to_handler_full
747 .long nonrecoverable_exception
748 .long ret_from_except
751 .globl ret_from_except_full
752 ret_from_except_full:
756 .globl ret_from_except
758 /* Hard-disable interrupts so that current_thread_info()->flags
759 * can't change between when we test it and when we return
760 * from the interrupt. */
761 /* Note: We don't bother telling lockdep about it */
762 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
763 SYNC /* Some chip revs have problems here... */
764 MTMSRD(r10) /* disable interrupts */
766 lwz r3,_MSR(r1) /* Returning to user mode? */
770 user_exc_return: /* r10 contains MSR_KERNEL here */
771 /* Check current_thread_info()->flags */
772 CURRENT_THREAD_INFO(r9, r1)
774 andi. r0,r9,_TIF_USER_WORK_MASK
778 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
779 /* Check whether this process has its own DBCR0 value. The internal
780 debug mode bit tells us that dbcr0 should be loaded. */
781 lwz r0,THREAD+THREAD_DBCR0(r2)
782 andis. r10,r0,DBCR0_IDM@h
788 /* N.B. the only way to get here is from the beq following ret_from_except. */
790 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
791 CURRENT_THREAD_INFO(r9, r1)
793 andis. r0,r8,_TIF_EMULATE_STACK_STORE@h
796 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
799 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
800 mr r4,r1 /* src: current exception frame */
801 mr r1,r3 /* Reroute the trampoline frame to r1 */
803 /* Copy from the original to the trampoline. */
804 li r5,INT_FRAME_SIZE/4 /* size: INT_FRAME_SIZE */
805 li r6,0 /* start offset: 0 */
812 /* Do real store operation to complete stwu */
816 /* Clear _TIF_EMULATE_STACK_STORE flag */
817 lis r11,_TIF_EMULATE_STACK_STORE@h
821 #ifdef CONFIG_IBM405_ERR77
828 #ifdef CONFIG_PREEMPT
829 /* check current_thread_info->preempt_count */
830 lwz r0,TI_PREEMPT(r9)
831 cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
833 andi. r8,r8,_TIF_NEED_RESCHED
836 andi. r0,r3,MSR_EE /* interrupts off? */
837 beq restore /* don't schedule if so */
838 #ifdef CONFIG_TRACE_IRQFLAGS
839 /* Lockdep thinks irqs are enabled, we need to call
840 * preempt_schedule_irq with IRQs off, so we inform lockdep
841 * now that we -did- turn them off already
843 bl trace_hardirqs_off
845 1: bl preempt_schedule_irq
846 CURRENT_THREAD_INFO(r9, r1)
848 andi. r0,r3,_TIF_NEED_RESCHED
850 #ifdef CONFIG_TRACE_IRQFLAGS
851 /* And now, to properly rebalance the above, we tell lockdep they
852 * are being turned back on, which will happen when we return
856 #endif /* CONFIG_PREEMPT */
858 /* interrupts are hard-disabled at this point */
861 BEGIN_MMU_FTR_SECTION
863 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
864 lis r4,icache_44x_need_flush@ha
865 lwz r5,icache_44x_need_flush@l(r4)
870 stw r6,icache_44x_need_flush@l(r4)
872 #endif /* CONFIG_44x */
875 #ifdef CONFIG_TRACE_IRQFLAGS
876 /* Lockdep doesn't know about the fact that IRQs are temporarily turned
877 * off in this assembly code while peeking at TI_FLAGS() and such. However
878 * we need to inform it if the exception turned interrupts off, and we
879 * are about to trun them back on.
881 * The problem here sadly is that we don't know whether the exceptions was
882 * one that turned interrupts off or not. So we always tell lockdep about
883 * turning them on here when we go back to wherever we came from with EE
884 * on, even if that may meen some redudant calls being tracked. Maybe later
885 * we could encode what the exception did somewhere or test the exception
886 * type in the pt_regs but that sounds overkill
891 * Since the ftrace irqsoff latency trace checks CALLER_ADDR1,
892 * which is the stack frame here, we need to force a stack frame
893 * in case we came from user space.
904 #endif /* CONFIG_TRACE_IRQFLAGS */
919 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
920 stwcx. r0,0,r1 /* to clear the reservation */
922 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
923 andi. r10,r9,MSR_RI /* check if this exception occurred */
924 beql nonrecoverable /* at a bad place (MSR:RI = 0) */
931 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
935 * Once we put values in SRR0 and SRR1, we are in a state
936 * where exceptions are not recoverable, since taking an
937 * exception will trash SRR0 and SRR1. Therefore we clear the
938 * MSR:RI bit to indicate this. If we do take an exception,
939 * we can't return to the point of the exception but we
940 * can restart the exception exit path at the label
941 * exc_exit_restart below. -- paulus
943 LOAD_MSR_KERNEL(r10,MSR_KERNEL & ~MSR_RI)
945 MTMSRD(r10) /* clear the RI bit */
946 .globl exc_exit_restart
954 .globl exc_exit_restart_end
955 exc_exit_restart_end:
959 #else /* !(CONFIG_4xx || CONFIG_BOOKE) */
961 * This is a bit different on 4xx/Book-E because it doesn't have
962 * the RI bit in the MSR.
963 * The TLB miss handler checks if we have interrupted
964 * the exception exit path and restarts it if so
965 * (well maybe one day it will... :).
971 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
975 .globl exc_exit_restart
984 .globl exc_exit_restart_end
985 exc_exit_restart_end:
988 b . /* prevent prefetch past rfi */
991 * Returning from a critical interrupt in user mode doesn't need
992 * to be any different from a normal exception. For a critical
993 * interrupt in the kernel, we just return (without checking for
994 * preemption) since the interrupt may have happened at some crucial
995 * place (e.g. inside the TLB miss handler), and because we will be
996 * running with r1 pointing into critical_stack, not the current
997 * process's kernel stack (and therefore current_thread_info() will
998 * give the wrong answer).
999 * We have to restore various SPRs that may have been in use at the
1000 * time of the critical interrupt.
1004 #define PPC_40x_TURN_OFF_MSR_DR \
1005 /* avoid any possible TLB misses here by turning off MSR.DR, we \
1006 * assume the instructions here are mapped by a pinned TLB entry */ \
1012 #define PPC_40x_TURN_OFF_MSR_DR
1015 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
1018 andi. r3,r3,MSR_PR; \
1019 LOAD_MSR_KERNEL(r10,MSR_KERNEL); \
1020 bne user_exc_return; \
1023 REST_4GPRS(3, r1); \
1024 REST_2GPRS(7, r1); \
1027 mtspr SPRN_XER,r10; \
1029 PPC405_ERR77(0,r1); \
1030 stwcx. r0,0,r1; /* to clear the reservation */ \
1031 lwz r11,_LINK(r1); \
1035 PPC_40x_TURN_OFF_MSR_DR; \
1038 mtspr SPRN_DEAR,r9; \
1039 mtspr SPRN_ESR,r10; \
1042 mtspr exc_lvl_srr0,r11; \
1043 mtspr exc_lvl_srr1,r12; \
1045 lwz r12,GPR12(r1); \
1046 lwz r10,GPR10(r1); \
1047 lwz r11,GPR11(r1); \
1049 PPC405_ERR77_SYNC; \
1051 b .; /* prevent prefetch past exc_lvl_rfi */
1053 #define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \
1054 lwz r9,_##exc_lvl_srr0(r1); \
1055 lwz r10,_##exc_lvl_srr1(r1); \
1056 mtspr SPRN_##exc_lvl_srr0,r9; \
1057 mtspr SPRN_##exc_lvl_srr1,r10;
1059 #if defined(CONFIG_PPC_BOOK3E_MMU)
1060 #ifdef CONFIG_PHYS_64BIT
1061 #define RESTORE_MAS7 \
1063 mtspr SPRN_MAS7,r11;
1065 #define RESTORE_MAS7
1066 #endif /* CONFIG_PHYS_64BIT */
1067 #define RESTORE_MMU_REGS \
1071 mtspr SPRN_MAS0,r9; \
1073 mtspr SPRN_MAS1,r10; \
1075 mtspr SPRN_MAS2,r11; \
1076 mtspr SPRN_MAS3,r9; \
1077 mtspr SPRN_MAS6,r10; \
1079 #elif defined(CONFIG_44x)
1080 #define RESTORE_MMU_REGS \
1082 mtspr SPRN_MMUCR,r9;
1084 #define RESTORE_MMU_REGS
1088 .globl ret_from_crit_exc
1090 mfspr r9,SPRN_SPRG_THREAD
1091 lis r10,saved_ksp_limit@ha;
1092 lwz r10,saved_ksp_limit@l(r10);
1094 stw r10,KSP_LIMIT(r9)
1095 lis r9,crit_srr0@ha;
1096 lwz r9,crit_srr0@l(r9);
1097 lis r10,crit_srr1@ha;
1098 lwz r10,crit_srr1@l(r10);
1100 mtspr SPRN_SRR1,r10;
1101 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1102 #endif /* CONFIG_40x */
1105 .globl ret_from_crit_exc
1107 mfspr r9,SPRN_SPRG_THREAD
1108 lwz r10,SAVED_KSP_LIMIT(r1)
1109 stw r10,KSP_LIMIT(r9)
1110 RESTORE_xSRR(SRR0,SRR1);
1112 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1114 .globl ret_from_debug_exc
1116 mfspr r9,SPRN_SPRG_THREAD
1117 lwz r10,SAVED_KSP_LIMIT(r1)
1118 stw r10,KSP_LIMIT(r9)
1119 lwz r9,THREAD_INFO-THREAD(r9)
1120 CURRENT_THREAD_INFO(r10, r1)
1121 lwz r10,TI_PREEMPT(r10)
1122 stw r10,TI_PREEMPT(r9)
1123 RESTORE_xSRR(SRR0,SRR1);
1124 RESTORE_xSRR(CSRR0,CSRR1);
1126 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
1128 .globl ret_from_mcheck_exc
1129 ret_from_mcheck_exc:
1130 mfspr r9,SPRN_SPRG_THREAD
1131 lwz r10,SAVED_KSP_LIMIT(r1)
1132 stw r10,KSP_LIMIT(r9)
1133 RESTORE_xSRR(SRR0,SRR1);
1134 RESTORE_xSRR(CSRR0,CSRR1);
1135 RESTORE_xSRR(DSRR0,DSRR1);
1137 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
1138 #endif /* CONFIG_BOOKE */
1141 * Load the DBCR0 value for a task that is being ptraced,
1142 * having first saved away the global DBCR0. Note that r0
1143 * has the dbcr0 value to set upon entry to this.
1146 mfmsr r10 /* first disable debug exceptions */
1147 rlwinm r10,r10,0,~MSR_DE
1150 mfspr r10,SPRN_DBCR0
1151 lis r11,global_dbcr0@ha
1152 addi r11,r11,global_dbcr0@l
1154 CURRENT_THREAD_INFO(r9, r1)
1165 mtspr SPRN_DBSR,r11 /* clear all pending debug events */
1173 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
1175 do_work: /* r10 contains MSR_KERNEL here */
1176 andi. r0,r9,_TIF_NEED_RESCHED
1179 do_resched: /* r10 contains MSR_KERNEL here */
1180 /* Note: We don't need to inform lockdep that we are enabling
1181 * interrupts here. As far as it knows, they are already enabled
1185 MTMSRD(r10) /* hard-enable interrupts */
1188 /* Note: And we don't tell it we are disabling them again
1189 * neither. Those disable/enable cycles used to peek at
1190 * TI_FLAGS aren't advertised.
1192 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
1194 MTMSRD(r10) /* disable interrupts */
1195 CURRENT_THREAD_INFO(r9, r1)
1197 andi. r0,r9,_TIF_NEED_RESCHED
1199 andi. r0,r9,_TIF_USER_WORK_MASK
1201 do_user_signal: /* r10 contains MSR_KERNEL here */
1204 MTMSRD(r10) /* hard-enable interrupts */
1205 /* save r13-r31 in the exception frame, if not already done */
1212 2: addi r3,r1,STACK_FRAME_OVERHEAD
1219 * We come here when we are at the end of handling an exception
1220 * that occurred at a place where taking an exception will lose
1221 * state information, such as the contents of SRR0 and SRR1.
1224 lis r10,exc_exit_restart_end@ha
1225 addi r10,r10,exc_exit_restart_end@l
1228 lis r11,exc_exit_restart@ha
1229 addi r11,r11,exc_exit_restart@l
1232 lis r10,ee_restarts@ha
1233 lwz r12,ee_restarts@l(r10)
1235 stw r12,ee_restarts@l(r10)
1236 mr r12,r11 /* restart at exc_exit_restart */
1238 3: /* OK, we can't recover, kill this process */
1239 /* but the 601 doesn't implement the RI bit, so assume it's OK */
1242 END_FTR_SECTION_IFSET(CPU_FTR_601)
1249 4: addi r3,r1,STACK_FRAME_OVERHEAD
1250 bl nonrecoverable_exception
1251 /* shouldn't return */
1261 * PROM code for specific machines follows. Put it
1262 * here so it's easy to add arch-specific sections later.
1265 #ifdef CONFIG_PPC_RTAS
1267 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1268 * called with the MMU off.
1271 stwu r1,-INT_FRAME_SIZE(r1)
1273 stw r0,INT_FRAME_SIZE+4(r1)
1274 LOAD_REG_ADDR(r4, rtas)
1275 lis r6,1f@ha /* physical return address for rtas */
1279 lwz r8,RTASENTRY(r4)
1283 LOAD_MSR_KERNEL(r0,MSR_KERNEL)
1284 SYNC /* disable interrupts so SRR0/1 */
1285 MTMSRD(r0) /* don't get trashed */
1286 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1288 mtspr SPRN_SPRG_RTAS,r7
1293 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
1294 lwz r9,8(r9) /* original msr value */
1296 addi r1,r1,INT_FRAME_SIZE
1298 mtspr SPRN_SPRG_RTAS,r0
1301 RFI /* return to caller */
1303 .globl machine_check_in_rtas
1304 machine_check_in_rtas:
1306 /* XXX load up BATs and panic */
1308 #endif /* CONFIG_PPC_RTAS */
1310 #ifdef CONFIG_FUNCTION_TRACER
1311 #ifdef CONFIG_DYNAMIC_FTRACE
1315 * It is required that _mcount on PPC32 must preserve the
1316 * link register. But we have r0 to play with. We use r0
1317 * to push the return address back to the caller of mcount
1318 * into the ctr register, restore the link register and
1319 * then jump back using the ctr register.
1327 _GLOBAL(ftrace_caller)
1329 /* r3 ends up with link register */
1330 subi r3, r3, MCOUNT_INSN_SIZE
1335 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1336 .globl ftrace_graph_call
1339 _GLOBAL(ftrace_graph_stub)
1341 MCOUNT_RESTORE_FRAME
1342 /* old link register ends up in ctr reg */
1350 subi r3, r3, MCOUNT_INSN_SIZE
1351 LOAD_REG_ADDR(r5, ftrace_trace_function)
1358 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1359 b ftrace_graph_caller
1361 MCOUNT_RESTORE_FRAME
1365 _GLOBAL(ftrace_stub)
1368 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1369 _GLOBAL(ftrace_graph_caller)
1370 /* load r4 with local address */
1372 subi r4, r4, MCOUNT_INSN_SIZE
1374 /* Grab the LR out of the caller stack frame */
1377 bl prepare_ftrace_return
1381 * prepare_ftrace_return gives us the address we divert to.
1382 * Change the LR in the callers stack frame to this.
1386 MCOUNT_RESTORE_FRAME
1387 /* old link register ends up in ctr reg */
1390 _GLOBAL(return_to_handler)
1391 /* need to save return values */
1398 bl ftrace_return_to_handler
1401 /* return value has real return address */
1409 /* Jump back to real return address */
1411 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1413 #endif /* CONFIG_FUNCTION_TRACER */