1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
13 * This file contains the system call entry code, context switch
14 * code, and exception/interrupt return code for PowerPC.
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/sys.h>
20 #include <linux/threads.h>
24 #include <asm/cputable.h>
25 #include <asm/thread_info.h>
26 #include <asm/ppc_asm.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/unistd.h>
29 #include <asm/ptrace.h>
30 #include <asm/export.h>
31 #include <asm/feature-fixups.h>
32 #include <asm/barrier.h>
39 * powerpc relies on return from interrupt/syscall being context synchronising
40 * (which rfi is) to support ARCH_HAS_MEMBARRIER_SYNC_CORE without additional
41 * synchronisation instructions.
45 * Align to 4k in order to ensure that all functions modyfing srr0/srr1
46 * fit into one page in order to not encounter a TLB miss between the
47 * modification of srr0/srr1 and the associated rfi.
52 .globl mcheck_transfer_to_handler
53 mcheck_transfer_to_handler:
59 _ASM_NOKPROBE_SYMBOL(mcheck_transfer_to_handler)
61 .globl debug_transfer_to_handler
62 debug_transfer_to_handler:
68 _ASM_NOKPROBE_SYMBOL(debug_transfer_to_handler)
70 .globl crit_transfer_to_handler
71 crit_transfer_to_handler:
72 #ifdef CONFIG_PPC_BOOK3E_MMU
83 #ifdef CONFIG_PHYS_64BIT
86 #endif /* CONFIG_PHYS_64BIT */
87 #endif /* CONFIG_PPC_BOOK3E_MMU */
97 /* set the stack limit to the current stack */
98 mfspr r8,SPRN_SPRG_THREAD
100 stw r0,SAVED_KSP_LIMIT(r11)
101 rlwinm r0,r1,0,0,(31 - THREAD_SHIFT)
104 _ASM_NOKPROBE_SYMBOL(crit_transfer_to_handler)
108 .globl crit_transfer_to_handler
109 crit_transfer_to_handler:
115 stw r0,crit_srr0@l(0)
117 stw r0,crit_srr1@l(0)
119 /* set the stack limit to the current stack */
120 mfspr r8,SPRN_SPRG_THREAD
122 stw r0,saved_ksp_limit@l(0)
123 rlwinm r0,r1,0,0,(31 - THREAD_SHIFT)
126 _ASM_NOKPROBE_SYMBOL(crit_transfer_to_handler)
130 * This code finishes saving the registers to the exception frame
131 * and jumps to the appropriate handler for the exception, turning
132 * on address translation.
133 * Note that we rely on the caller having set cr0.eq iff the exception
134 * occurred in kernel mode (i.e. MSR:PR = 0).
136 .globl transfer_to_handler_full
137 transfer_to_handler_full:
139 _ASM_NOKPROBE_SYMBOL(transfer_to_handler_full)
142 .globl transfer_to_handler
152 mfspr r12,SPRN_SPRG_THREAD
153 tovirt_vmstack r12, r12
154 beq 2f /* if from user, fix up THREAD.regs */
155 addi r2, r12, -THREAD
156 addi r11,r1,STACK_FRAME_OVERHEAD
158 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
159 /* Check to see if the dbcr0 register is set up to debug. Use the
160 internal debug mode bit to do this. */
161 lwz r12,THREAD_DBCR0(r12)
162 andis. r12,r12,DBCR0_IDM@h
164 ACCOUNT_CPU_USER_ENTRY(r2, r11, r12)
165 #ifdef CONFIG_PPC_BOOK3S_32
168 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
170 /* From user and task is ptraced - load up global dbcr0 */
171 li r12,-1 /* clear all pending debug events */
173 lis r11,global_dbcr0@ha
175 addi r11,r11,global_dbcr0@l
190 2: /* if from kernel, check interrupted DOZE/NAP mode and
191 * check for stack overflow
193 kuap_save_and_lock r11, r12, r9, r2, r6
194 addi r2, r12, -THREAD
195 #ifndef CONFIG_VMAP_STACK
196 lwz r9,KSP_LIMIT(r12)
197 cmplw r1,r9 /* if r1 <= ksp_limit */
198 ble- stack_ovf /* then the kernel stack overflowed */
201 #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500)
202 lwz r12,TI_LOCAL_FLAGS(r2)
204 bt- 31-TLF_NAPPING,4f
205 bt- 31-TLF_SLEEPING,7f
206 #endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_E500 */
207 .globl transfer_to_handler_cont
208 transfer_to_handler_cont:
211 tovirt_novmstack r2, r2 /* set r2 to current */
212 tovirt_vmstack r9, r9
213 lwz r11,0(r9) /* virtual address of handler */
214 lwz r9,4(r9) /* where to go when done */
215 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
218 #ifdef CONFIG_TRACE_IRQFLAGS
220 * When tracing IRQ state (lockdep) we enable the MMU before we call
221 * the IRQ tracing functions as they might access vmalloc space or
222 * perform IOs for console output.
224 * To speed up the syscall path where interrupts stay on, let's check
225 * first if we are changing the MSR value at all.
227 tophys_novmstack r12, r1
232 /* MSR isn't changing, just transition directly */
237 RFI /* jump to handler, enable MMU */
239 #if defined (CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500)
240 4: rlwinm r12,r12,0,~_TLF_NAPPING
241 stw r12,TI_LOCAL_FLAGS(r2)
242 b power_save_ppc32_restore
244 7: rlwinm r12,r12,0,~_TLF_SLEEPING
245 stw r12,TI_LOCAL_FLAGS(r2)
246 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
247 rlwinm r9,r9,0,~MSR_EE
248 lwz r12,_LINK(r11) /* and return to address in LR */
249 kuap_restore r11, r2, r3, r4, r5
251 b fast_exception_return
253 _ASM_NOKPROBE_SYMBOL(transfer_to_handler)
254 _ASM_NOKPROBE_SYMBOL(transfer_to_handler_cont)
256 #ifdef CONFIG_TRACE_IRQFLAGS
257 1: /* MSR is changing, re-enable MMU so we can notify lockdep. We need to
258 * keep interrupts disabled at this point otherwise we might risk
259 * taking an interrupt before we tell lockdep they are enabled.
261 lis r12,reenable_mmu@h
262 ori r12,r12,reenable_mmu@l
263 LOAD_REG_IMMEDIATE(r0, MSR_KERNEL)
270 * We save a bunch of GPRs,
271 * r3 can be different from GPR3(r1) at this point, r9 and r11
272 * contains the old MSR and handler address respectively,
273 * r4 & r5 can contain page fault arguments that need to be passed
274 * along as well. r0, r6-r8, r12, CCR, CTR, XER etc... are left
275 * clobbered as they aren't useful past this point.
285 /* If we are disabling interrupts (normal case), simply log it with
288 1: bl trace_hardirqs_off
297 bctr /* jump to handler */
298 #endif /* CONFIG_TRACE_IRQFLAGS */
300 #ifndef CONFIG_VMAP_STACK
302 * On kernel stack overflow, load up an initial stack pointer
303 * and call StackOverflow(regs), which should not return.
306 /* sometimes we use a statically-allocated stack, which is OK. */
310 ble 5b /* r1 <= &_end is OK */
312 addi r3,r1,STACK_FRAME_OVERHEAD
313 lis r1,init_thread_union@ha
314 addi r1,r1,init_thread_union@l
315 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
316 lis r9,StackOverflow@ha
317 addi r9,r9,StackOverflow@l
318 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL)
319 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
325 _ASM_NOKPROBE_SYMBOL(stack_ovf)
328 #ifdef CONFIG_TRACE_IRQFLAGS
329 trace_syscall_entry_irq_off:
331 * Syscall shouldn't happen while interrupts are disabled,
332 * so let's do a warning here.
335 EMIT_BUG_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING
338 /* Now enable for real */
339 LOAD_REG_IMMEDIATE(r10, MSR_KERNEL | MSR_EE)
346 #endif /* CONFIG_TRACE_IRQFLAGS */
348 .globl transfer_to_syscall
350 #ifdef CONFIG_PPC_BOOK3S_32
353 #ifdef CONFIG_TRACE_IRQFLAGS
355 beq- trace_syscall_entry_irq_off
356 #endif /* CONFIG_TRACE_IRQFLAGS */
359 * Handle a system call.
361 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
362 .stabs "entry_32.S",N_SO,0,0,0f
369 #ifdef CONFIG_TRACE_IRQFLAGS
370 /* Make sure interrupts are enabled */
373 /* We came in with interrupts disabled, we WARN and mark them enabled
376 EMIT_BUG_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING
377 #endif /* CONFIG_TRACE_IRQFLAGS */
379 andi. r11,r11,_TIF_SYSCALL_DOTRACE
381 syscall_dotrace_cont:
382 cmplwi 0,r0,NR_syscalls
383 lis r10,sys_call_table@h
384 ori r10,r10,sys_call_table@l
390 * Prevent the load of the handler below (based on the user-passed
391 * system call number) being speculatively executed until the test
392 * against NR_syscalls and branch to .66f above has
396 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
398 addi r9,r1,STACK_FRAME_OVERHEAD
400 blrl /* Call handler */
401 .globl ret_from_syscall
403 #ifdef CONFIG_DEBUG_RSEQ
404 /* Check whether the syscall is issued inside a restartable sequence */
406 addi r3,r1,STACK_FRAME_OVERHEAD
411 /* disable interrupts so current_thread_info()->flags can't change */
412 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL) /* doesn't include MSR_EE */
413 /* Note: We don't bother telling lockdep about it */
417 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
418 bne- syscall_exit_work
420 blt+ syscall_exit_cont
421 lwz r11,_CCR(r1) /* Load CR */
423 oris r11,r11,0x1000 /* Set SO bit in CR */
427 #ifdef CONFIG_TRACE_IRQFLAGS
428 /* If we are going to return from the syscall with interrupts
429 * off, we trace that here. It shouldn't normally happen.
434 bl trace_hardirqs_off
437 #endif /* CONFIG_TRACE_IRQFLAGS */
438 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
439 /* If the process has its own DBCR0 value, load it up. The internal
440 debug mode bit tells us that dbcr0 should be loaded. */
441 lwz r0,THREAD+THREAD_DBCR0(r2)
442 andis. r10,r0,DBCR0_IDM@h
446 BEGIN_MMU_FTR_SECTION
447 lis r4,icache_44x_need_flush@ha
448 lwz r5,icache_44x_need_flush@l(r4)
452 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x)
453 #endif /* CONFIG_44x */
456 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
457 stwcx. r0,0,r1 /* to clear the reservation */
458 ACCOUNT_CPU_USER_EXIT(r2, r5, r7)
459 #ifdef CONFIG_PPC_BOOK3S_32
471 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
477 _ASM_NOKPROBE_SYMBOL(syscall_exit_finish)
481 stw r7,icache_44x_need_flush@l(r4)
483 #endif /* CONFIG_44x */
495 .globl ret_from_kernel_thread
496 ret_from_kernel_thread:
506 /* Traced system call support */
511 addi r3,r1,STACK_FRAME_OVERHEAD
512 bl do_syscall_trace_enter
514 * Restore argument registers possibly just changed.
515 * We use the return value of do_syscall_trace_enter
516 * for call number to look up in the table (r0).
527 cmplwi r0,NR_syscalls
528 /* Return code is already in r3 thanks to do_syscall_trace_enter() */
529 bge- ret_from_syscall
530 b syscall_dotrace_cont
533 andi. r0,r9,_TIF_RESTOREALL
539 andi. r0,r9,_TIF_NOERROR
541 lwz r11,_CCR(r1) /* Load CR */
543 oris r11,r11,0x1000 /* Set SO bit in CR */
546 1: stw r6,RESULT(r1) /* Save result */
547 stw r3,GPR3(r1) /* Update return value */
548 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
551 /* Clear per-syscall TIF flags if any are set. */
553 li r11,_TIF_PERSYSCALL_MASK
560 4: /* Anything which requires enabling interrupts? */
561 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
564 /* Re-enable interrupts. There is no need to trace that with
565 * lockdep as we are supposed to have IRQs on at this point
570 /* Save NVGPRS if they're not saved already */
578 addi r3,r1,STACK_FRAME_OVERHEAD
579 bl do_syscall_trace_leave
580 b ret_from_except_full
583 * System call was called from kernel. We get here with SRR1 in r9.
584 * Mark the exception as recoverable once we have retrieved SRR0,
585 * trap a warning and return ENOSYS with CR[SO] set.
587 .globl ret_from_kernel_syscall
588 ret_from_kernel_syscall:
591 #if !defined(CONFIG_4xx) && !defined(CONFIG_BOOKE)
592 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~(MSR_IR|MSR_DR))
597 EMIT_BUG_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING
601 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
607 _ASM_NOKPROBE_SYMBOL(ret_from_kernel_syscall)
610 * The fork/clone functions need to copy the full register set into
611 * the child process. Therefore we need to save all the nonvolatile
612 * registers (r13 - r31) before calling the C code.
618 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
619 stw r0,_TRAP(r1) /* register set saved */
626 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
627 stw r0,_TRAP(r1) /* register set saved */
634 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
635 stw r0,_TRAP(r1) /* register set saved */
642 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
643 stw r0,_TRAP(r1) /* register set saved */
646 .globl ppc_swapcontext
650 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
651 stw r0,_TRAP(r1) /* register set saved */
655 * Top-level page fault handling.
656 * This is in assembler because if do_page_fault tells us that
657 * it is a bad kernel page fault, we want to save the non-volatile
658 * registers before calling bad_page_fault.
660 .globl handle_page_fault
662 addi r3,r1,STACK_FRAME_OVERHEAD
663 #ifdef CONFIG_PPC_BOOK3S_32
664 andis. r0,r5,DSISR_DABRMATCH@h
665 bne- handle_dabr_fault
675 addi r3,r1,STACK_FRAME_OVERHEAD
678 b ret_from_except_full
680 #ifdef CONFIG_PPC_BOOK3S_32
681 /* We have a data breakpoint exception - handle it */
688 b ret_from_except_full
692 * This routine switches between two different tasks. The process
693 * state of one is saved on its kernel stack. Then the state
694 * of the other is restored from its kernel stack. The memory
695 * management hardware is updated to the second process's state.
696 * Finally, we can return to the second process.
697 * On entry, r3 points to the THREAD for the current task, r4
698 * points to the THREAD for the new task.
700 * This routine is always called with interrupts disabled.
702 * Note: there are two ways to get to the "going out" portion
703 * of this code; either by coming in via the entry (_switch)
704 * or via "fork" which must set up an environment equivalent
705 * to the "_switch" path. If you change this , you'll have to
706 * change the fork code also.
708 * The code which creates the new task context is in 'copy_thread'
709 * in arch/ppc/kernel/process.c
712 stwu r1,-INT_FRAME_SIZE(r1)
714 stw r0,INT_FRAME_SIZE+4(r1)
715 /* r3-r12 are caller saved -- Cort */
717 stw r0,_NIP(r1) /* Return to switch caller */
719 li r0,MSR_FP /* Disable floating-point */
720 #ifdef CONFIG_ALTIVEC
722 oris r0,r0,MSR_VEC@h /* Disable altivec */
723 mfspr r12,SPRN_VRSAVE /* save vrsave register value */
724 stw r12,THREAD+THREAD_VRSAVE(r2)
725 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
726 #endif /* CONFIG_ALTIVEC */
729 oris r0,r0,MSR_SPE@h /* Disable SPE */
730 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
731 stw r12,THREAD+THREAD_SPEFSCR(r2)
732 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
733 #endif /* CONFIG_SPE */
734 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
742 stw r1,KSP(r3) /* Set old stack pointer */
746 /* We need a sync somewhere here to make sure that if the
747 * previous task gets rescheduled on another CPU, it sees all
748 * stores it has performed on this one.
751 #endif /* CONFIG_SMP */
754 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */
755 lwz r1,KSP(r4) /* Load new stack pointer */
757 /* save the old current 'last' for return value */
759 addi r2,r4,-THREAD /* Update current */
761 #ifdef CONFIG_ALTIVEC
763 lwz r0,THREAD+THREAD_VRSAVE(r2)
764 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
765 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
766 #endif /* CONFIG_ALTIVEC */
769 lwz r0,THREAD+THREAD_SPEFSCR(r2)
770 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
771 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
772 #endif /* CONFIG_SPE */
776 /* r3-r12 are destroyed -- Cort */
779 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
781 addi r1,r1,INT_FRAME_SIZE
784 .globl fast_exception_return
785 fast_exception_return:
786 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
787 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
788 beq 1f /* if not, we've got problems */
791 2: REST_4GPRS(3, r11)
797 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
801 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
810 _ASM_NOKPROBE_SYMBOL(fast_exception_return)
812 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
813 /* check if the exception happened in a restartable section */
814 1: lis r3,exc_exit_restart_end@ha
815 addi r3,r3,exc_exit_restart_end@l
818 lis r4,exc_exit_restart@ha
819 addi r4,r4,exc_exit_restart@l
822 lis r3,fee_restarts@ha
824 lwz r5,fee_restarts@l(r3)
826 stw r5,fee_restarts@l(r3)
827 mr r12,r4 /* restart at exc_exit_restart */
836 /* aargh, a nonrecoverable interrupt, panic */
837 /* aargh, we don't know which trap this is */
841 addi r3,r1,STACK_FRAME_OVERHEAD
843 ori r10,r10,MSR_KERNEL@l
844 bl transfer_to_handler_full
845 .long unrecoverable_exception
846 .long ret_from_except
849 .globl ret_from_except_full
850 ret_from_except_full:
854 .globl ret_from_except
856 /* Hard-disable interrupts so that current_thread_info()->flags
857 * can't change between when we test it and when we return
858 * from the interrupt. */
859 /* Note: We don't bother telling lockdep about it */
860 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL)
861 mtmsr r10 /* disable interrupts */
863 lwz r3,_MSR(r1) /* Returning to user mode? */
867 user_exc_return: /* r10 contains MSR_KERNEL here */
868 /* Check current_thread_info()->flags */
870 andi. r0,r9,_TIF_USER_WORK_MASK
874 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
875 /* Check whether this process has its own DBCR0 value. The internal
876 debug mode bit tells us that dbcr0 should be loaded. */
877 lwz r0,THREAD+THREAD_DBCR0(r2)
878 andis. r10,r0,DBCR0_IDM@h
881 ACCOUNT_CPU_USER_EXIT(r2, r10, r11)
882 #ifdef CONFIG_PPC_BOOK3S_32
888 /* N.B. the only way to get here is from the beq following ret_from_except. */
890 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
892 andis. r0,r8,_TIF_EMULATE_STACK_STORE@h
895 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
898 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
899 mr r4,r1 /* src: current exception frame */
900 mr r1,r3 /* Reroute the trampoline frame to r1 */
902 /* Copy from the original to the trampoline. */
903 li r5,INT_FRAME_SIZE/4 /* size: INT_FRAME_SIZE */
904 li r6,0 /* start offset: 0 */
911 /* Do real store operation to complete stwu */
915 /* Clear _TIF_EMULATE_STACK_STORE flag */
916 lis r11,_TIF_EMULATE_STACK_STORE@h
924 #ifdef CONFIG_PREEMPTION
925 /* check current_thread_info->preempt_count */
926 lwz r0,TI_PREEMPT(r2)
927 cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
929 andi. r8,r8,_TIF_NEED_RESCHED
932 andi. r0,r3,MSR_EE /* interrupts off? */
933 beq restore_kuap /* don't schedule if so */
934 #ifdef CONFIG_TRACE_IRQFLAGS
935 /* Lockdep thinks irqs are enabled, we need to call
936 * preempt_schedule_irq with IRQs off, so we inform lockdep
937 * now that we -did- turn them off already
939 bl trace_hardirqs_off
941 bl preempt_schedule_irq
942 #ifdef CONFIG_TRACE_IRQFLAGS
943 /* And now, to properly rebalance the above, we tell lockdep they
944 * are being turned back on, which will happen when we return
948 #endif /* CONFIG_PREEMPTION */
950 kuap_restore r1, r2, r9, r10, r0
952 /* interrupts are hard-disabled at this point */
955 BEGIN_MMU_FTR_SECTION
957 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
958 lis r4,icache_44x_need_flush@ha
959 lwz r5,icache_44x_need_flush@l(r4)
964 stw r6,icache_44x_need_flush@l(r4)
966 #endif /* CONFIG_44x */
969 #ifdef CONFIG_TRACE_IRQFLAGS
970 /* Lockdep doesn't know about the fact that IRQs are temporarily turned
971 * off in this assembly code while peeking at TI_FLAGS() and such. However
972 * we need to inform it if the exception turned interrupts off, and we
973 * are about to trun them back on.
984 #endif /* CONFIG_TRACE_IRQFLAGS */
998 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
999 stwcx. r0,0,r1 /* to clear the reservation */
1001 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
1002 andi. r10,r9,MSR_RI /* check if this exception occurred */
1003 beql nonrecoverable /* at a bad place (MSR:RI = 0) */
1010 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
1014 * Once we put values in SRR0 and SRR1, we are in a state
1015 * where exceptions are not recoverable, since taking an
1016 * exception will trash SRR0 and SRR1. Therefore we clear the
1017 * MSR:RI bit to indicate this. If we do take an exception,
1018 * we can't return to the point of the exception but we
1019 * can restart the exception exit path at the label
1020 * exc_exit_restart below. -- paulus
1022 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL & ~MSR_RI)
1023 mtmsr r10 /* clear the RI bit */
1024 .globl exc_exit_restart
1031 .globl exc_exit_restart_end
1032 exc_exit_restart_end:
1034 _ASM_NOKPROBE_SYMBOL(exc_exit_restart)
1035 _ASM_NOKPROBE_SYMBOL(exc_exit_restart_end)
1037 #else /* !(CONFIG_4xx || CONFIG_BOOKE) */
1039 * This is a bit different on 4xx/Book-E because it doesn't have
1040 * the RI bit in the MSR.
1041 * The TLB miss handler checks if we have interrupted
1042 * the exception exit path and restarts it if so
1043 * (well maybe one day it will... :).
1049 /* Clear the exception_marker on the stack to avoid confusing stacktrace */
1053 .globl exc_exit_restart
1061 .globl exc_exit_restart_end
1062 exc_exit_restart_end:
1064 b . /* prevent prefetch past rfi */
1065 _ASM_NOKPROBE_SYMBOL(exc_exit_restart)
1068 * Returning from a critical interrupt in user mode doesn't need
1069 * to be any different from a normal exception. For a critical
1070 * interrupt in the kernel, we just return (without checking for
1071 * preemption) since the interrupt may have happened at some crucial
1072 * place (e.g. inside the TLB miss handler), and because we will be
1073 * running with r1 pointing into critical_stack, not the current
1074 * process's kernel stack (and therefore current_thread_info() will
1075 * give the wrong answer).
1076 * We have to restore various SPRs that may have been in use at the
1077 * time of the critical interrupt.
1081 #define PPC_40x_TURN_OFF_MSR_DR \
1082 /* avoid any possible TLB misses here by turning off MSR.DR, we \
1083 * assume the instructions here are mapped by a pinned TLB entry */ \
1089 #define PPC_40x_TURN_OFF_MSR_DR
1092 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
1095 andi. r3,r3,MSR_PR; \
1096 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL); \
1097 bne user_exc_return; \
1100 REST_4GPRS(3, r1); \
1101 REST_2GPRS(7, r1); \
1104 mtspr SPRN_XER,r10; \
1106 stwcx. r0,0,r1; /* to clear the reservation */ \
1107 lwz r11,_LINK(r1); \
1111 PPC_40x_TURN_OFF_MSR_DR; \
1114 mtspr SPRN_DEAR,r9; \
1115 mtspr SPRN_ESR,r10; \
1118 mtspr exc_lvl_srr0,r11; \
1119 mtspr exc_lvl_srr1,r12; \
1121 lwz r12,GPR12(r1); \
1122 lwz r10,GPR10(r1); \
1123 lwz r11,GPR11(r1); \
1126 b .; /* prevent prefetch past exc_lvl_rfi */
1128 #define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \
1129 lwz r9,_##exc_lvl_srr0(r1); \
1130 lwz r10,_##exc_lvl_srr1(r1); \
1131 mtspr SPRN_##exc_lvl_srr0,r9; \
1132 mtspr SPRN_##exc_lvl_srr1,r10;
1134 #if defined(CONFIG_PPC_BOOK3E_MMU)
1135 #ifdef CONFIG_PHYS_64BIT
1136 #define RESTORE_MAS7 \
1138 mtspr SPRN_MAS7,r11;
1140 #define RESTORE_MAS7
1141 #endif /* CONFIG_PHYS_64BIT */
1142 #define RESTORE_MMU_REGS \
1146 mtspr SPRN_MAS0,r9; \
1148 mtspr SPRN_MAS1,r10; \
1150 mtspr SPRN_MAS2,r11; \
1151 mtspr SPRN_MAS3,r9; \
1152 mtspr SPRN_MAS6,r10; \
1154 #elif defined(CONFIG_44x)
1155 #define RESTORE_MMU_REGS \
1157 mtspr SPRN_MMUCR,r9;
1159 #define RESTORE_MMU_REGS
1163 .globl ret_from_crit_exc
1165 mfspr r9,SPRN_SPRG_THREAD
1166 lis r10,saved_ksp_limit@ha;
1167 lwz r10,saved_ksp_limit@l(r10);
1169 stw r10,KSP_LIMIT(r9)
1170 lis r9,crit_srr0@ha;
1171 lwz r9,crit_srr0@l(r9);
1172 lis r10,crit_srr1@ha;
1173 lwz r10,crit_srr1@l(r10);
1175 mtspr SPRN_SRR1,r10;
1176 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1177 _ASM_NOKPROBE_SYMBOL(ret_from_crit_exc)
1178 #endif /* CONFIG_40x */
1181 .globl ret_from_crit_exc
1183 mfspr r9,SPRN_SPRG_THREAD
1184 lwz r10,SAVED_KSP_LIMIT(r1)
1185 stw r10,KSP_LIMIT(r9)
1186 RESTORE_xSRR(SRR0,SRR1);
1188 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1189 _ASM_NOKPROBE_SYMBOL(ret_from_crit_exc)
1191 .globl ret_from_debug_exc
1193 mfspr r9,SPRN_SPRG_THREAD
1194 lwz r10,SAVED_KSP_LIMIT(r1)
1195 stw r10,KSP_LIMIT(r9)
1196 RESTORE_xSRR(SRR0,SRR1);
1197 RESTORE_xSRR(CSRR0,CSRR1);
1199 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
1200 _ASM_NOKPROBE_SYMBOL(ret_from_debug_exc)
1202 .globl ret_from_mcheck_exc
1203 ret_from_mcheck_exc:
1204 mfspr r9,SPRN_SPRG_THREAD
1205 lwz r10,SAVED_KSP_LIMIT(r1)
1206 stw r10,KSP_LIMIT(r9)
1207 RESTORE_xSRR(SRR0,SRR1);
1208 RESTORE_xSRR(CSRR0,CSRR1);
1209 RESTORE_xSRR(DSRR0,DSRR1);
1211 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
1212 _ASM_NOKPROBE_SYMBOL(ret_from_mcheck_exc)
1213 #endif /* CONFIG_BOOKE */
1216 * Load the DBCR0 value for a task that is being ptraced,
1217 * having first saved away the global DBCR0. Note that r0
1218 * has the dbcr0 value to set upon entry to this.
1221 mfmsr r10 /* first disable debug exceptions */
1222 rlwinm r10,r10,0,~MSR_DE
1225 mfspr r10,SPRN_DBCR0
1226 lis r11,global_dbcr0@ha
1227 addi r11,r11,global_dbcr0@l
1239 mtspr SPRN_DBSR,r11 /* clear all pending debug events */
1244 .global global_dbcr0
1248 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
1250 do_work: /* r10 contains MSR_KERNEL here */
1251 andi. r0,r9,_TIF_NEED_RESCHED
1254 do_resched: /* r10 contains MSR_KERNEL here */
1255 #ifdef CONFIG_TRACE_IRQFLAGS
1256 bl trace_hardirqs_on
1260 mtmsr r10 /* hard-enable interrupts */
1263 /* Note: And we don't tell it we are disabling them again
1264 * neither. Those disable/enable cycles used to peek at
1265 * TI_FLAGS aren't advertised.
1267 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL)
1268 mtmsr r10 /* disable interrupts */
1270 andi. r0,r9,_TIF_NEED_RESCHED
1272 andi. r0,r9,_TIF_USER_WORK_MASK
1274 do_user_signal: /* r10 contains MSR_KERNEL here */
1276 mtmsr r10 /* hard-enable interrupts */
1277 /* save r13-r31 in the exception frame, if not already done */
1284 2: addi r3,r1,STACK_FRAME_OVERHEAD
1291 * We come here when we are at the end of handling an exception
1292 * that occurred at a place where taking an exception will lose
1293 * state information, such as the contents of SRR0 and SRR1.
1296 lis r10,exc_exit_restart_end@ha
1297 addi r10,r10,exc_exit_restart_end@l
1300 lis r11,exc_exit_restart@ha
1301 addi r11,r11,exc_exit_restart@l
1304 lis r10,ee_restarts@ha
1305 lwz r12,ee_restarts@l(r10)
1307 stw r12,ee_restarts@l(r10)
1308 mr r12,r11 /* restart at exc_exit_restart */
1310 3: /* OK, we can't recover, kill this process */
1317 5: mfspr r2,SPRN_SPRG_THREAD
1319 tovirt(r2,r2) /* set back r2 to current */
1320 4: addi r3,r1,STACK_FRAME_OVERHEAD
1321 bl unrecoverable_exception
1322 /* shouldn't return */
1324 _ASM_NOKPROBE_SYMBOL(nonrecoverable)
1333 * PROM code for specific machines follows. Put it
1334 * here so it's easy to add arch-specific sections later.
1337 #ifdef CONFIG_PPC_RTAS
1339 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1340 * called with the MMU off.
1343 stwu r1,-INT_FRAME_SIZE(r1)
1345 stw r0,INT_FRAME_SIZE+4(r1)
1346 LOAD_REG_ADDR(r4, rtas)
1347 lis r6,1f@ha /* physical return address for rtas */
1350 tophys_novmstack r7, r1
1351 lwz r8,RTASENTRY(r4)
1355 LOAD_REG_IMMEDIATE(r0,MSR_KERNEL)
1356 mtmsr r0 /* disable interrupts so SRR0/1 don't get trashed */
1357 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1359 stw r7, THREAD + RTAS_SP(r2)
1363 1: tophys_novmstack r9, r1
1364 #ifdef CONFIG_VMAP_STACK
1365 li r0, MSR_KERNEL & ~MSR_IR /* can take DTLB miss */
1369 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
1370 lwz r9,8(r9) /* original msr value */
1371 addi r1,r1,INT_FRAME_SIZE
1373 tophys_novmstack r7, r2
1374 stw r0, THREAD + RTAS_SP(r7)
1377 RFI /* return to caller */
1378 _ASM_NOKPROBE_SYMBOL(enter_rtas)
1379 #endif /* CONFIG_PPC_RTAS */