1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
13 * This file contains the system call entry code, context switch
14 * code, and exception/interrupt return code for PowerPC.
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/sys.h>
20 #include <linux/threads.h>
24 #include <asm/cputable.h>
25 #include <asm/thread_info.h>
26 #include <asm/ppc_asm.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/unistd.h>
29 #include <asm/ptrace.h>
30 #include <asm/export.h>
31 #include <asm/feature-fixups.h>
32 #include <asm/barrier.h>
35 #include <asm/interrupt.h>
40 * powerpc relies on return from interrupt/syscall being context synchronising
41 * (which rfi is) to support ARCH_HAS_MEMBARRIER_SYNC_CORE without additional
42 * synchronisation instructions.
46 * Align to 4k in order to ensure that all functions modyfing srr0/srr1
47 * fit into one page in order to not encounter a TLB miss between the
48 * modification of srr0/srr1 and the associated rfi.
52 #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_E500)
53 .globl prepare_transfer_to_handler
54 prepare_transfer_to_handler:
55 /* if from kernel, check interrupted DOZE/NAP mode */
56 lwz r12,TI_LOCAL_FLAGS(r2)
59 bt- 31-TLF_SLEEPING,7f
62 4: rlwinm r12,r12,0,~_TLF_NAPPING
63 stw r12,TI_LOCAL_FLAGS(r2)
64 b power_save_ppc32_restore
66 7: rlwinm r12,r12,0,~_TLF_SLEEPING
67 stw r12,TI_LOCAL_FLAGS(r2)
68 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
69 rlwinm r9,r9,0,~MSR_EE
70 lwz r12,_LINK(r11) /* and return to address in LR */
72 b fast_exception_return
73 _ASM_NOKPROBE_SYMBOL(prepare_transfer_to_handler)
74 #endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_PPC_E500 */
76 #if defined(CONFIG_PPC_KUEP) && defined(CONFIG_PPC_BOOK3S_32)
79 lwz r9, THREAD+THSR0(r2)
80 update_user_segments_by_4 r9, r10, r11, r12
84 lwz r9, THREAD+THSR0(r2)
86 update_user_segments_by_4 r9, r10, r11, r12
102 .globl transfer_to_syscall
104 stw r3, ORIG_GPR3(r1)
109 #ifdef CONFIG_BOOKE_OR_40x
110 rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */
112 lis r12,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
114 addi r12,r12,STACK_FRAME_REGS_MARKER@l
116 li r2, INTERRUPT_SYSCALL
125 /* Calling convention has r3 = regs, r4 = orig r0 */
126 addi r3,r1,STACK_FRAME_OVERHEAD
128 bl system_call_exception
131 addi r4,r1,STACK_FRAME_OVERHEAD
133 bl syscall_exit_prepare
134 #ifdef CONFIG_PPC_47x
135 lis r4,icache_44x_need_flush@ha
136 lwz r5,icache_44x_need_flush@l(r4)
139 #endif /* CONFIG_PPC_47x */
159 b . /* Prevent prefetch past rfi */
175 stw r7,icache_44x_need_flush@l(r4)
177 #endif /* CONFIG_44x */
186 .globl ret_from_kernel_thread
187 ret_from_kernel_thread:
198 * This routine switches between two different tasks. The process
199 * state of one is saved on its kernel stack. Then the state
200 * of the other is restored from its kernel stack. The memory
201 * management hardware is updated to the second process's state.
202 * Finally, we can return to the second process.
203 * On entry, r3 points to the THREAD for the current task, r4
204 * points to the THREAD for the new task.
206 * This routine is always called with interrupts disabled.
208 * Note: there are two ways to get to the "going out" portion
209 * of this code; either by coming in via the entry (_switch)
210 * or via "fork" which must set up an environment equivalent
211 * to the "_switch" path. If you change this , you'll have to
212 * change the fork code also.
214 * The code which creates the new task context is in 'copy_thread'
215 * in arch/ppc/kernel/process.c
218 stwu r1,-INT_FRAME_SIZE(r1)
220 stw r0,INT_FRAME_SIZE+4(r1)
221 /* r3-r12 are caller saved -- Cort */
223 stw r0,_NIP(r1) /* Return to switch caller */
226 stw r1,KSP(r3) /* Set old stack pointer */
229 /* We need a sync somewhere here to make sure that if the
230 * previous task gets rescheduled on another CPU, it sees all
231 * stores it has performed on this one.
234 #endif /* CONFIG_SMP */
237 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */
238 lwz r1,KSP(r4) /* Load new stack pointer */
240 /* save the old current 'last' for return value */
242 addi r2,r4,-THREAD /* Update current */
246 /* r3-r12 are destroyed -- Cort */
249 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
251 addi r1,r1,INT_FRAME_SIZE
254 .globl fast_exception_return
255 fast_exception_return:
256 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
257 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
258 beq 3f /* if not, we've got problems */
266 /* Clear the exception marker on the stack to avoid confusing stacktrace */
270 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
280 b . /* Prevent prefetch past rfi */
282 _ASM_NOKPROBE_SYMBOL(fast_exception_return)
284 /* aargh, a nonrecoverable interrupt, panic */
285 /* aargh, we don't know which trap this is */
289 prepare_transfer_to_handler
290 bl unrecoverable_exception
291 trap /* should not get here */
293 .globl interrupt_return
296 addi r3,r1,STACK_FRAME_OVERHEAD
298 beq .Lkernel_interrupt_return
299 bl interrupt_exit_user_prepare
302 bne- .Lrestore_nvgprs
304 .Lfast_user_interrupt_return:
311 stwcx. r0,0,r1 /* to clear the reservation */
314 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
323 * Leaving a stale exception marker on the stack can confuse
324 * the reliable stack unwinder later on. Clear it.
339 b . /* Prevent prefetch past rfi */
344 b .Lfast_user_interrupt_return
346 .Lkernel_interrupt_return:
347 bl interrupt_exit_kernel_prepare
349 .Lfast_kernel_interrupt_return:
357 stwcx. r0,0,r1 /* to clear the reservation */
360 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
375 * Leaving a stale exception marker on the stack can confuse
376 * the reliable stack unwinder later on. Clear it.
382 bne- cr1,1f /* emulate stack store */
389 b . /* Prevent prefetch past rfi */
393 * Emulate stack store with update. New r1 value was already calculated
394 * and updated in our interrupt regs by emulate_loadstore, but we can't
395 * store the previous value of r1 to the stack before re-loading our
396 * registers from it, otherwise they could be clobbered. Use
397 * SPRG Scratch0 as temporary storage to hold the store
398 * data, as interrupts are disabled here so it won't be clobbered.
402 mtspr SPRN_SPRG_WSCRATCH0, r9
404 mtspr SPRN_SPRG_SCRATCH0, r9
406 addi r9,r1,INT_FRAME_SIZE /* get original r1 */
410 stw r9,0(r1) /* perform store component of stwu */
412 mfspr r9, SPRN_SPRG_RSCRATCH0
414 mfspr r9, SPRN_SPRG_SCRATCH0
418 b . /* Prevent prefetch past rfi */
420 _ASM_NOKPROBE_SYMBOL(interrupt_return)
422 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
425 * Returning from a critical interrupt in user mode doesn't need
426 * to be any different from a normal exception. For a critical
427 * interrupt in the kernel, we just return (without checking for
428 * preemption) since the interrupt may have happened at some crucial
429 * place (e.g. inside the TLB miss handler), and because we will be
430 * running with r1 pointing into critical_stack, not the current
431 * process's kernel stack (and therefore current_thread_info() will
432 * give the wrong answer).
433 * We have to restore various SPRs that may have been in use at the
434 * time of the critical interrupt.
438 #define PPC_40x_TURN_OFF_MSR_DR \
439 /* avoid any possible TLB misses here by turning off MSR.DR, we \
440 * assume the instructions here are mapped by a pinned TLB entry */ \
446 #define PPC_40x_TURN_OFF_MSR_DR
449 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
452 andi. r3,r3,MSR_PR; \
453 bne interrupt_return; \
455 REST_GPRS(2, 8, r1); \
458 mtspr SPRN_XER,r10; \
460 stwcx. r0,0,r1; /* to clear the reservation */ \
465 PPC_40x_TURN_OFF_MSR_DR; \
468 mtspr SPRN_DEAR,r9; \
469 mtspr SPRN_ESR,r10; \
472 mtspr exc_lvl_srr0,r11; \
473 mtspr exc_lvl_srr1,r12; \
474 REST_GPRS(9, 12, r1); \
477 b .; /* prevent prefetch past exc_lvl_rfi */
479 #define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \
480 lwz r9,_##exc_lvl_srr0(r1); \
481 lwz r10,_##exc_lvl_srr1(r1); \
482 mtspr SPRN_##exc_lvl_srr0,r9; \
483 mtspr SPRN_##exc_lvl_srr1,r10;
485 #if defined(CONFIG_PPC_E500)
486 #ifdef CONFIG_PHYS_64BIT
487 #define RESTORE_MAS7 \
492 #endif /* CONFIG_PHYS_64BIT */
493 #define RESTORE_MMU_REGS \
497 mtspr SPRN_MAS0,r9; \
499 mtspr SPRN_MAS1,r10; \
501 mtspr SPRN_MAS2,r11; \
502 mtspr SPRN_MAS3,r9; \
503 mtspr SPRN_MAS6,r10; \
505 #elif defined(CONFIG_44x)
506 #define RESTORE_MMU_REGS \
510 #define RESTORE_MMU_REGS
514 .globl ret_from_crit_exc
517 lwz r9,crit_srr0@l(r9);
518 lis r10,crit_srr1@ha;
519 lwz r10,crit_srr1@l(r10);
522 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
523 _ASM_NOKPROBE_SYMBOL(ret_from_crit_exc)
524 #endif /* CONFIG_40x */
527 .globl ret_from_crit_exc
529 RESTORE_xSRR(SRR0,SRR1);
531 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
532 _ASM_NOKPROBE_SYMBOL(ret_from_crit_exc)
534 .globl ret_from_debug_exc
536 RESTORE_xSRR(SRR0,SRR1);
537 RESTORE_xSRR(CSRR0,CSRR1);
539 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
540 _ASM_NOKPROBE_SYMBOL(ret_from_debug_exc)
542 .globl ret_from_mcheck_exc
544 RESTORE_xSRR(SRR0,SRR1);
545 RESTORE_xSRR(CSRR0,CSRR1);
546 RESTORE_xSRR(DSRR0,DSRR1);
548 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
549 _ASM_NOKPROBE_SYMBOL(ret_from_mcheck_exc)
550 #endif /* CONFIG_BOOKE */
551 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */