1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright IBM Corporation 2001, 2005, 2006
4 * Copyright Dave Engebretsen & Todd Inglett 2001
5 * Copyright Linas Vepstas 2005, 2006
6 * Copyright 2001-2012 IBM Corporation.
8 * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com>
11 #include <linux/delay.h>
12 #include <linux/sched.h>
13 #include <linux/init.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/iommu.h>
17 #include <linux/proc_fs.h>
18 #include <linux/rbtree.h>
19 #include <linux/reboot.h>
20 #include <linux/seq_file.h>
21 #include <linux/spinlock.h>
22 #include <linux/export.h>
24 #include <linux/debugfs.h>
26 #include <linux/atomic.h>
28 #include <asm/eeh_event.h>
30 #include <asm/iommu.h>
31 #include <asm/machdep.h>
32 #include <asm/ppc-pci.h>
34 #include <asm/pte-walk.h>
38 * EEH, or "Enhanced Error Handling" is a PCI bridge technology for
39 * dealing with PCI bus errors that can't be dealt with within the
40 * usual PCI framework, except by check-stopping the CPU. Systems
41 * that are designed for high-availability/reliability cannot afford
42 * to crash due to a "mere" PCI error, thus the need for EEH.
43 * An EEH-capable bridge operates by converting a detected error
44 * into a "slot freeze", taking the PCI adapter off-line, making
45 * the slot behave, from the OS'es point of view, as if the slot
46 * were "empty": all reads return 0xff's and all writes are silently
47 * ignored. EEH slot isolation events can be triggered by parity
48 * errors on the address or data busses (e.g. during posted writes),
49 * which in turn might be caused by low voltage on the bus, dust,
50 * vibration, humidity, radioactivity or plain-old failed hardware.
52 * Note, however, that one of the leading causes of EEH slot
53 * freeze events are buggy device drivers, buggy device microcode,
54 * or buggy device hardware. This is because any attempt by the
55 * device to bus-master data to a memory address that is not
56 * assigned to the device will trigger a slot freeze. (The idea
57 * is to prevent devices-gone-wild from corrupting system memory).
58 * Buggy hardware/drivers will have a miserable time co-existing
61 * Ideally, a PCI device driver, when suspecting that an isolation
62 * event has occurred (e.g. by reading 0xff's), will then ask EEH
63 * whether this is the case, and then take appropriate steps to
64 * reset the PCI slot, the PCI device, and then resume operations.
65 * However, until that day, the checking is done here, with the
66 * eeh_check_failure() routine embedded in the MMIO macros. If
67 * the slot is found to be isolated, an "EEH Event" is synthesized
68 * and sent out for processing.
71 /* If a device driver keeps reading an MMIO register in an interrupt
72 * handler after a slot isolation event, it might be broken.
73 * This sets the threshold for how many read attempts we allow
74 * before printing an error message.
76 #define EEH_MAX_FAILS 2100000
78 /* Time to wait for a PCI slot to report status, in milliseconds */
79 #define PCI_BUS_RESET_WAIT_MSEC (5*60*1000)
82 * EEH probe mode support, which is part of the flags,
83 * is to support multiple platforms for EEH. Some platforms
84 * like pSeries do PCI emunation based on device tree.
85 * However, other platforms like powernv probe PCI devices
86 * from hardware. The flag is used to distinguish that.
87 * In addition, struct eeh_ops::probe would be invoked for
88 * particular OF node or PCI device so that the corresponding
89 * PE would be created there.
91 int eeh_subsystem_flags;
92 EXPORT_SYMBOL(eeh_subsystem_flags);
95 * EEH allowed maximal frozen times. If one particular PE's
96 * frozen count in last hour exceeds this limit, the PE will
97 * be forced to be offline permanently.
99 u32 eeh_max_freezes = 5;
102 * Controls whether a recovery event should be scheduled when an
103 * isolated device is discovered. This is only really useful for
104 * debugging problems with the EEH core.
106 bool eeh_debugfs_no_recover;
108 /* Platform dependent EEH operations */
109 struct eeh_ops *eeh_ops = NULL;
111 /* Lock to avoid races due to multiple reports of an error */
112 DEFINE_RAW_SPINLOCK(confirm_error_lock);
113 EXPORT_SYMBOL_GPL(confirm_error_lock);
115 /* Lock to protect passed flags */
116 static DEFINE_MUTEX(eeh_dev_mutex);
118 /* Buffer for reporting pci register dumps. Its here in BSS, and
119 * not dynamically alloced, so that it ends up in RMO where RTAS
122 #define EEH_PCI_REGS_LOG_LEN 8192
123 static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN];
126 * The struct is used to maintain the EEH global statistic
127 * information. Besides, the EEH global statistics will be
128 * exported to user space through procfs
131 u64 no_device; /* PCI device not found */
132 u64 no_dn; /* OF node not found */
133 u64 no_cfg_addr; /* Config address not found */
134 u64 ignored_check; /* EEH check skipped */
135 u64 total_mmio_ffs; /* Total EEH checks */
136 u64 false_positives; /* Unnecessary EEH checks */
137 u64 slot_resets; /* PE reset */
140 static struct eeh_stats eeh_stats;
142 static int __init eeh_setup(char *str)
144 if (!strcmp(str, "off"))
145 eeh_add_flag(EEH_FORCE_DISABLED);
146 else if (!strcmp(str, "early_log"))
147 eeh_add_flag(EEH_EARLY_DUMP_LOG);
151 __setup("eeh=", eeh_setup);
153 void eeh_show_enabled(void)
155 if (eeh_has_flag(EEH_FORCE_DISABLED))
156 pr_info("EEH: Recovery disabled by kernel parameter.\n");
157 else if (eeh_has_flag(EEH_ENABLED))
158 pr_info("EEH: Capable adapter found: recovery enabled.\n");
160 pr_info("EEH: No capable adapters found: recovery disabled.\n");
164 * This routine captures assorted PCI configuration space data
165 * for the indicated PCI device, and puts them into a buffer
166 * for RTAS error logging.
168 static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len)
175 n += scnprintf(buf+n, len-n, "%04x:%02x:%02x.%01x\n",
176 edev->pe->phb->global_number, edev->bdfn >> 8,
177 PCI_SLOT(edev->bdfn), PCI_FUNC(edev->bdfn));
178 pr_warn("EEH: of node=%04x:%02x:%02x.%01x\n",
179 edev->pe->phb->global_number, edev->bdfn >> 8,
180 PCI_SLOT(edev->bdfn), PCI_FUNC(edev->bdfn));
182 eeh_ops->read_config(edev, PCI_VENDOR_ID, 4, &cfg);
183 n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg);
184 pr_warn("EEH: PCI device/vendor: %08x\n", cfg);
186 eeh_ops->read_config(edev, PCI_COMMAND, 4, &cfg);
187 n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg);
188 pr_warn("EEH: PCI cmd/status register: %08x\n", cfg);
190 /* Gather bridge-specific registers */
191 if (edev->mode & EEH_DEV_BRIDGE) {
192 eeh_ops->read_config(edev, PCI_SEC_STATUS, 2, &cfg);
193 n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg);
194 pr_warn("EEH: Bridge secondary status: %04x\n", cfg);
196 eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &cfg);
197 n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg);
198 pr_warn("EEH: Bridge control: %04x\n", cfg);
201 /* Dump out the PCI-X command and status regs */
202 cap = edev->pcix_cap;
204 eeh_ops->read_config(edev, cap, 4, &cfg);
205 n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg);
206 pr_warn("EEH: PCI-X cmd: %08x\n", cfg);
208 eeh_ops->read_config(edev, cap+4, 4, &cfg);
209 n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg);
210 pr_warn("EEH: PCI-X status: %08x\n", cfg);
213 /* If PCI-E capable, dump PCI-E cap 10 */
214 cap = edev->pcie_cap;
216 n += scnprintf(buf+n, len-n, "pci-e cap10:\n");
217 pr_warn("EEH: PCI-E capabilities and status follow:\n");
219 for (i=0; i<=8; i++) {
220 eeh_ops->read_config(edev, cap+4*i, 4, &cfg);
221 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
225 pr_warn("%s\n", buffer);
227 l = scnprintf(buffer, sizeof(buffer),
228 "EEH: PCI-E %02x: %08x ",
231 l += scnprintf(buffer+l, sizeof(buffer)-l,
237 pr_warn("%s\n", buffer);
240 /* If AER capable, dump it */
243 n += scnprintf(buf+n, len-n, "pci-e AER:\n");
244 pr_warn("EEH: PCI-E AER capability register set follows:\n");
246 for (i=0; i<=13; i++) {
247 eeh_ops->read_config(edev, cap+4*i, 4, &cfg);
248 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
252 pr_warn("%s\n", buffer);
254 l = scnprintf(buffer, sizeof(buffer),
255 "EEH: PCI-E AER %02x: %08x ",
258 l += scnprintf(buffer+l, sizeof(buffer)-l,
263 pr_warn("%s\n", buffer);
269 static void *eeh_dump_pe_log(struct eeh_pe *pe, void *flag)
271 struct eeh_dev *edev, *tmp;
274 eeh_pe_for_each_dev(pe, edev, tmp)
275 *plen += eeh_dump_dev_log(edev, pci_regs_buf + *plen,
276 EEH_PCI_REGS_LOG_LEN - *plen);
282 * eeh_slot_error_detail - Generate combined log including driver log and error log
284 * @severity: temporary or permanent error log
286 * This routine should be called to generate the combined log, which
287 * is comprised of driver log and error log. The driver log is figured
288 * out from the config space of the corresponding PCI device, while
289 * the error log is fetched through platform dependent function call.
291 void eeh_slot_error_detail(struct eeh_pe *pe, int severity)
296 * When the PHB is fenced or dead, it's pointless to collect
297 * the data from PCI config space because it should return
298 * 0xFF's. For ER, we still retrieve the data from the PCI
301 * For pHyp, we have to enable IO for log retrieval. Otherwise,
302 * 0xFF's is always returned from PCI config space.
304 * When the @severity is EEH_LOG_PERM, the PE is going to be
305 * removed. Prior to that, the drivers for devices included in
306 * the PE will be closed. The drivers rely on working IO path
307 * to bring the devices to quiet state. Otherwise, PCI traffic
308 * from those devices after they are removed is like to cause
309 * another unexpected EEH error.
311 if (!(pe->type & EEH_PE_PHB)) {
312 if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG) ||
313 severity == EEH_LOG_PERM)
314 eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
317 * The config space of some PCI devices can't be accessed
318 * when their PEs are in frozen state. Otherwise, fenced
319 * PHB might be seen. Those PEs are identified with flag
320 * EEH_PE_CFG_RESTRICTED, indicating EEH_PE_CFG_BLOCKED
321 * is set automatically when the PE is put to EEH_PE_ISOLATED.
323 * Restoring BARs possibly triggers PCI config access in
324 * (OPAL) firmware and then causes fenced PHB. If the
325 * PCI config is blocked with flag EEH_PE_CFG_BLOCKED, it's
326 * pointless to restore BARs and dump config space.
328 eeh_ops->configure_bridge(pe);
329 if (!(pe->state & EEH_PE_CFG_BLOCKED)) {
330 eeh_pe_restore_bars(pe);
333 eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen);
337 eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
341 * eeh_token_to_phys - Convert EEH address token to phys address
342 * @token: I/O token, should be address in the form 0xA....
344 * This routine should be called to convert virtual I/O address
347 static inline unsigned long eeh_token_to_phys(unsigned long token)
349 return ppc_find_vmap_phys(token);
353 * On PowerNV platform, we might already have fenced PHB there.
354 * For that case, it's meaningless to recover frozen PE. Intead,
355 * We have to handle fenced PHB firstly.
357 static int eeh_phb_check_failure(struct eeh_pe *pe)
359 struct eeh_pe *phb_pe;
363 if (!eeh_has_flag(EEH_PROBE_MODE_DEV))
366 /* Find the PHB PE */
367 phb_pe = eeh_phb_pe_get(pe->phb);
369 pr_warn("%s Can't find PE for PHB#%x\n",
370 __func__, pe->phb->global_number);
374 /* If the PHB has been in problematic state */
375 eeh_serialize_lock(&flags);
376 if (phb_pe->state & EEH_PE_ISOLATED) {
381 /* Check PHB state */
382 ret = eeh_ops->get_state(phb_pe, NULL);
384 (ret == EEH_STATE_NOT_SUPPORT) || eeh_state_active(ret)) {
389 /* Isolate the PHB and send event */
390 eeh_pe_mark_isolated(phb_pe);
391 eeh_serialize_unlock(flags);
393 pr_debug("EEH: PHB#%x failure detected, location: %s\n",
394 phb_pe->phb->global_number, eeh_pe_loc_get(phb_pe));
395 eeh_send_failure_event(phb_pe);
398 eeh_serialize_unlock(flags);
402 static inline const char *eeh_driver_name(struct pci_dev *pdev)
405 return dev_driver_string(&pdev->dev);
411 * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze
414 * Check for an EEH failure for the given device node. Call this
415 * routine if the result of a read was all 0xff's and you want to
416 * find out if this is due to an EEH slot freeze. This routine
417 * will query firmware for the EEH status.
419 * Returns 0 if there has not been an EEH error; otherwise returns
420 * a non-zero value and queues up a slot isolation event notification.
422 * It is safe to call this routine in an interrupt context.
424 int eeh_dev_check_failure(struct eeh_dev *edev)
428 struct device_node *dn;
430 struct eeh_pe *pe, *parent_pe;
432 const char *location = NULL;
434 eeh_stats.total_mmio_ffs++;
443 dev = eeh_dev_to_pci_dev(edev);
444 pe = eeh_dev_to_pe(edev);
446 /* Access to IO BARs might get this far and still not want checking. */
448 eeh_stats.ignored_check++;
449 eeh_edev_dbg(edev, "Ignored check\n");
454 * On PowerNV platform, we might already have fenced PHB
455 * there and we need take care of that firstly.
457 ret = eeh_phb_check_failure(pe);
462 * If the PE isn't owned by us, we shouldn't check the
463 * state. Instead, let the owner handle it if the PE has
466 if (eeh_pe_passed(pe))
469 /* If we already have a pending isolation event for this
470 * slot, we know it's bad already, we don't need to check.
471 * Do this checking under a lock; as multiple PCI devices
472 * in one slot might report errors simultaneously, and we
473 * only want one error recovery routine running.
475 eeh_serialize_lock(&flags);
477 if (pe->state & EEH_PE_ISOLATED) {
479 if (pe->check_count == EEH_MAX_FAILS) {
480 dn = pci_device_to_OF_node(dev);
482 location = of_get_property(dn, "ibm,loc-code",
484 eeh_edev_err(edev, "%d reads ignored for recovering device at location=%s driver=%s\n",
486 location ? location : "unknown",
487 eeh_driver_name(dev));
488 eeh_edev_err(edev, "Might be infinite loop in %s driver\n",
489 eeh_driver_name(dev));
496 * Now test for an EEH failure. This is VERY expensive.
497 * Note that the eeh_config_addr may be a parent device
498 * in the case of a device behind a bridge, or it may be
499 * function zero of a multi-function device.
500 * In any case they must share a common PHB.
502 ret = eeh_ops->get_state(pe, NULL);
504 /* Note that config-io to empty slots may fail;
505 * they are empty when they don't have children.
506 * We will punt with the following conditions: Failure to get
507 * PE's state, EEH not support and Permanently unavailable
508 * state, PE is in good state.
511 (ret == EEH_STATE_NOT_SUPPORT) || eeh_state_active(ret)) {
512 eeh_stats.false_positives++;
513 pe->false_positives++;
519 * It should be corner case that the parent PE has been
520 * put into frozen state as well. We should take care
523 parent_pe = pe->parent;
525 /* Hit the ceiling ? */
526 if (parent_pe->type & EEH_PE_PHB)
529 /* Frozen parent PE ? */
530 ret = eeh_ops->get_state(parent_pe, NULL);
531 if (ret > 0 && !eeh_state_active(ret)) {
533 pr_err("EEH: Failure of PHB#%x-PE#%x will be handled at parent PHB#%x-PE#%x.\n",
534 pe->phb->global_number, pe->addr,
535 pe->phb->global_number, parent_pe->addr);
538 /* Next parent level */
539 parent_pe = parent_pe->parent;
542 eeh_stats.slot_resets++;
544 /* Avoid repeated reports of this failure, including problems
545 * with other functions on this device, and functions under
548 eeh_pe_mark_isolated(pe);
549 eeh_serialize_unlock(flags);
551 /* Most EEH events are due to device driver bugs. Having
552 * a stack trace will help the device-driver authors figure
553 * out what happened. So print that out.
555 pr_debug("EEH: %s: Frozen PHB#%x-PE#%x detected\n",
556 __func__, pe->phb->global_number, pe->addr);
557 eeh_send_failure_event(pe);
562 eeh_serialize_unlock(flags);
566 EXPORT_SYMBOL_GPL(eeh_dev_check_failure);
569 * eeh_check_failure - Check if all 1's data is due to EEH slot freeze
570 * @token: I/O address
572 * Check for an EEH failure at the given I/O address. Call this
573 * routine if the result of a read was all 0xff's and you want to
574 * find out if this is due to an EEH slot freeze event. This routine
575 * will query firmware for the EEH status.
577 * Note this routine is safe to call in an interrupt context.
579 int eeh_check_failure(const volatile void __iomem *token)
582 struct eeh_dev *edev;
584 /* Finding the phys addr + pci device; this is pretty quick. */
585 addr = eeh_token_to_phys((unsigned long __force) token);
586 edev = eeh_addr_cache_get_dev(addr);
588 eeh_stats.no_device++;
592 return eeh_dev_check_failure(edev);
594 EXPORT_SYMBOL(eeh_check_failure);
598 * eeh_pci_enable - Enable MMIO or DMA transfers for this slot
600 * @function: EEH option
602 * This routine should be called to reenable frozen MMIO or DMA
603 * so that it would work correctly again. It's useful while doing
604 * recovery or log collection on the indicated device.
606 int eeh_pci_enable(struct eeh_pe *pe, int function)
611 * pHyp doesn't allow to enable IO or DMA on unfrozen PE.
612 * Also, it's pointless to enable them on unfrozen PE. So
613 * we have to check before enabling IO or DMA.
616 case EEH_OPT_THAW_MMIO:
617 active_flag = EEH_STATE_MMIO_ACTIVE | EEH_STATE_MMIO_ENABLED;
619 case EEH_OPT_THAW_DMA:
620 active_flag = EEH_STATE_DMA_ACTIVE;
622 case EEH_OPT_DISABLE:
624 case EEH_OPT_FREEZE_PE:
628 pr_warn("%s: Invalid function %d\n",
634 * Check if IO or DMA has been enabled before
638 rc = eeh_ops->get_state(pe, NULL);
642 /* Needn't enable it at all */
643 if (rc == EEH_STATE_NOT_SUPPORT)
646 /* It's already enabled */
647 if (rc & active_flag)
652 /* Issue the request */
653 rc = eeh_ops->set_option(pe, function);
655 pr_warn("%s: Unexpected state change %d on "
656 "PHB#%x-PE#%x, err=%d\n",
657 __func__, function, pe->phb->global_number,
660 /* Check if the request is finished successfully */
662 rc = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
666 if (rc & active_flag)
675 static void eeh_disable_and_save_dev_state(struct eeh_dev *edev,
678 struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
679 struct pci_dev *dev = userdata;
682 * The caller should have disabled and saved the
683 * state for the specified device
685 if (!pdev || pdev == dev)
688 /* Ensure we have D0 power state */
689 pci_set_power_state(pdev, PCI_D0);
691 /* Save device state */
692 pci_save_state(pdev);
695 * Disable device to avoid any DMA traffic and
696 * interrupt from the device
698 pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
701 static void eeh_restore_dev_state(struct eeh_dev *edev, void *userdata)
703 struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
704 struct pci_dev *dev = userdata;
709 /* Apply customization from firmware */
710 if (eeh_ops->restore_config)
711 eeh_ops->restore_config(edev);
713 /* The caller should restore state for the specified device */
715 pci_restore_state(pdev);
719 * pcibios_set_pcie_reset_state - Set PCI-E reset state
720 * @dev: pci device struct
721 * @state: reset state to enter
726 int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
728 struct eeh_dev *edev = pci_dev_to_eeh_dev(dev);
729 struct eeh_pe *pe = eeh_dev_to_pe(edev);
732 pr_err("%s: No PE found on PCI device %s\n",
733 __func__, pci_name(dev));
738 case pcie_deassert_reset:
739 eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
741 if (!(pe->type & EEH_PE_VF))
742 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);
743 eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev);
744 eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true);
747 eeh_pe_mark_isolated(pe);
748 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);
749 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
750 eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
751 if (!(pe->type & EEH_PE_VF))
752 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
753 eeh_ops->reset(pe, EEH_RESET_HOT);
755 case pcie_warm_reset:
756 eeh_pe_mark_isolated(pe);
757 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);
758 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
759 eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
760 if (!(pe->type & EEH_PE_VF))
761 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
762 eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
765 eeh_pe_state_clear(pe, EEH_PE_ISOLATED | EEH_PE_CFG_BLOCKED, true);
773 * eeh_set_dev_freset - Check the required reset for the indicated device
775 * @flag: return value
777 * Each device might have its preferred reset type: fundamental or
778 * hot reset. The routine is used to collected the information for
779 * the indicated device and its children so that the bunch of the
780 * devices could be reset properly.
782 static void eeh_set_dev_freset(struct eeh_dev *edev, void *flag)
785 unsigned int *freset = (unsigned int *)flag;
787 dev = eeh_dev_to_pci_dev(edev);
789 *freset |= dev->needs_freset;
792 static void eeh_pe_refreeze_passed(struct eeh_pe *root)
797 eeh_for_each_pe(root, pe) {
798 if (eeh_pe_passed(pe)) {
799 state = eeh_ops->get_state(pe, NULL);
801 (EEH_STATE_MMIO_ACTIVE | EEH_STATE_MMIO_ENABLED)) {
802 pr_info("EEH: Passed-through PE PHB#%x-PE#%x was thawed by reset, re-freezing for safety.\n",
803 pe->phb->global_number, pe->addr);
804 eeh_pe_set_option(pe, EEH_OPT_FREEZE_PE);
811 * eeh_pe_reset_full - Complete a full reset process on the indicated PE
813 * @include_passed: include passed-through devices?
815 * This function executes a full reset procedure on a PE, including setting
816 * the appropriate flags, performing a fundamental or hot reset, and then
817 * deactivating the reset status. It is designed to be used within the EEH
818 * subsystem, as opposed to eeh_pe_reset which is exported to drivers and
819 * only performs a single operation at a time.
821 * This function will attempt to reset a PE three times before failing.
823 int eeh_pe_reset_full(struct eeh_pe *pe, bool include_passed)
825 int reset_state = (EEH_PE_RESET | EEH_PE_CFG_BLOCKED);
826 int type = EEH_RESET_HOT;
827 unsigned int freset = 0;
828 int i, state = 0, ret;
831 * Determine the type of reset to perform - hot or fundamental.
832 * Hot reset is the default operation, unless any device under the
833 * PE requires a fundamental reset.
835 eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset);
838 type = EEH_RESET_FUNDAMENTAL;
840 /* Mark the PE as in reset state and block config space accesses */
841 eeh_pe_state_mark(pe, reset_state);
843 /* Make three attempts at resetting the bus */
844 for (i = 0; i < 3; i++) {
845 ret = eeh_pe_reset(pe, type, include_passed);
847 ret = eeh_pe_reset(pe, EEH_RESET_DEACTIVATE,
851 pr_warn("EEH: Failure %d resetting PHB#%x-PE#%x (attempt %d)\n\n",
852 state, pe->phb->global_number, pe->addr, i + 1);
856 pr_warn("EEH: PHB#%x-PE#%x: Successful reset (attempt %d)\n",
857 pe->phb->global_number, pe->addr, i + 1);
859 /* Wait until the PE is in a functioning state */
860 state = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
862 pr_warn("EEH: Unrecoverable slot failure on PHB#%x-PE#%x",
863 pe->phb->global_number, pe->addr);
864 ret = -ENOTRECOVERABLE;
867 if (eeh_state_active(state))
870 pr_warn("EEH: PHB#%x-PE#%x: Slot inactive after reset: 0x%x (attempt %d)\n",
871 pe->phb->global_number, pe->addr, state, i + 1);
874 /* Resetting the PE may have unfrozen child PEs. If those PEs have been
875 * (potentially) passed through to a guest, re-freeze them:
878 eeh_pe_refreeze_passed(pe);
880 eeh_pe_state_clear(pe, reset_state, true);
885 * eeh_save_bars - Save device bars
886 * @edev: PCI device associated EEH device
888 * Save the values of the device bars. Unlike the restore
889 * routine, this routine is *not* recursive. This is because
890 * PCI devices are added individually; but, for the restore,
891 * an entire slot is reset at a time.
893 void eeh_save_bars(struct eeh_dev *edev)
900 for (i = 0; i < 16; i++)
901 eeh_ops->read_config(edev, i * 4, 4, &edev->config_space[i]);
904 * For PCI bridges including root port, we need enable bus
905 * master explicitly. Otherwise, it can't fetch IODA table
906 * entries correctly. So we cache the bit in advance so that
907 * we can restore it after reset, either PHB range or PE range.
909 if (edev->mode & EEH_DEV_BRIDGE)
910 edev->config_space[1] |= PCI_COMMAND_MASTER;
913 static int eeh_reboot_notifier(struct notifier_block *nb,
914 unsigned long action, void *unused)
916 eeh_clear_flag(EEH_ENABLED);
920 static struct notifier_block eeh_reboot_nb = {
921 .notifier_call = eeh_reboot_notifier,
924 static int eeh_device_notifier(struct notifier_block *nb,
925 unsigned long action, void *data)
927 struct device *dev = data;
931 * Note: It's not possible to perform EEH device addition (i.e.
932 * {pseries,pnv}_pcibios_bus_add_device()) here because it depends on
933 * the device's resources, which have not yet been set up.
935 case BUS_NOTIFY_DEL_DEVICE:
936 eeh_remove_device(to_pci_dev(dev));
944 static struct notifier_block eeh_device_nb = {
945 .notifier_call = eeh_device_notifier,
949 * eeh_init - System wide EEH initialization
950 * @ops: struct to trace EEH operation callback functions
952 * It's the platform's job to call this from an arch_initcall().
954 int eeh_init(struct eeh_ops *ops)
956 struct pci_controller *hose, *tmp;
959 /* the platform should only initialise EEH once */
960 if (WARN_ON(eeh_ops))
966 /* Register reboot notifier */
967 ret = register_reboot_notifier(&eeh_reboot_nb);
969 pr_warn("%s: Failed to register reboot notifier (%d)\n",
974 ret = bus_register_notifier(&pci_bus_type, &eeh_device_nb);
976 pr_warn("%s: Failed to register bus notifier (%d)\n",
981 /* Initialize PHB PEs */
982 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
983 eeh_phb_pe_create(hose);
985 eeh_addr_cache_init();
987 /* Initialize EEH event */
988 return eeh_event_init();
992 * eeh_probe_device() - Perform EEH initialization for the indicated pci device
993 * @dev: pci device for which to set up EEH
995 * This routine must be used to complete EEH initialization for PCI
996 * devices that were added after system boot (e.g. hotplug, dlpar).
998 void eeh_probe_device(struct pci_dev *dev)
1000 struct eeh_dev *edev;
1002 pr_debug("EEH: Adding device %s\n", pci_name(dev));
1005 * pci_dev_to_eeh_dev() can only work if eeh_probe_dev() was
1006 * already called for this device.
1008 if (WARN_ON_ONCE(pci_dev_to_eeh_dev(dev))) {
1009 pci_dbg(dev, "Already bound to an eeh_dev!\n");
1013 edev = eeh_ops->probe(dev);
1015 pr_debug("EEH: Adding device failed\n");
1020 * FIXME: We rely on pcibios_release_device() to remove the
1021 * existing EEH state. The release function is only called if
1022 * the pci_dev's refcount drops to zero so if something is
1023 * keeping a ref to a device (e.g. a filesystem) we need to
1024 * remove the old EEH state.
1026 * FIXME: HEY MA, LOOK AT ME, NO LOCKING!
1028 if (edev->pdev && edev->pdev != dev) {
1029 eeh_pe_tree_remove(edev);
1030 eeh_addr_cache_rmv_dev(edev->pdev);
1031 eeh_sysfs_remove_device(edev->pdev);
1034 * We definitely should have the PCI device removed
1035 * though it wasn't correctly. So we needn't call
1036 * into error handler afterwards.
1038 edev->mode |= EEH_DEV_NO_HANDLER;
1041 /* bind the pdev and the edev together */
1043 dev->dev.archdata.edev = edev;
1044 eeh_addr_cache_insert_dev(dev);
1045 eeh_sysfs_add_device(dev);
1049 * eeh_remove_device - Undo EEH setup for the indicated pci device
1050 * @dev: pci device to be removed
1052 * This routine should be called when a device is removed from
1053 * a running system (e.g. by hotplug or dlpar). It unregisters
1054 * the PCI device from the EEH subsystem. I/O errors affecting
1055 * this device will no longer be detected after this call; thus,
1056 * i/o errors affecting this slot may leave this device unusable.
1058 void eeh_remove_device(struct pci_dev *dev)
1060 struct eeh_dev *edev;
1062 if (!dev || !eeh_enabled())
1064 edev = pci_dev_to_eeh_dev(dev);
1066 /* Unregister the device with the EEH/PCI address search system */
1067 dev_dbg(&dev->dev, "EEH: Removing device\n");
1069 if (!edev || !edev->pdev || !edev->pe) {
1070 dev_dbg(&dev->dev, "EEH: Device not referenced!\n");
1075 * During the hotplug for EEH error recovery, we need the EEH
1076 * device attached to the parent PE in order for BAR restore
1077 * a bit later. So we keep it for BAR restore and remove it
1078 * from the parent PE during the BAR resotre.
1083 * eeh_sysfs_remove_device() uses pci_dev_to_eeh_dev() so we need to
1084 * remove the sysfs files before clearing dev.archdata.edev
1086 if (edev->mode & EEH_DEV_SYSFS)
1087 eeh_sysfs_remove_device(dev);
1090 * We're removing from the PCI subsystem, that means
1091 * the PCI device driver can't support EEH or not
1092 * well. So we rely on hotplug completely to do recovery
1093 * for the specific PCI device.
1095 edev->mode |= EEH_DEV_NO_HANDLER;
1097 eeh_addr_cache_rmv_dev(dev);
1100 * The flag "in_error" is used to trace EEH devices for VFs
1101 * in error state or not. It's set in eeh_report_error(). If
1102 * it's not set, eeh_report_{reset,resume}() won't be called
1103 * for the VF EEH device.
1105 edev->in_error = false;
1106 dev->dev.archdata.edev = NULL;
1107 if (!(edev->pe->state & EEH_PE_KEEP))
1108 eeh_pe_tree_remove(edev);
1110 edev->mode |= EEH_DEV_DISCONNECTED;
1113 int eeh_unfreeze_pe(struct eeh_pe *pe)
1117 ret = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
1119 pr_warn("%s: Failure %d enabling IO on PHB#%x-PE#%x\n",
1120 __func__, ret, pe->phb->global_number, pe->addr);
1124 ret = eeh_pci_enable(pe, EEH_OPT_THAW_DMA);
1126 pr_warn("%s: Failure %d enabling DMA on PHB#%x-PE#%x\n",
1127 __func__, ret, pe->phb->global_number, pe->addr);
1135 static struct pci_device_id eeh_reset_ids[] = {
1136 { PCI_DEVICE(0x19a2, 0x0710) }, /* Emulex, BE */
1137 { PCI_DEVICE(0x10df, 0xe220) }, /* Emulex, Lancer */
1138 { PCI_DEVICE(0x14e4, 0x1657) }, /* Broadcom BCM5719 */
1142 static int eeh_pe_change_owner(struct eeh_pe *pe)
1144 struct eeh_dev *edev, *tmp;
1145 struct pci_dev *pdev;
1146 struct pci_device_id *id;
1149 /* Check PE state */
1150 ret = eeh_ops->get_state(pe, NULL);
1151 if (ret < 0 || ret == EEH_STATE_NOT_SUPPORT)
1154 /* Unfrozen PE, nothing to do */
1155 if (eeh_state_active(ret))
1158 /* Frozen PE, check if it needs PE level reset */
1159 eeh_pe_for_each_dev(pe, edev, tmp) {
1160 pdev = eeh_dev_to_pci_dev(edev);
1164 for (id = &eeh_reset_ids[0]; id->vendor != 0; id++) {
1165 if (id->vendor != PCI_ANY_ID &&
1166 id->vendor != pdev->vendor)
1168 if (id->device != PCI_ANY_ID &&
1169 id->device != pdev->device)
1171 if (id->subvendor != PCI_ANY_ID &&
1172 id->subvendor != pdev->subsystem_vendor)
1174 if (id->subdevice != PCI_ANY_ID &&
1175 id->subdevice != pdev->subsystem_device)
1178 return eeh_pe_reset_and_recover(pe);
1182 ret = eeh_unfreeze_pe(pe);
1184 eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true);
1189 * eeh_dev_open - Increase count of pass through devices for PE
1192 * Increase count of passed through devices for the indicated
1193 * PE. In the result, the EEH errors detected on the PE won't be
1194 * reported. The PE owner will be responsible for detection
1197 int eeh_dev_open(struct pci_dev *pdev)
1199 struct eeh_dev *edev;
1202 mutex_lock(&eeh_dev_mutex);
1204 /* No PCI device ? */
1208 /* No EEH device or PE ? */
1209 edev = pci_dev_to_eeh_dev(pdev);
1210 if (!edev || !edev->pe)
1214 * The PE might have been put into frozen state, but we
1215 * didn't detect that yet. The passed through PCI devices
1216 * in frozen PE won't work properly. Clear the frozen state
1219 ret = eeh_pe_change_owner(edev->pe);
1223 /* Increase PE's pass through count */
1224 atomic_inc(&edev->pe->pass_dev_cnt);
1225 mutex_unlock(&eeh_dev_mutex);
1229 mutex_unlock(&eeh_dev_mutex);
1232 EXPORT_SYMBOL_GPL(eeh_dev_open);
1235 * eeh_dev_release - Decrease count of pass through devices for PE
1238 * Decrease count of pass through devices for the indicated PE. If
1239 * there is no passed through device in PE, the EEH errors detected
1240 * on the PE will be reported and handled as usual.
1242 void eeh_dev_release(struct pci_dev *pdev)
1244 struct eeh_dev *edev;
1246 mutex_lock(&eeh_dev_mutex);
1248 /* No PCI device ? */
1252 /* No EEH device ? */
1253 edev = pci_dev_to_eeh_dev(pdev);
1254 if (!edev || !edev->pe || !eeh_pe_passed(edev->pe))
1257 /* Decrease PE's pass through count */
1258 WARN_ON(atomic_dec_if_positive(&edev->pe->pass_dev_cnt) < 0);
1259 eeh_pe_change_owner(edev->pe);
1261 mutex_unlock(&eeh_dev_mutex);
1263 EXPORT_SYMBOL(eeh_dev_release);
1265 #ifdef CONFIG_IOMMU_API
1267 static int dev_has_iommu_table(struct device *dev, void *data)
1269 struct pci_dev *pdev = to_pci_dev(dev);
1270 struct pci_dev **ppdev = data;
1275 if (device_iommu_mapped(dev)) {
1284 * eeh_iommu_group_to_pe - Convert IOMMU group to EEH PE
1285 * @group: IOMMU group
1287 * The routine is called to convert IOMMU group to EEH PE.
1289 struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group)
1291 struct pci_dev *pdev = NULL;
1292 struct eeh_dev *edev;
1295 /* No IOMMU group ? */
1299 ret = iommu_group_for_each_dev(group, &pdev, dev_has_iommu_table);
1303 /* No EEH device or PE ? */
1304 edev = pci_dev_to_eeh_dev(pdev);
1305 if (!edev || !edev->pe)
1310 EXPORT_SYMBOL_GPL(eeh_iommu_group_to_pe);
1312 #endif /* CONFIG_IOMMU_API */
1315 * eeh_pe_set_option - Set options for the indicated PE
1317 * @option: requested option
1319 * The routine is called to enable or disable EEH functionality
1320 * on the indicated PE, to enable IO or DMA for the frozen PE.
1322 int eeh_pe_set_option(struct eeh_pe *pe, int option)
1331 * EEH functionality could possibly be disabled, just
1332 * return error for the case. And the EEH functionality
1333 * isn't expected to be disabled on one specific PE.
1336 case EEH_OPT_ENABLE:
1337 if (eeh_enabled()) {
1338 ret = eeh_pe_change_owner(pe);
1343 case EEH_OPT_DISABLE:
1345 case EEH_OPT_THAW_MMIO:
1346 case EEH_OPT_THAW_DMA:
1347 case EEH_OPT_FREEZE_PE:
1348 if (!eeh_ops || !eeh_ops->set_option) {
1353 ret = eeh_pci_enable(pe, option);
1356 pr_debug("%s: Option %d out of range (%d, %d)\n",
1357 __func__, option, EEH_OPT_DISABLE, EEH_OPT_THAW_DMA);
1363 EXPORT_SYMBOL_GPL(eeh_pe_set_option);
1366 * eeh_pe_get_state - Retrieve PE's state
1369 * Retrieve the PE's state, which includes 3 aspects: enabled
1370 * DMA, enabled IO and asserted reset.
1372 int eeh_pe_get_state(struct eeh_pe *pe)
1374 int result, ret = 0;
1375 bool rst_active, dma_en, mmio_en;
1381 if (!eeh_ops || !eeh_ops->get_state)
1385 * If the parent PE is owned by the host kernel and is undergoing
1386 * error recovery, we should return the PE state as temporarily
1387 * unavailable so that the error recovery on the guest is suspended
1388 * until the recovery completes on the host.
1391 !(pe->state & EEH_PE_REMOVED) &&
1392 (pe->parent->state & (EEH_PE_ISOLATED | EEH_PE_RECOVERING)))
1393 return EEH_PE_STATE_UNAVAIL;
1395 result = eeh_ops->get_state(pe, NULL);
1396 rst_active = !!(result & EEH_STATE_RESET_ACTIVE);
1397 dma_en = !!(result & EEH_STATE_DMA_ENABLED);
1398 mmio_en = !!(result & EEH_STATE_MMIO_ENABLED);
1401 ret = EEH_PE_STATE_RESET;
1402 else if (dma_en && mmio_en)
1403 ret = EEH_PE_STATE_NORMAL;
1404 else if (!dma_en && !mmio_en)
1405 ret = EEH_PE_STATE_STOPPED_IO_DMA;
1406 else if (!dma_en && mmio_en)
1407 ret = EEH_PE_STATE_STOPPED_DMA;
1409 ret = EEH_PE_STATE_UNAVAIL;
1413 EXPORT_SYMBOL_GPL(eeh_pe_get_state);
1415 static int eeh_pe_reenable_devices(struct eeh_pe *pe, bool include_passed)
1417 struct eeh_dev *edev, *tmp;
1418 struct pci_dev *pdev;
1421 eeh_pe_restore_bars(pe);
1424 * Reenable PCI devices as the devices passed
1425 * through are always enabled before the reset.
1427 eeh_pe_for_each_dev(pe, edev, tmp) {
1428 pdev = eeh_dev_to_pci_dev(edev);
1432 ret = pci_reenable_device(pdev);
1434 pr_warn("%s: Failure %d reenabling %s\n",
1435 __func__, ret, pci_name(pdev));
1440 /* The PE is still in frozen state */
1441 if (include_passed || !eeh_pe_passed(pe)) {
1442 ret = eeh_unfreeze_pe(pe);
1444 pr_info("EEH: Note: Leaving passthrough PHB#%x-PE#%x frozen.\n",
1445 pe->phb->global_number, pe->addr);
1447 eeh_pe_state_clear(pe, EEH_PE_ISOLATED, include_passed);
1453 * eeh_pe_reset - Issue PE reset according to specified type
1455 * @option: reset type
1456 * @include_passed: include passed-through devices?
1458 * The routine is called to reset the specified PE with the
1459 * indicated type, either fundamental reset or hot reset.
1460 * PE reset is the most important part for error recovery.
1462 int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed)
1470 if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset)
1474 case EEH_RESET_DEACTIVATE:
1475 ret = eeh_ops->reset(pe, option);
1476 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, include_passed);
1480 ret = eeh_pe_reenable_devices(pe, include_passed);
1483 case EEH_RESET_FUNDAMENTAL:
1485 * Proactively freeze the PE to drop all MMIO access
1486 * during reset, which should be banned as it's always
1487 * cause recursive EEH error.
1489 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
1491 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
1492 ret = eeh_ops->reset(pe, option);
1495 pr_debug("%s: Unsupported option %d\n",
1502 EXPORT_SYMBOL_GPL(eeh_pe_reset);
1505 * eeh_pe_configure - Configure PCI bridges after PE reset
1508 * The routine is called to restore the PCI config space for
1509 * those PCI devices, especially PCI bridges affected by PE
1510 * reset issued previously.
1512 int eeh_pe_configure(struct eeh_pe *pe)
1522 EXPORT_SYMBOL_GPL(eeh_pe_configure);
1525 * eeh_pe_inject_err - Injecting the specified PCI error to the indicated PE
1526 * @pe: the indicated PE
1528 * @func: error function
1530 * @mask: address mask
1532 * The routine is called to inject the specified PCI error, which
1533 * is determined by @type and @func, to the indicated PE for
1536 int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
1537 unsigned long addr, unsigned long mask)
1543 /* Unsupported operation ? */
1544 if (!eeh_ops || !eeh_ops->err_inject)
1547 /* Check on PCI error type */
1548 if (type != EEH_ERR_TYPE_32 && type != EEH_ERR_TYPE_64)
1551 /* Check on PCI error function */
1552 if (func < EEH_ERR_FUNC_MIN || func > EEH_ERR_FUNC_MAX)
1555 return eeh_ops->err_inject(pe, type, func, addr, mask);
1557 EXPORT_SYMBOL_GPL(eeh_pe_inject_err);
1559 #ifdef CONFIG_PROC_FS
1560 static int proc_eeh_show(struct seq_file *m, void *v)
1562 if (!eeh_enabled()) {
1563 seq_printf(m, "EEH Subsystem is globally disabled\n");
1564 seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs);
1566 seq_printf(m, "EEH Subsystem is enabled\n");
1569 "no device node=%llu\n"
1570 "no config address=%llu\n"
1571 "check not wanted=%llu\n"
1572 "eeh_total_mmio_ffs=%llu\n"
1573 "eeh_false_positives=%llu\n"
1574 "eeh_slot_resets=%llu\n",
1575 eeh_stats.no_device,
1577 eeh_stats.no_cfg_addr,
1578 eeh_stats.ignored_check,
1579 eeh_stats.total_mmio_ffs,
1580 eeh_stats.false_positives,
1581 eeh_stats.slot_resets);
1586 #endif /* CONFIG_PROC_FS */
1588 #ifdef CONFIG_DEBUG_FS
1591 static struct pci_dev *eeh_debug_lookup_pdev(struct file *filp,
1592 const char __user *user_buf,
1593 size_t count, loff_t *ppos)
1595 uint32_t domain, bus, dev, fn;
1596 struct pci_dev *pdev;
1600 memset(buf, 0, sizeof(buf));
1601 ret = simple_write_to_buffer(buf, sizeof(buf)-1, ppos, user_buf, count);
1603 return ERR_PTR(-EFAULT);
1605 ret = sscanf(buf, "%x:%x:%x.%x", &domain, &bus, &dev, &fn);
1607 pr_err("%s: expected 4 args, got %d\n", __func__, ret);
1608 return ERR_PTR(-EINVAL);
1611 pdev = pci_get_domain_bus_and_slot(domain, bus, (dev << 3) | fn);
1613 return ERR_PTR(-ENODEV);
1618 static int eeh_enable_dbgfs_set(void *data, u64 val)
1621 eeh_clear_flag(EEH_FORCE_DISABLED);
1623 eeh_add_flag(EEH_FORCE_DISABLED);
1628 static int eeh_enable_dbgfs_get(void *data, u64 *val)
1637 DEFINE_DEBUGFS_ATTRIBUTE(eeh_enable_dbgfs_ops, eeh_enable_dbgfs_get,
1638 eeh_enable_dbgfs_set, "0x%llx\n");
1640 static ssize_t eeh_force_recover_write(struct file *filp,
1641 const char __user *user_buf,
1642 size_t count, loff_t *ppos)
1644 struct pci_controller *hose;
1645 uint32_t phbid, pe_no;
1650 ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count);
1655 * When PE is NULL the event is a "special" event. Rather than
1656 * recovering a specific PE it forces the EEH core to scan for failed
1657 * PHBs and recovers each. This needs to be done before any device
1658 * recoveries can occur.
1660 if (!strncmp(buf, "hwcheck", 7)) {
1661 __eeh_send_failure_event(NULL);
1665 ret = sscanf(buf, "%x:%x", &phbid, &pe_no);
1669 hose = pci_find_controller_for_domain(phbid);
1674 pe = eeh_pe_get(hose, pe_no);
1679 * We don't do any state checking here since the detection
1680 * process is async to the recovery process. The recovery
1681 * thread *should* not break even if we schedule a recovery
1682 * from an odd state (e.g. PE removed, or recovery of a
1685 __eeh_send_failure_event(pe);
1687 return ret < 0 ? ret : count;
1690 static const struct file_operations eeh_force_recover_fops = {
1691 .open = simple_open,
1692 .llseek = no_llseek,
1693 .write = eeh_force_recover_write,
1696 static ssize_t eeh_debugfs_dev_usage(struct file *filp,
1697 char __user *user_buf,
1698 size_t count, loff_t *ppos)
1700 static const char usage[] = "input format: <domain>:<bus>:<dev>.<fn>\n";
1702 return simple_read_from_buffer(user_buf, count, ppos,
1703 usage, sizeof(usage) - 1);
1706 static ssize_t eeh_dev_check_write(struct file *filp,
1707 const char __user *user_buf,
1708 size_t count, loff_t *ppos)
1710 struct pci_dev *pdev;
1711 struct eeh_dev *edev;
1714 pdev = eeh_debug_lookup_pdev(filp, user_buf, count, ppos);
1716 return PTR_ERR(pdev);
1718 edev = pci_dev_to_eeh_dev(pdev);
1720 pci_err(pdev, "No eeh_dev for this device!\n");
1725 ret = eeh_dev_check_failure(edev);
1726 pci_info(pdev, "eeh_dev_check_failure(%s) = %d\n",
1727 pci_name(pdev), ret);
1734 static const struct file_operations eeh_dev_check_fops = {
1735 .open = simple_open,
1736 .llseek = no_llseek,
1737 .write = eeh_dev_check_write,
1738 .read = eeh_debugfs_dev_usage,
1741 static int eeh_debugfs_break_device(struct pci_dev *pdev)
1743 struct resource *bar = NULL;
1744 void __iomem *mapped;
1748 /* Do we have an MMIO BAR to disable? */
1749 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
1750 struct resource *r = &pdev->resource[i];
1752 if (!r->flags || !r->start)
1754 if (r->flags & IORESOURCE_IO)
1756 if (r->flags & IORESOURCE_UNSET)
1764 pci_err(pdev, "Unable to find Memory BAR to cause EEH with\n");
1768 pci_err(pdev, "Going to break: %pR\n", bar);
1770 if (pdev->is_virtfn) {
1771 #ifndef CONFIG_PCI_IOV
1775 * VFs don't have a per-function COMMAND register, so the best
1776 * we can do is clear the Memory Space Enable bit in the PF's
1777 * SRIOV control reg.
1779 * Unfortunately, this requires that we have a PF (i.e doesn't
1780 * work for a passed-through VF) and it has the potential side
1781 * effect of also causing an EEH on every other VF under the
1784 pdev = pdev->physfn;
1786 return -ENXIO; /* passed through VFs have no PF */
1788 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1789 pos += PCI_SRIOV_CTRL;
1790 bit = PCI_SRIOV_CTRL_MSE;
1791 #endif /* !CONFIG_PCI_IOV */
1793 bit = PCI_COMMAND_MEMORY;
1800 * 1. Disable Memory space.
1802 * 2. Perform an MMIO to the device. This should result in an error
1803 * (CA / UR) being raised by the device which results in an EEH
1804 * PE freeze. Using the in_8() accessor skips the eeh detection hook
1805 * so the freeze hook so the EEH Detection machinery won't be
1806 * triggered here. This is to match the usual behaviour of EEH
1807 * where the HW will asynchronously freeze a PE and it's up to
1808 * the kernel to notice and deal with it.
1810 * 3. Turn Memory space back on. This is more important for VFs
1811 * since recovery will probably fail if we don't. For normal
1812 * the COMMAND register is reset as a part of re-initialising
1815 * Breaking stuff is the point so who cares if it's racy ;)
1817 pci_read_config_word(pdev, pos, &old);
1819 mapped = ioremap(bar->start, PAGE_SIZE);
1821 pci_err(pdev, "Unable to map MMIO BAR %pR\n", bar);
1825 pci_write_config_word(pdev, pos, old & ~bit);
1827 pci_write_config_word(pdev, pos, old);
1834 static ssize_t eeh_dev_break_write(struct file *filp,
1835 const char __user *user_buf,
1836 size_t count, loff_t *ppos)
1838 struct pci_dev *pdev;
1841 pdev = eeh_debug_lookup_pdev(filp, user_buf, count, ppos);
1843 return PTR_ERR(pdev);
1845 ret = eeh_debugfs_break_device(pdev);
1854 static const struct file_operations eeh_dev_break_fops = {
1855 .open = simple_open,
1856 .llseek = no_llseek,
1857 .write = eeh_dev_break_write,
1858 .read = eeh_debugfs_dev_usage,
1861 static ssize_t eeh_dev_can_recover(struct file *filp,
1862 const char __user *user_buf,
1863 size_t count, loff_t *ppos)
1865 struct pci_driver *drv;
1866 struct pci_dev *pdev;
1869 pdev = eeh_debug_lookup_pdev(filp, user_buf, count, ppos);
1871 return PTR_ERR(pdev);
1874 * In order for error recovery to work the driver needs to implement
1875 * .error_detected(), so it can quiesce IO to the device, and
1876 * .slot_reset() so it can re-initialise the device after a reset.
1878 * Ideally they'd implement .resume() too, but some drivers which
1879 * we need to support (notably IPR) don't so I guess we can tolerate
1882 * .mmio_enabled() is mostly there as a work-around for devices which
1883 * take forever to re-init after a hot reset. Implementing that is
1884 * strictly optional.
1886 drv = pci_dev_driver(pdev);
1889 drv->err_handler->error_detected &&
1890 drv->err_handler->slot_reset) {
1901 static const struct file_operations eeh_dev_can_recover_fops = {
1902 .open = simple_open,
1903 .llseek = no_llseek,
1904 .write = eeh_dev_can_recover,
1905 .read = eeh_debugfs_dev_usage,
1910 static int __init eeh_init_proc(void)
1912 if (machine_is(pseries) || machine_is(powernv)) {
1913 proc_create_single("powerpc/eeh", 0, NULL, proc_eeh_show);
1914 #ifdef CONFIG_DEBUG_FS
1915 debugfs_create_file_unsafe("eeh_enable", 0600,
1916 arch_debugfs_dir, NULL,
1917 &eeh_enable_dbgfs_ops);
1918 debugfs_create_u32("eeh_max_freezes", 0600,
1919 arch_debugfs_dir, &eeh_max_freezes);
1920 debugfs_create_bool("eeh_disable_recovery", 0600,
1922 &eeh_debugfs_no_recover);
1923 debugfs_create_file_unsafe("eeh_dev_check", 0600,
1924 arch_debugfs_dir, NULL,
1925 &eeh_dev_check_fops);
1926 debugfs_create_file_unsafe("eeh_dev_break", 0600,
1927 arch_debugfs_dir, NULL,
1928 &eeh_dev_break_fops);
1929 debugfs_create_file_unsafe("eeh_force_recover", 0600,
1930 arch_debugfs_dir, NULL,
1931 &eeh_force_recover_fops);
1932 debugfs_create_file_unsafe("eeh_dev_can_recover", 0600,
1933 arch_debugfs_dir, NULL,
1934 &eeh_dev_can_recover_fops);
1935 eeh_cache_debugfs_init();
1941 __initcall(eeh_init_proc);