2 * Copyright IBM Corporation 2001, 2005, 2006
3 * Copyright Dave Engebretsen & Todd Inglett 2001
4 * Copyright Linas Vepstas 2005, 2006
5 * Copyright 2001-2012 IBM Corporation.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com>
24 #include <linux/delay.h>
25 #include <linux/debugfs.h>
26 #include <linux/sched.h>
27 #include <linux/init.h>
28 #include <linux/list.h>
29 #include <linux/pci.h>
30 #include <linux/iommu.h>
31 #include <linux/proc_fs.h>
32 #include <linux/rbtree.h>
33 #include <linux/reboot.h>
34 #include <linux/seq_file.h>
35 #include <linux/spinlock.h>
36 #include <linux/export.h>
39 #include <linux/atomic.h>
40 #include <asm/debug.h>
42 #include <asm/eeh_event.h>
44 #include <asm/iommu.h>
45 #include <asm/machdep.h>
46 #include <asm/ppc-pci.h>
51 * EEH, or "Extended Error Handling" is a PCI bridge technology for
52 * dealing with PCI bus errors that can't be dealt with within the
53 * usual PCI framework, except by check-stopping the CPU. Systems
54 * that are designed for high-availability/reliability cannot afford
55 * to crash due to a "mere" PCI error, thus the need for EEH.
56 * An EEH-capable bridge operates by converting a detected error
57 * into a "slot freeze", taking the PCI adapter off-line, making
58 * the slot behave, from the OS'es point of view, as if the slot
59 * were "empty": all reads return 0xff's and all writes are silently
60 * ignored. EEH slot isolation events can be triggered by parity
61 * errors on the address or data busses (e.g. during posted writes),
62 * which in turn might be caused by low voltage on the bus, dust,
63 * vibration, humidity, radioactivity or plain-old failed hardware.
65 * Note, however, that one of the leading causes of EEH slot
66 * freeze events are buggy device drivers, buggy device microcode,
67 * or buggy device hardware. This is because any attempt by the
68 * device to bus-master data to a memory address that is not
69 * assigned to the device will trigger a slot freeze. (The idea
70 * is to prevent devices-gone-wild from corrupting system memory).
71 * Buggy hardware/drivers will have a miserable time co-existing
74 * Ideally, a PCI device driver, when suspecting that an isolation
75 * event has occurred (e.g. by reading 0xff's), will then ask EEH
76 * whether this is the case, and then take appropriate steps to
77 * reset the PCI slot, the PCI device, and then resume operations.
78 * However, until that day, the checking is done here, with the
79 * eeh_check_failure() routine embedded in the MMIO macros. If
80 * the slot is found to be isolated, an "EEH Event" is synthesized
81 * and sent out for processing.
84 /* If a device driver keeps reading an MMIO register in an interrupt
85 * handler after a slot isolation event, it might be broken.
86 * This sets the threshold for how many read attempts we allow
87 * before printing an error message.
89 #define EEH_MAX_FAILS 2100000
91 /* Time to wait for a PCI slot to report status, in milliseconds */
92 #define PCI_BUS_RESET_WAIT_MSEC (5*60*1000)
95 * EEH probe mode support, which is part of the flags,
96 * is to support multiple platforms for EEH. Some platforms
97 * like pSeries do PCI emunation based on device tree.
98 * However, other platforms like powernv probe PCI devices
99 * from hardware. The flag is used to distinguish that.
100 * In addition, struct eeh_ops::probe would be invoked for
101 * particular OF node or PCI device so that the corresponding
102 * PE would be created there.
104 int eeh_subsystem_flags;
105 EXPORT_SYMBOL(eeh_subsystem_flags);
108 * EEH allowed maximal frozen times. If one particular PE's
109 * frozen count in last hour exceeds this limit, the PE will
110 * be forced to be offline permanently.
112 int eeh_max_freezes = 5;
114 /* Platform dependent EEH operations */
115 struct eeh_ops *eeh_ops = NULL;
117 /* Lock to avoid races due to multiple reports of an error */
118 DEFINE_RAW_SPINLOCK(confirm_error_lock);
120 /* Lock to protect passed flags */
121 static DEFINE_MUTEX(eeh_dev_mutex);
123 /* Buffer for reporting pci register dumps. Its here in BSS, and
124 * not dynamically alloced, so that it ends up in RMO where RTAS
127 #define EEH_PCI_REGS_LOG_LEN 8192
128 static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN];
131 * The struct is used to maintain the EEH global statistic
132 * information. Besides, the EEH global statistics will be
133 * exported to user space through procfs
136 u64 no_device; /* PCI device not found */
137 u64 no_dn; /* OF node not found */
138 u64 no_cfg_addr; /* Config address not found */
139 u64 ignored_check; /* EEH check skipped */
140 u64 total_mmio_ffs; /* Total EEH checks */
141 u64 false_positives; /* Unnecessary EEH checks */
142 u64 slot_resets; /* PE reset */
145 static struct eeh_stats eeh_stats;
147 static int __init eeh_setup(char *str)
149 if (!strcmp(str, "off"))
150 eeh_add_flag(EEH_FORCE_DISABLED);
151 else if (!strcmp(str, "early_log"))
152 eeh_add_flag(EEH_EARLY_DUMP_LOG);
156 __setup("eeh=", eeh_setup);
159 * This routine captures assorted PCI configuration space data
160 * for the indicated PCI device, and puts them into a buffer
161 * for RTAS error logging.
163 static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len)
165 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
171 n += scnprintf(buf+n, len-n, "%04x:%02x:%02x:%01x\n",
172 edev->phb->global_number, pdn->busno,
173 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
174 pr_warn("EEH: of node=%04x:%02x:%02x:%01x\n",
175 edev->phb->global_number, pdn->busno,
176 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
178 eeh_ops->read_config(pdn, PCI_VENDOR_ID, 4, &cfg);
179 n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg);
180 pr_warn("EEH: PCI device/vendor: %08x\n", cfg);
182 eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cfg);
183 n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg);
184 pr_warn("EEH: PCI cmd/status register: %08x\n", cfg);
186 /* Gather bridge-specific registers */
187 if (edev->mode & EEH_DEV_BRIDGE) {
188 eeh_ops->read_config(pdn, PCI_SEC_STATUS, 2, &cfg);
189 n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg);
190 pr_warn("EEH: Bridge secondary status: %04x\n", cfg);
192 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg);
193 n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg);
194 pr_warn("EEH: Bridge control: %04x\n", cfg);
197 /* Dump out the PCI-X command and status regs */
198 cap = edev->pcix_cap;
200 eeh_ops->read_config(pdn, cap, 4, &cfg);
201 n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg);
202 pr_warn("EEH: PCI-X cmd: %08x\n", cfg);
204 eeh_ops->read_config(pdn, cap+4, 4, &cfg);
205 n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg);
206 pr_warn("EEH: PCI-X status: %08x\n", cfg);
209 /* If PCI-E capable, dump PCI-E cap 10 */
210 cap = edev->pcie_cap;
212 n += scnprintf(buf+n, len-n, "pci-e cap10:\n");
213 pr_warn("EEH: PCI-E capabilities and status follow:\n");
215 for (i=0; i<=8; i++) {
216 eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);
217 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
221 pr_warn("%s\n", buffer);
223 l = scnprintf(buffer, sizeof(buffer),
224 "EEH: PCI-E %02x: %08x ",
227 l += scnprintf(buffer+l, sizeof(buffer)-l,
233 pr_warn("%s\n", buffer);
236 /* If AER capable, dump it */
239 n += scnprintf(buf+n, len-n, "pci-e AER:\n");
240 pr_warn("EEH: PCI-E AER capability register set follows:\n");
242 for (i=0; i<=13; i++) {
243 eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);
244 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
248 pr_warn("%s\n", buffer);
250 l = scnprintf(buffer, sizeof(buffer),
251 "EEH: PCI-E AER %02x: %08x ",
254 l += scnprintf(buffer+l, sizeof(buffer)-l,
259 pr_warn("%s\n", buffer);
265 static void *eeh_dump_pe_log(void *data, void *flag)
267 struct eeh_pe *pe = data;
268 struct eeh_dev *edev, *tmp;
271 /* If the PE's config space is blocked, 0xFF's will be
272 * returned. It's pointless to collect the log in this
275 if (pe->state & EEH_PE_CFG_BLOCKED)
278 eeh_pe_for_each_dev(pe, edev, tmp)
279 *plen += eeh_dump_dev_log(edev, pci_regs_buf + *plen,
280 EEH_PCI_REGS_LOG_LEN - *plen);
286 * eeh_slot_error_detail - Generate combined log including driver log and error log
288 * @severity: temporary or permanent error log
290 * This routine should be called to generate the combined log, which
291 * is comprised of driver log and error log. The driver log is figured
292 * out from the config space of the corresponding PCI device, while
293 * the error log is fetched through platform dependent function call.
295 void eeh_slot_error_detail(struct eeh_pe *pe, int severity)
300 * When the PHB is fenced or dead, it's pointless to collect
301 * the data from PCI config space because it should return
302 * 0xFF's. For ER, we still retrieve the data from the PCI
305 * For pHyp, we have to enable IO for log retrieval. Otherwise,
306 * 0xFF's is always returned from PCI config space.
308 * When the @severity is EEH_LOG_PERM, the PE is going to be
309 * removed. Prior to that, the drivers for devices included in
310 * the PE will be closed. The drivers rely on working IO path
311 * to bring the devices to quiet state. Otherwise, PCI traffic
312 * from those devices after they are removed is like to cause
313 * another unexpected EEH error.
315 if (!(pe->type & EEH_PE_PHB)) {
316 if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG) ||
317 severity == EEH_LOG_PERM)
318 eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
321 * The config space of some PCI devices can't be accessed
322 * when their PEs are in frozen state. Otherwise, fenced
323 * PHB might be seen. Those PEs are identified with flag
324 * EEH_PE_CFG_RESTRICTED, indicating EEH_PE_CFG_BLOCKED
325 * is set automatically when the PE is put to EEH_PE_ISOLATED.
327 * Restoring BARs possibly triggers PCI config access in
328 * (OPAL) firmware and then causes fenced PHB. If the
329 * PCI config is blocked with flag EEH_PE_CFG_BLOCKED, it's
330 * pointless to restore BARs and dump config space.
332 eeh_ops->configure_bridge(pe);
333 if (!(pe->state & EEH_PE_CFG_BLOCKED)) {
334 eeh_pe_restore_bars(pe);
337 eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen);
341 eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
345 * eeh_token_to_phys - Convert EEH address token to phys address
346 * @token: I/O token, should be address in the form 0xA....
348 * This routine should be called to convert virtual I/O address
351 static inline unsigned long eeh_token_to_phys(unsigned long token)
358 * We won't find hugepages here(this is iomem). Hence we are not
359 * worried about _PAGE_SPLITTING/collapse. Also we will not hit
360 * page table free, because of init_mm.
362 ptep = __find_linux_pte_or_hugepte(init_mm.pgd, token,
363 NULL, &hugepage_shift);
369 /* On radix we can do hugepage mappings for io, so handle that */
371 hugepage_shift = PAGE_SHIFT;
374 pa |= token & ((1ul << hugepage_shift) - 1);
379 * On PowerNV platform, we might already have fenced PHB there.
380 * For that case, it's meaningless to recover frozen PE. Intead,
381 * We have to handle fenced PHB firstly.
383 static int eeh_phb_check_failure(struct eeh_pe *pe)
385 struct eeh_pe *phb_pe;
389 if (!eeh_has_flag(EEH_PROBE_MODE_DEV))
392 /* Find the PHB PE */
393 phb_pe = eeh_phb_pe_get(pe->phb);
395 pr_warn("%s Can't find PE for PHB#%d\n",
396 __func__, pe->phb->global_number);
400 /* If the PHB has been in problematic state */
401 eeh_serialize_lock(&flags);
402 if (phb_pe->state & EEH_PE_ISOLATED) {
407 /* Check PHB state */
408 ret = eeh_ops->get_state(phb_pe, NULL);
410 (ret == EEH_STATE_NOT_SUPPORT) ||
411 (ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) ==
412 (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) {
417 /* Isolate the PHB and send event */
418 eeh_pe_state_mark(phb_pe, EEH_PE_ISOLATED);
419 eeh_serialize_unlock(flags);
421 pr_err("EEH: PHB#%x failure detected, location: %s\n",
422 phb_pe->phb->global_number, eeh_pe_loc_get(phb_pe));
424 eeh_send_failure_event(phb_pe);
428 eeh_serialize_unlock(flags);
433 * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze
436 * Check for an EEH failure for the given device node. Call this
437 * routine if the result of a read was all 0xff's and you want to
438 * find out if this is due to an EEH slot freeze. This routine
439 * will query firmware for the EEH status.
441 * Returns 0 if there has not been an EEH error; otherwise returns
442 * a non-zero value and queues up a slot isolation event notification.
444 * It is safe to call this routine in an interrupt context.
446 int eeh_dev_check_failure(struct eeh_dev *edev)
449 int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
453 struct eeh_pe *pe, *parent_pe, *phb_pe;
455 const char *location = NULL;
457 eeh_stats.total_mmio_ffs++;
466 dev = eeh_dev_to_pci_dev(edev);
467 pe = eeh_dev_to_pe(edev);
469 /* Access to IO BARs might get this far and still not want checking. */
471 eeh_stats.ignored_check++;
472 pr_debug("EEH: Ignored check for %s\n",
477 if (!pe->addr && !pe->config_addr) {
478 eeh_stats.no_cfg_addr++;
483 * On PowerNV platform, we might already have fenced PHB
484 * there and we need take care of that firstly.
486 ret = eeh_phb_check_failure(pe);
491 * If the PE isn't owned by us, we shouldn't check the
492 * state. Instead, let the owner handle it if the PE has
495 if (eeh_pe_passed(pe))
498 /* If we already have a pending isolation event for this
499 * slot, we know it's bad already, we don't need to check.
500 * Do this checking under a lock; as multiple PCI devices
501 * in one slot might report errors simultaneously, and we
502 * only want one error recovery routine running.
504 eeh_serialize_lock(&flags);
506 if (pe->state & EEH_PE_ISOLATED) {
508 if (pe->check_count % EEH_MAX_FAILS == 0) {
509 pdn = eeh_dev_to_pdn(edev);
511 location = of_get_property(pdn->node, "ibm,loc-code", NULL);
512 printk(KERN_ERR "EEH: %d reads ignored for recovering device at "
513 "location=%s driver=%s pci addr=%s\n",
515 location ? location : "unknown",
516 eeh_driver_name(dev), eeh_pci_name(dev));
517 printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n",
518 eeh_driver_name(dev));
525 * Now test for an EEH failure. This is VERY expensive.
526 * Note that the eeh_config_addr may be a parent device
527 * in the case of a device behind a bridge, or it may be
528 * function zero of a multi-function device.
529 * In any case they must share a common PHB.
531 ret = eeh_ops->get_state(pe, NULL);
533 /* Note that config-io to empty slots may fail;
534 * they are empty when they don't have children.
535 * We will punt with the following conditions: Failure to get
536 * PE's state, EEH not support and Permanently unavailable
537 * state, PE is in good state.
540 (ret == EEH_STATE_NOT_SUPPORT) ||
541 ((ret & active_flags) == active_flags)) {
542 eeh_stats.false_positives++;
543 pe->false_positives++;
549 * It should be corner case that the parent PE has been
550 * put into frozen state as well. We should take care
553 parent_pe = pe->parent;
555 /* Hit the ceiling ? */
556 if (parent_pe->type & EEH_PE_PHB)
559 /* Frozen parent PE ? */
560 ret = eeh_ops->get_state(parent_pe, NULL);
562 (ret & active_flags) != active_flags)
565 /* Next parent level */
566 parent_pe = parent_pe->parent;
569 eeh_stats.slot_resets++;
571 /* Avoid repeated reports of this failure, including problems
572 * with other functions on this device, and functions under
575 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
576 eeh_serialize_unlock(flags);
578 /* Most EEH events are due to device driver bugs. Having
579 * a stack trace will help the device-driver authors figure
580 * out what happened. So print that out.
582 phb_pe = eeh_phb_pe_get(pe->phb);
583 pr_err("EEH: Frozen PHB#%x-PE#%x detected\n",
584 pe->phb->global_number, pe->addr);
585 pr_err("EEH: PE location: %s, PHB location: %s\n",
586 eeh_pe_loc_get(pe), eeh_pe_loc_get(phb_pe));
589 eeh_send_failure_event(pe);
594 eeh_serialize_unlock(flags);
598 EXPORT_SYMBOL_GPL(eeh_dev_check_failure);
601 * eeh_check_failure - Check if all 1's data is due to EEH slot freeze
602 * @token: I/O address
604 * Check for an EEH failure at the given I/O address. Call this
605 * routine if the result of a read was all 0xff's and you want to
606 * find out if this is due to an EEH slot freeze event. This routine
607 * will query firmware for the EEH status.
609 * Note this routine is safe to call in an interrupt context.
611 int eeh_check_failure(const volatile void __iomem *token)
614 struct eeh_dev *edev;
616 /* Finding the phys addr + pci device; this is pretty quick. */
617 addr = eeh_token_to_phys((unsigned long __force) token);
618 edev = eeh_addr_cache_get_dev(addr);
620 eeh_stats.no_device++;
624 return eeh_dev_check_failure(edev);
626 EXPORT_SYMBOL(eeh_check_failure);
630 * eeh_pci_enable - Enable MMIO or DMA transfers for this slot
633 * This routine should be called to reenable frozen MMIO or DMA
634 * so that it would work correctly again. It's useful while doing
635 * recovery or log collection on the indicated device.
637 int eeh_pci_enable(struct eeh_pe *pe, int function)
642 * pHyp doesn't allow to enable IO or DMA on unfrozen PE.
643 * Also, it's pointless to enable them on unfrozen PE. So
644 * we have to check before enabling IO or DMA.
647 case EEH_OPT_THAW_MMIO:
648 active_flag = EEH_STATE_MMIO_ACTIVE | EEH_STATE_MMIO_ENABLED;
650 case EEH_OPT_THAW_DMA:
651 active_flag = EEH_STATE_DMA_ACTIVE;
653 case EEH_OPT_DISABLE:
655 case EEH_OPT_FREEZE_PE:
659 pr_warn("%s: Invalid function %d\n",
665 * Check if IO or DMA has been enabled before
669 rc = eeh_ops->get_state(pe, NULL);
673 /* Needn't enable it at all */
674 if (rc == EEH_STATE_NOT_SUPPORT)
677 /* It's already enabled */
678 if (rc & active_flag)
683 /* Issue the request */
684 rc = eeh_ops->set_option(pe, function);
686 pr_warn("%s: Unexpected state change %d on "
687 "PHB#%d-PE#%x, err=%d\n",
688 __func__, function, pe->phb->global_number,
691 /* Check if the request is finished successfully */
693 rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
697 if (rc & active_flag)
706 static void *eeh_disable_and_save_dev_state(void *data, void *userdata)
708 struct eeh_dev *edev = data;
709 struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
710 struct pci_dev *dev = userdata;
713 * The caller should have disabled and saved the
714 * state for the specified device
716 if (!pdev || pdev == dev)
719 /* Ensure we have D0 power state */
720 pci_set_power_state(pdev, PCI_D0);
722 /* Save device state */
723 pci_save_state(pdev);
726 * Disable device to avoid any DMA traffic and
727 * interrupt from the device
729 pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
734 static void *eeh_restore_dev_state(void *data, void *userdata)
736 struct eeh_dev *edev = data;
737 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
738 struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
739 struct pci_dev *dev = userdata;
744 /* Apply customization from firmware */
745 if (pdn && eeh_ops->restore_config)
746 eeh_ops->restore_config(pdn);
748 /* The caller should restore state for the specified device */
750 pci_restore_state(pdev);
756 * pcibios_set_pcie_slot_reset - Set PCI-E reset state
757 * @dev: pci device struct
758 * @state: reset state to enter
763 int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
765 struct eeh_dev *edev = pci_dev_to_eeh_dev(dev);
766 struct eeh_pe *pe = eeh_dev_to_pe(edev);
769 pr_err("%s: No PE found on PCI device %s\n",
770 __func__, pci_name(dev));
775 case pcie_deassert_reset:
776 eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
777 eeh_unfreeze_pe(pe, false);
778 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);
779 eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev);
780 eeh_pe_state_clear(pe, EEH_PE_ISOLATED);
783 eeh_pe_state_mark_with_cfg(pe, EEH_PE_ISOLATED);
784 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
785 eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
786 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
787 eeh_ops->reset(pe, EEH_RESET_HOT);
789 case pcie_warm_reset:
790 eeh_pe_state_mark_with_cfg(pe, EEH_PE_ISOLATED);
791 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
792 eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
793 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
794 eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
797 eeh_pe_state_clear(pe, EEH_PE_ISOLATED | EEH_PE_CFG_BLOCKED);
805 * eeh_set_pe_freset - Check the required reset for the indicated device
807 * @flag: return value
809 * Each device might have its preferred reset type: fundamental or
810 * hot reset. The routine is used to collected the information for
811 * the indicated device and its children so that the bunch of the
812 * devices could be reset properly.
814 static void *eeh_set_dev_freset(void *data, void *flag)
817 unsigned int *freset = (unsigned int *)flag;
818 struct eeh_dev *edev = (struct eeh_dev *)data;
820 dev = eeh_dev_to_pci_dev(edev);
822 *freset |= dev->needs_freset;
828 * eeh_reset_pe_once - Assert the pci #RST line for 1/4 second
831 * Assert the PCI #RST line for 1/4 second.
833 static void eeh_reset_pe_once(struct eeh_pe *pe)
835 unsigned int freset = 0;
837 /* Determine type of EEH reset required for
838 * Partitionable Endpoint, a hot-reset (1)
839 * or a fundamental reset (3).
840 * A fundamental reset required by any device under
841 * Partitionable Endpoint trumps hot-reset.
843 eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset);
846 eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
848 eeh_ops->reset(pe, EEH_RESET_HOT);
850 eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
854 * eeh_reset_pe - Reset the indicated PE
857 * This routine should be called to reset indicated device, including
858 * PE. A PE might include multiple PCI devices and sometimes PCI bridges
859 * might be involved as well.
861 int eeh_reset_pe(struct eeh_pe *pe)
863 int flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
866 /* Mark as reset and block config space */
867 eeh_pe_state_mark(pe, EEH_PE_RESET | EEH_PE_CFG_BLOCKED);
869 /* Take three shots at resetting the bus */
870 for (i = 0; i < 3; i++) {
871 eeh_reset_pe_once(pe);
874 * EEH_PE_ISOLATED is expected to be removed after
877 state = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
878 if ((state & flags) == flags) {
884 pr_warn("%s: Unrecoverable slot failure on PHB#%d-PE#%x",
885 __func__, pe->phb->global_number, pe->addr);
886 ret = -ENOTRECOVERABLE;
890 /* We might run out of credits */
892 pr_warn("%s: Failure %d resetting PHB#%x-PE#%x\n (%d)\n",
893 __func__, state, pe->phb->global_number, pe->addr, (i + 1));
897 eeh_pe_state_clear(pe, EEH_PE_RESET | EEH_PE_CFG_BLOCKED);
902 * eeh_save_bars - Save device bars
903 * @edev: PCI device associated EEH device
905 * Save the values of the device bars. Unlike the restore
906 * routine, this routine is *not* recursive. This is because
907 * PCI devices are added individually; but, for the restore,
908 * an entire slot is reset at a time.
910 void eeh_save_bars(struct eeh_dev *edev)
915 pdn = eeh_dev_to_pdn(edev);
919 for (i = 0; i < 16; i++)
920 eeh_ops->read_config(pdn, i * 4, 4, &edev->config_space[i]);
923 * For PCI bridges including root port, we need enable bus
924 * master explicitly. Otherwise, it can't fetch IODA table
925 * entries correctly. So we cache the bit in advance so that
926 * we can restore it after reset, either PHB range or PE range.
928 if (edev->mode & EEH_DEV_BRIDGE)
929 edev->config_space[1] |= PCI_COMMAND_MASTER;
933 * eeh_ops_register - Register platform dependent EEH operations
934 * @ops: platform dependent EEH operations
936 * Register the platform dependent EEH operation callback
937 * functions. The platform should call this function before
938 * any other EEH operations.
940 int __init eeh_ops_register(struct eeh_ops *ops)
943 pr_warn("%s: Invalid EEH ops name for %p\n",
948 if (eeh_ops && eeh_ops != ops) {
949 pr_warn("%s: EEH ops of platform %s already existing (%s)\n",
950 __func__, eeh_ops->name, ops->name);
960 * eeh_ops_unregister - Unreigster platform dependent EEH operations
961 * @name: name of EEH platform operations
963 * Unregister the platform dependent EEH operation callback
966 int __exit eeh_ops_unregister(const char *name)
968 if (!name || !strlen(name)) {
969 pr_warn("%s: Invalid EEH ops name\n",
974 if (eeh_ops && !strcmp(eeh_ops->name, name)) {
982 static int eeh_reboot_notifier(struct notifier_block *nb,
983 unsigned long action, void *unused)
985 eeh_clear_flag(EEH_ENABLED);
989 static struct notifier_block eeh_reboot_nb = {
990 .notifier_call = eeh_reboot_notifier,
994 * eeh_init - EEH initialization
996 * Initialize EEH by trying to enable it for all of the adapters in the system.
997 * As a side effect we can determine here if eeh is supported at all.
998 * Note that we leave EEH on so failed config cycles won't cause a machine
999 * check. If a user turns off EEH for a particular adapter they are really
1000 * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't
1001 * grant access to a slot if EEH isn't enabled, and so we always enable
1002 * EEH for all slots/all devices.
1004 * The eeh-force-off option disables EEH checking globally, for all slots.
1005 * Even if force-off is set, the EEH hardware is still enabled, so that
1006 * newer systems can boot.
1010 struct pci_controller *hose, *tmp;
1016 * We have to delay the initialization on PowerNV after
1017 * the PCI hierarchy tree has been built because the PEs
1018 * are figured out based on PCI devices instead of device
1021 if (machine_is(powernv) && cnt++ <= 0)
1024 /* Register reboot notifier */
1025 ret = register_reboot_notifier(&eeh_reboot_nb);
1027 pr_warn("%s: Failed to register notifier (%d)\n",
1032 /* call platform initialization function */
1034 pr_warn("%s: Platform EEH operation not found\n",
1037 } else if ((ret = eeh_ops->init()))
1040 /* Initialize EEH event */
1041 ret = eeh_event_init();
1045 /* Enable EEH for all adapters */
1046 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1047 pdn = hose->pci_data;
1048 traverse_pci_dn(pdn, eeh_ops->probe, NULL);
1052 * Call platform post-initialization. Actually, It's good chance
1053 * to inform platform that EEH is ready to supply service if the
1054 * I/O cache stuff has been built up.
1056 if (eeh_ops->post_init) {
1057 ret = eeh_ops->post_init();
1063 pr_info("EEH: PCI Enhanced I/O Error Handling Enabled\n");
1065 pr_warn("EEH: No capable adapters found\n");
1070 core_initcall_sync(eeh_init);
1073 * eeh_add_device_early - Enable EEH for the indicated device node
1074 * @pdn: PCI device node for which to set up EEH
1076 * This routine must be used to perform EEH initialization for PCI
1077 * devices that were added after system boot (e.g. hotplug, dlpar).
1078 * This routine must be called before any i/o is performed to the
1079 * adapter (inluding any config-space i/o).
1080 * Whether this actually enables EEH or not for this device depends
1081 * on the CEC architecture, type of the device, on earlier boot
1082 * command-line arguments & etc.
1084 void eeh_add_device_early(struct pci_dn *pdn)
1086 struct pci_controller *phb;
1087 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1092 if (!eeh_has_flag(EEH_PROBE_MODE_DEVTREE))
1095 /* USB Bus children of PCI devices will not have BUID's */
1098 (eeh_has_flag(EEH_PROBE_MODE_DEVTREE) && 0 == phb->buid))
1101 eeh_ops->probe(pdn, NULL);
1105 * eeh_add_device_tree_early - Enable EEH for the indicated device
1106 * @pdn: PCI device node
1108 * This routine must be used to perform EEH initialization for the
1109 * indicated PCI device that was added after system boot (e.g.
1112 void eeh_add_device_tree_early(struct pci_dn *pdn)
1119 list_for_each_entry(n, &pdn->child_list, list)
1120 eeh_add_device_tree_early(n);
1121 eeh_add_device_early(pdn);
1123 EXPORT_SYMBOL_GPL(eeh_add_device_tree_early);
1126 * eeh_add_device_late - Perform EEH initialization for the indicated pci device
1127 * @dev: pci device for which to set up EEH
1129 * This routine must be used to complete EEH initialization for PCI
1130 * devices that were added after system boot (e.g. hotplug, dlpar).
1132 void eeh_add_device_late(struct pci_dev *dev)
1135 struct eeh_dev *edev;
1137 if (!dev || !eeh_enabled())
1140 pr_debug("EEH: Adding device %s\n", pci_name(dev));
1142 pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
1143 edev = pdn_to_eeh_dev(pdn);
1144 if (edev->pdev == dev) {
1145 pr_debug("EEH: Already referenced !\n");
1150 * The EEH cache might not be removed correctly because of
1151 * unbalanced kref to the device during unplug time, which
1152 * relies on pcibios_release_device(). So we have to remove
1153 * that here explicitly.
1156 eeh_rmv_from_parent_pe(edev);
1157 eeh_addr_cache_rmv_dev(edev->pdev);
1158 eeh_sysfs_remove_device(edev->pdev);
1159 edev->mode &= ~EEH_DEV_SYSFS;
1162 * We definitely should have the PCI device removed
1163 * though it wasn't correctly. So we needn't call
1164 * into error handler afterwards.
1166 edev->mode |= EEH_DEV_NO_HANDLER;
1169 dev->dev.archdata.edev = NULL;
1172 if (eeh_has_flag(EEH_PROBE_MODE_DEV))
1173 eeh_ops->probe(pdn, NULL);
1176 dev->dev.archdata.edev = edev;
1178 eeh_addr_cache_insert_dev(dev);
1182 * eeh_add_device_tree_late - Perform EEH initialization for the indicated PCI bus
1185 * This routine must be used to perform EEH initialization for PCI
1186 * devices which are attached to the indicated PCI bus. The PCI bus
1187 * is added after system boot through hotplug or dlpar.
1189 void eeh_add_device_tree_late(struct pci_bus *bus)
1191 struct pci_dev *dev;
1193 list_for_each_entry(dev, &bus->devices, bus_list) {
1194 eeh_add_device_late(dev);
1195 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1196 struct pci_bus *subbus = dev->subordinate;
1198 eeh_add_device_tree_late(subbus);
1202 EXPORT_SYMBOL_GPL(eeh_add_device_tree_late);
1205 * eeh_add_sysfs_files - Add EEH sysfs files for the indicated PCI bus
1208 * This routine must be used to add EEH sysfs files for PCI
1209 * devices which are attached to the indicated PCI bus. The PCI bus
1210 * is added after system boot through hotplug or dlpar.
1212 void eeh_add_sysfs_files(struct pci_bus *bus)
1214 struct pci_dev *dev;
1216 list_for_each_entry(dev, &bus->devices, bus_list) {
1217 eeh_sysfs_add_device(dev);
1218 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1219 struct pci_bus *subbus = dev->subordinate;
1221 eeh_add_sysfs_files(subbus);
1225 EXPORT_SYMBOL_GPL(eeh_add_sysfs_files);
1228 * eeh_remove_device - Undo EEH setup for the indicated pci device
1229 * @dev: pci device to be removed
1231 * This routine should be called when a device is removed from
1232 * a running system (e.g. by hotplug or dlpar). It unregisters
1233 * the PCI device from the EEH subsystem. I/O errors affecting
1234 * this device will no longer be detected after this call; thus,
1235 * i/o errors affecting this slot may leave this device unusable.
1237 void eeh_remove_device(struct pci_dev *dev)
1239 struct eeh_dev *edev;
1241 if (!dev || !eeh_enabled())
1243 edev = pci_dev_to_eeh_dev(dev);
1245 /* Unregister the device with the EEH/PCI address search system */
1246 pr_debug("EEH: Removing device %s\n", pci_name(dev));
1248 if (!edev || !edev->pdev || !edev->pe) {
1249 pr_debug("EEH: Not referenced !\n");
1254 * During the hotplug for EEH error recovery, we need the EEH
1255 * device attached to the parent PE in order for BAR restore
1256 * a bit later. So we keep it for BAR restore and remove it
1257 * from the parent PE during the BAR resotre.
1260 dev->dev.archdata.edev = NULL;
1261 if (!(edev->pe->state & EEH_PE_KEEP))
1262 eeh_rmv_from_parent_pe(edev);
1264 edev->mode |= EEH_DEV_DISCONNECTED;
1267 * We're removing from the PCI subsystem, that means
1268 * the PCI device driver can't support EEH or not
1269 * well. So we rely on hotplug completely to do recovery
1270 * for the specific PCI device.
1272 edev->mode |= EEH_DEV_NO_HANDLER;
1274 eeh_addr_cache_rmv_dev(dev);
1275 eeh_sysfs_remove_device(dev);
1276 edev->mode &= ~EEH_DEV_SYSFS;
1279 int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state)
1283 ret = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
1285 pr_warn("%s: Failure %d enabling IO on PHB#%x-PE#%x\n",
1286 __func__, ret, pe->phb->global_number, pe->addr);
1290 ret = eeh_pci_enable(pe, EEH_OPT_THAW_DMA);
1292 pr_warn("%s: Failure %d enabling DMA on PHB#%x-PE#%x\n",
1293 __func__, ret, pe->phb->global_number, pe->addr);
1297 /* Clear software isolated state */
1298 if (sw_state && (pe->state & EEH_PE_ISOLATED))
1299 eeh_pe_state_clear(pe, EEH_PE_ISOLATED);
1305 static struct pci_device_id eeh_reset_ids[] = {
1306 { PCI_DEVICE(0x19a2, 0x0710) }, /* Emulex, BE */
1307 { PCI_DEVICE(0x10df, 0xe220) }, /* Emulex, Lancer */
1308 { PCI_DEVICE(0x14e4, 0x1657) }, /* Broadcom BCM5719 */
1312 static int eeh_pe_change_owner(struct eeh_pe *pe)
1314 struct eeh_dev *edev, *tmp;
1315 struct pci_dev *pdev;
1316 struct pci_device_id *id;
1319 /* Check PE state */
1320 flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
1321 ret = eeh_ops->get_state(pe, NULL);
1322 if (ret < 0 || ret == EEH_STATE_NOT_SUPPORT)
1325 /* Unfrozen PE, nothing to do */
1326 if ((ret & flags) == flags)
1329 /* Frozen PE, check if it needs PE level reset */
1330 eeh_pe_for_each_dev(pe, edev, tmp) {
1331 pdev = eeh_dev_to_pci_dev(edev);
1335 for (id = &eeh_reset_ids[0]; id->vendor != 0; id++) {
1336 if (id->vendor != PCI_ANY_ID &&
1337 id->vendor != pdev->vendor)
1339 if (id->device != PCI_ANY_ID &&
1340 id->device != pdev->device)
1342 if (id->subvendor != PCI_ANY_ID &&
1343 id->subvendor != pdev->subsystem_vendor)
1345 if (id->subdevice != PCI_ANY_ID &&
1346 id->subdevice != pdev->subsystem_device)
1353 return eeh_unfreeze_pe(pe, true);
1356 return eeh_pe_reset_and_recover(pe);
1360 * eeh_dev_open - Increase count of pass through devices for PE
1363 * Increase count of passed through devices for the indicated
1364 * PE. In the result, the EEH errors detected on the PE won't be
1365 * reported. The PE owner will be responsible for detection
1368 int eeh_dev_open(struct pci_dev *pdev)
1370 struct eeh_dev *edev;
1373 mutex_lock(&eeh_dev_mutex);
1375 /* No PCI device ? */
1379 /* No EEH device or PE ? */
1380 edev = pci_dev_to_eeh_dev(pdev);
1381 if (!edev || !edev->pe)
1385 * The PE might have been put into frozen state, but we
1386 * didn't detect that yet. The passed through PCI devices
1387 * in frozen PE won't work properly. Clear the frozen state
1390 ret = eeh_pe_change_owner(edev->pe);
1394 /* Increase PE's pass through count */
1395 atomic_inc(&edev->pe->pass_dev_cnt);
1396 mutex_unlock(&eeh_dev_mutex);
1400 mutex_unlock(&eeh_dev_mutex);
1403 EXPORT_SYMBOL_GPL(eeh_dev_open);
1406 * eeh_dev_release - Decrease count of pass through devices for PE
1409 * Decrease count of pass through devices for the indicated PE. If
1410 * there is no passed through device in PE, the EEH errors detected
1411 * on the PE will be reported and handled as usual.
1413 void eeh_dev_release(struct pci_dev *pdev)
1415 struct eeh_dev *edev;
1417 mutex_lock(&eeh_dev_mutex);
1419 /* No PCI device ? */
1423 /* No EEH device ? */
1424 edev = pci_dev_to_eeh_dev(pdev);
1425 if (!edev || !edev->pe || !eeh_pe_passed(edev->pe))
1428 /* Decrease PE's pass through count */
1429 WARN_ON(atomic_dec_if_positive(&edev->pe->pass_dev_cnt) < 0);
1430 eeh_pe_change_owner(edev->pe);
1432 mutex_unlock(&eeh_dev_mutex);
1434 EXPORT_SYMBOL(eeh_dev_release);
1436 #ifdef CONFIG_IOMMU_API
1438 static int dev_has_iommu_table(struct device *dev, void *data)
1440 struct pci_dev *pdev = to_pci_dev(dev);
1441 struct pci_dev **ppdev = data;
1446 if (dev->iommu_group) {
1455 * eeh_iommu_group_to_pe - Convert IOMMU group to EEH PE
1456 * @group: IOMMU group
1458 * The routine is called to convert IOMMU group to EEH PE.
1460 struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group)
1462 struct pci_dev *pdev = NULL;
1463 struct eeh_dev *edev;
1466 /* No IOMMU group ? */
1470 ret = iommu_group_for_each_dev(group, &pdev, dev_has_iommu_table);
1474 /* No EEH device or PE ? */
1475 edev = pci_dev_to_eeh_dev(pdev);
1476 if (!edev || !edev->pe)
1481 EXPORT_SYMBOL_GPL(eeh_iommu_group_to_pe);
1483 #endif /* CONFIG_IOMMU_API */
1486 * eeh_pe_set_option - Set options for the indicated PE
1488 * @option: requested option
1490 * The routine is called to enable or disable EEH functionality
1491 * on the indicated PE, to enable IO or DMA for the frozen PE.
1493 int eeh_pe_set_option(struct eeh_pe *pe, int option)
1502 * EEH functionality could possibly be disabled, just
1503 * return error for the case. And the EEH functinality
1504 * isn't expected to be disabled on one specific PE.
1507 case EEH_OPT_ENABLE:
1508 if (eeh_enabled()) {
1509 ret = eeh_pe_change_owner(pe);
1514 case EEH_OPT_DISABLE:
1516 case EEH_OPT_THAW_MMIO:
1517 case EEH_OPT_THAW_DMA:
1518 if (!eeh_ops || !eeh_ops->set_option) {
1523 ret = eeh_pci_enable(pe, option);
1526 pr_debug("%s: Option %d out of range (%d, %d)\n",
1527 __func__, option, EEH_OPT_DISABLE, EEH_OPT_THAW_DMA);
1533 EXPORT_SYMBOL_GPL(eeh_pe_set_option);
1536 * eeh_pe_get_state - Retrieve PE's state
1539 * Retrieve the PE's state, which includes 3 aspects: enabled
1540 * DMA, enabled IO and asserted reset.
1542 int eeh_pe_get_state(struct eeh_pe *pe)
1544 int result, ret = 0;
1545 bool rst_active, dma_en, mmio_en;
1551 if (!eeh_ops || !eeh_ops->get_state)
1554 result = eeh_ops->get_state(pe, NULL);
1555 rst_active = !!(result & EEH_STATE_RESET_ACTIVE);
1556 dma_en = !!(result & EEH_STATE_DMA_ENABLED);
1557 mmio_en = !!(result & EEH_STATE_MMIO_ENABLED);
1560 ret = EEH_PE_STATE_RESET;
1561 else if (dma_en && mmio_en)
1562 ret = EEH_PE_STATE_NORMAL;
1563 else if (!dma_en && !mmio_en)
1564 ret = EEH_PE_STATE_STOPPED_IO_DMA;
1565 else if (!dma_en && mmio_en)
1566 ret = EEH_PE_STATE_STOPPED_DMA;
1568 ret = EEH_PE_STATE_UNAVAIL;
1572 EXPORT_SYMBOL_GPL(eeh_pe_get_state);
1574 static int eeh_pe_reenable_devices(struct eeh_pe *pe)
1576 struct eeh_dev *edev, *tmp;
1577 struct pci_dev *pdev;
1580 /* Restore config space */
1581 eeh_pe_restore_bars(pe);
1584 * Reenable PCI devices as the devices passed
1585 * through are always enabled before the reset.
1587 eeh_pe_for_each_dev(pe, edev, tmp) {
1588 pdev = eeh_dev_to_pci_dev(edev);
1592 ret = pci_reenable_device(pdev);
1594 pr_warn("%s: Failure %d reenabling %s\n",
1595 __func__, ret, pci_name(pdev));
1600 /* The PE is still in frozen state */
1601 return eeh_unfreeze_pe(pe, true);
1605 * eeh_pe_reset - Issue PE reset according to specified type
1607 * @option: reset type
1609 * The routine is called to reset the specified PE with the
1610 * indicated type, either fundamental reset or hot reset.
1611 * PE reset is the most important part for error recovery.
1613 int eeh_pe_reset(struct eeh_pe *pe, int option)
1621 if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset)
1625 case EEH_RESET_DEACTIVATE:
1626 ret = eeh_ops->reset(pe, option);
1627 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);
1631 ret = eeh_pe_reenable_devices(pe);
1634 case EEH_RESET_FUNDAMENTAL:
1636 * Proactively freeze the PE to drop all MMIO access
1637 * during reset, which should be banned as it's always
1638 * cause recursive EEH error.
1640 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
1642 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
1643 ret = eeh_ops->reset(pe, option);
1646 pr_debug("%s: Unsupported option %d\n",
1653 EXPORT_SYMBOL_GPL(eeh_pe_reset);
1656 * eeh_pe_configure - Configure PCI bridges after PE reset
1659 * The routine is called to restore the PCI config space for
1660 * those PCI devices, especially PCI bridges affected by PE
1661 * reset issued previously.
1663 int eeh_pe_configure(struct eeh_pe *pe)
1673 EXPORT_SYMBOL_GPL(eeh_pe_configure);
1676 * eeh_pe_inject_err - Injecting the specified PCI error to the indicated PE
1677 * @pe: the indicated PE
1679 * @function: error function
1681 * @mask: address mask
1683 * The routine is called to inject the specified PCI error, which
1684 * is determined by @type and @function, to the indicated PE for
1687 int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
1688 unsigned long addr, unsigned long mask)
1694 /* Unsupported operation ? */
1695 if (!eeh_ops || !eeh_ops->err_inject)
1698 /* Check on PCI error type */
1699 if (type != EEH_ERR_TYPE_32 && type != EEH_ERR_TYPE_64)
1702 /* Check on PCI error function */
1703 if (func < EEH_ERR_FUNC_MIN || func > EEH_ERR_FUNC_MAX)
1706 return eeh_ops->err_inject(pe, type, func, addr, mask);
1708 EXPORT_SYMBOL_GPL(eeh_pe_inject_err);
1710 static int proc_eeh_show(struct seq_file *m, void *v)
1712 if (!eeh_enabled()) {
1713 seq_printf(m, "EEH Subsystem is globally disabled\n");
1714 seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs);
1716 seq_printf(m, "EEH Subsystem is enabled\n");
1719 "no device node=%llu\n"
1720 "no config address=%llu\n"
1721 "check not wanted=%llu\n"
1722 "eeh_total_mmio_ffs=%llu\n"
1723 "eeh_false_positives=%llu\n"
1724 "eeh_slot_resets=%llu\n",
1725 eeh_stats.no_device,
1727 eeh_stats.no_cfg_addr,
1728 eeh_stats.ignored_check,
1729 eeh_stats.total_mmio_ffs,
1730 eeh_stats.false_positives,
1731 eeh_stats.slot_resets);
1737 static int proc_eeh_open(struct inode *inode, struct file *file)
1739 return single_open(file, proc_eeh_show, NULL);
1742 static const struct file_operations proc_eeh_operations = {
1743 .open = proc_eeh_open,
1745 .llseek = seq_lseek,
1746 .release = single_release,
1749 #ifdef CONFIG_DEBUG_FS
1750 static int eeh_enable_dbgfs_set(void *data, u64 val)
1753 eeh_clear_flag(EEH_FORCE_DISABLED);
1755 eeh_add_flag(EEH_FORCE_DISABLED);
1757 /* Notify the backend */
1758 if (eeh_ops->post_init)
1759 eeh_ops->post_init();
1764 static int eeh_enable_dbgfs_get(void *data, u64 *val)
1773 static int eeh_freeze_dbgfs_set(void *data, u64 val)
1775 eeh_max_freezes = val;
1779 static int eeh_freeze_dbgfs_get(void *data, u64 *val)
1781 *val = eeh_max_freezes;
1785 DEFINE_SIMPLE_ATTRIBUTE(eeh_enable_dbgfs_ops, eeh_enable_dbgfs_get,
1786 eeh_enable_dbgfs_set, "0x%llx\n");
1787 DEFINE_SIMPLE_ATTRIBUTE(eeh_freeze_dbgfs_ops, eeh_freeze_dbgfs_get,
1788 eeh_freeze_dbgfs_set, "0x%llx\n");
1791 static int __init eeh_init_proc(void)
1793 if (machine_is(pseries) || machine_is(powernv)) {
1794 proc_create("powerpc/eeh", 0, NULL, &proc_eeh_operations);
1795 #ifdef CONFIG_DEBUG_FS
1796 debugfs_create_file("eeh_enable", 0600,
1797 powerpc_debugfs_root, NULL,
1798 &eeh_enable_dbgfs_ops);
1799 debugfs_create_file("eeh_max_freezes", 0600,
1800 powerpc_debugfs_root, NULL,
1801 &eeh_freeze_dbgfs_ops);
1807 __initcall(eeh_init_proc);