arch/powerpc/kernel/dt_cpu_ftrs.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright 2017, Nicholas Piggin, IBM Corporation
   4  */
   5
   6 #define pr_fmt(fmt) "dt-cpu-ftrs: " fmt
   7
   8 #include <linux/export.h>
   9 #include <linux/init.h>
  10 #include <linux/jump_label.h>
  11 #include <linux/libfdt.h>
  12 #include <linux/memblock.h>
  13 #include <linux/of_fdt.h>
  14 #include <linux/printk.h>
  15 #include <linux/sched.h>
  16 #include <linux/string.h>
  17 #include <linux/threads.h>
  18
  19 #include <asm/cputable.h>
  20 #include <asm/dt_cpu_ftrs.h>
  21 #include <asm/mce.h>
  22 #include <asm/mmu.h>
  23 #include <asm/setup.h>
  24
  25
  26 /* Device-tree visible constants follow */
  27 #define ISA_V3_0B       3000
  28 #define ISA_V3_1        3100
  29
  30 #define USABLE_PR               (1U << 0)
  31 #define USABLE_OS               (1U << 1)
  32 #define USABLE_HV               (1U << 2)
  33
  34 #define HV_SUPPORT_HFSCR        (1U << 0)
  35 #define OS_SUPPORT_FSCR         (1U << 0)
  36
  37 /* For parsing, we define all bits set as "NONE" case */
  38 #define HV_SUPPORT_NONE         0xffffffffU
  39 #define OS_SUPPORT_NONE         0xffffffffU
  40
  41 struct dt_cpu_feature {
  42         const char *name;
  43         uint32_t isa;
  44         uint32_t usable_privilege;
  45         uint32_t hv_support;
  46         uint32_t os_support;
  47         uint32_t hfscr_bit_nr;
  48         uint32_t fscr_bit_nr;
  49         uint32_t hwcap_bit_nr;
  50         /* fdt parsing */
  51         unsigned long node;
  52         int enabled;
  53         int disabled;
  54 };
  55
  56 #define MMU_FTRS_HASH_BASE (MMU_FTRS_POWER8)
  57
  58 #define COMMON_USER_BASE        (PPC_FEATURE_32 | PPC_FEATURE_64 | \
  59                                  PPC_FEATURE_ARCH_2_06 |\
  60                                  PPC_FEATURE_ICACHE_SNOOP)
  61 #define COMMON_USER2_BASE       (PPC_FEATURE2_ARCH_2_07 | \
  62                                  PPC_FEATURE2_ISEL)
  63 /*
  64  * Set up the base CPU
  65  */
  66
  67 static int hv_mode;
  68
  69 static struct {
  70         u64     lpcr;
  71         u64     hfscr;
  72         u64     fscr;
  73         u64     pcr;
  74 } system_registers;
  75
  76 static void (*init_pmu_registers)(void);
  77
  78 static void __restore_cpu_cpufeatures(void)
  79 {
  80         mtspr(SPRN_LPCR, system_registers.lpcr);
  81         if (hv_mode) {
  82                 mtspr(SPRN_LPID, 0);
  83                 mtspr(SPRN_AMOR, ~0);
  84                 mtspr(SPRN_HFSCR, system_registers.hfscr);
  85                 mtspr(SPRN_PCR, system_registers.pcr);
  86         }
  87         mtspr(SPRN_FSCR, system_registers.fscr);
  88
  89         if (init_pmu_registers)
  90                 init_pmu_registers();
  91 }
  92
  93 static char dt_cpu_name[64];
  94
  95 static struct cpu_spec __initdata base_cpu_spec = {
  96         .cpu_name               = NULL,
  97         .cpu_features           = CPU_FTRS_DT_CPU_BASE,
  98         .cpu_user_features      = COMMON_USER_BASE,
  99         .cpu_user_features2     = COMMON_USER2_BASE,
 100         .mmu_features           = 0,
 101         .icache_bsize           = 32, /* minimum block size, fixed by */
 102         .dcache_bsize           = 32, /* cache info init.             */
 103         .num_pmcs               = 0,
 104         .pmc_type               = PPC_PMC_DEFAULT,
 105         .cpu_setup              = NULL,
 106         .cpu_restore            = __restore_cpu_cpufeatures,
 107         .machine_check_early    = NULL,
 108         .platform               = NULL,
 109 };
 110
 111 static void __init cpufeatures_setup_cpu(void)
 112 {
 113         set_cur_cpu_spec(&base_cpu_spec);
 114
 115         cur_cpu_spec->pvr_mask = -1;
 116         cur_cpu_spec->pvr_value = mfspr(SPRN_PVR);
 117
 118         /* Initialize the base environment -- clear FSCR/HFSCR.  */
 119         hv_mode = !!(mfmsr() & MSR_HV);
 120         if (hv_mode) {
 121                 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
 122                 mtspr(SPRN_HFSCR, 0);
 123         }
 124         mtspr(SPRN_FSCR, 0);
 125         mtspr(SPRN_PCR, PCR_MASK);
 126
 127         /*
 128          * LPCR does not get cleared, to match behaviour with secondaries
 129          * in __restore_cpu_cpufeatures. Once the idle code is fixed, this
 130          * could clear LPCR too.
 131          */
 132 }
 133
 134 static int __init feat_try_enable_unknown(struct dt_cpu_feature *f)
 135 {
 136         if (f->hv_support == HV_SUPPORT_NONE) {
 137         } else if (f->hv_support & HV_SUPPORT_HFSCR) {
 138                 u64 hfscr = mfspr(SPRN_HFSCR);
 139                 hfscr |= 1UL << f->hfscr_bit_nr;
 140                 mtspr(SPRN_HFSCR, hfscr);
 141         } else {
 142                 /* Does not have a known recipe */
 143                 return 0;
 144         }
 145
 146         if (f->os_support == OS_SUPPORT_NONE) {
 147         } else if (f->os_support & OS_SUPPORT_FSCR) {
 148                 u64 fscr = mfspr(SPRN_FSCR);
 149                 fscr |= 1UL << f->fscr_bit_nr;
 150                 mtspr(SPRN_FSCR, fscr);
 151         } else {
 152                 /* Does not have a known recipe */
 153                 return 0;
 154         }
 155
 156         if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) {
 157                 uint32_t word = f->hwcap_bit_nr / 32;
 158                 uint32_t bit = f->hwcap_bit_nr % 32;
 159
 160                 if (word == 0)
 161                         cur_cpu_spec->cpu_user_features |= 1U << bit;
 162                 else if (word == 1)
 163                         cur_cpu_spec->cpu_user_features2 |= 1U << bit;
 164                 else
 165                         pr_err("%s could not advertise to user (no hwcap bits)\n", f->name);
 166         }
 167
 168         return 1;
 169 }
 170
 171 static int __init feat_enable(struct dt_cpu_feature *f)
 172 {
 173         if (f->hv_support != HV_SUPPORT_NONE) {
 174                 if (f->hfscr_bit_nr != -1) {
 175                         u64 hfscr = mfspr(SPRN_HFSCR);
 176                         hfscr |= 1UL << f->hfscr_bit_nr;
 177                         mtspr(SPRN_HFSCR, hfscr);
 178                 }
 179         }
 180
 181         if (f->os_support != OS_SUPPORT_NONE) {
 182                 if (f->fscr_bit_nr != -1) {
 183                         u64 fscr = mfspr(SPRN_FSCR);
 184                         fscr |= 1UL << f->fscr_bit_nr;
 185                         mtspr(SPRN_FSCR, fscr);
 186                 }
 187         }
 188
 189         if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) {
 190                 uint32_t word = f->hwcap_bit_nr / 32;
 191                 uint32_t bit = f->hwcap_bit_nr % 32;
 192
 193                 if (word == 0)
 194                         cur_cpu_spec->cpu_user_features |= 1U << bit;
 195                 else if (word == 1)
 196                         cur_cpu_spec->cpu_user_features2 |= 1U << bit;
 197                 else
 198                         pr_err("CPU feature: %s could not advertise to user (no hwcap bits)\n", f->name);
 199         }
 200
 201         return 1;
 202 }
 203
 204 static int __init feat_disable(struct dt_cpu_feature *f)
 205 {
 206         return 0;
 207 }
 208
 209 static int __init feat_enable_hv(struct dt_cpu_feature *f)
 210 {
 211         u64 lpcr;
 212
 213         if (!hv_mode) {
 214                 pr_err("CPU feature hypervisor present in device tree but HV mode not enabled in the CPU. Ignoring.\n");
 215                 return 0;
 216         }
 217
 218         mtspr(SPRN_LPID, 0);
 219         mtspr(SPRN_AMOR, ~0);
 220
 221         lpcr = mfspr(SPRN_LPCR);
 222         lpcr &=  ~LPCR_LPES0; /* HV external interrupts */
 223         mtspr(SPRN_LPCR, lpcr);
 224
 225         cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
 226
 227         return 1;
 228 }
 229
 230 static int __init feat_enable_le(struct dt_cpu_feature *f)
 231 {
 232         cur_cpu_spec->cpu_user_features |= PPC_FEATURE_TRUE_LE;
 233         return 1;
 234 }
 235
 236 static int __init feat_enable_smt(struct dt_cpu_feature *f)
 237 {
 238         cur_cpu_spec->cpu_features |= CPU_FTR_SMT;
 239         cur_cpu_spec->cpu_user_features |= PPC_FEATURE_SMT;
 240         return 1;
 241 }
 242
 243 static int __init feat_enable_idle_nap(struct dt_cpu_feature *f)
 244 {
 245         u64 lpcr;
 246
 247         /* Set PECE wakeup modes for ISA 207 */
 248         lpcr = mfspr(SPRN_LPCR);
 249         lpcr |=  LPCR_PECE0;
 250         lpcr |=  LPCR_PECE1;
 251         lpcr |=  LPCR_PECE2;
 252         mtspr(SPRN_LPCR, lpcr);
 253
 254         return 1;
 255 }
 256
 257 static int __init feat_enable_idle_stop(struct dt_cpu_feature *f)
 258 {
 259         u64 lpcr;
 260
 261         /* Set PECE wakeup modes for ISAv3.0B */
 262         lpcr = mfspr(SPRN_LPCR);
 263         lpcr |=  LPCR_PECE0;
 264         lpcr |=  LPCR_PECE1;
 265         lpcr |=  LPCR_PECE2;
 266         mtspr(SPRN_LPCR, lpcr);
 267
 268         return 1;
 269 }
 270
 271 static int __init feat_enable_mmu_hash(struct dt_cpu_feature *f)
 272 {
 273         u64 lpcr;
 274
 275         if (!IS_ENABLED(CONFIG_PPC_64S_HASH_MMU))
 276                 return 0;
 277
 278         lpcr = mfspr(SPRN_LPCR);
 279         lpcr &= ~LPCR_ISL;
 280
 281         /* VRMASD */
 282         lpcr |= LPCR_VPM0;
 283         lpcr &= ~LPCR_VPM1;
 284         lpcr |= 0x10UL << LPCR_VRMASD_SH; /* L=1 LP=00 */
 285         mtspr(SPRN_LPCR, lpcr);
 286
 287         cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
 288         cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
 289
 290         return 1;
 291 }
 292
 293 static int __init feat_enable_mmu_hash_v3(struct dt_cpu_feature *f)
 294 {
 295         u64 lpcr;
 296
 297         if (!IS_ENABLED(CONFIG_PPC_64S_HASH_MMU))
 298                 return 0;
 299
 300         lpcr = mfspr(SPRN_LPCR);
 301         lpcr &= ~(LPCR_ISL | LPCR_UPRT | LPCR_HR);
 302         mtspr(SPRN_LPCR, lpcr);
 303
 304         cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
 305         cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
 306
 307         return 1;
 308 }
 309
 310
 311 static int __init feat_enable_mmu_radix(struct dt_cpu_feature *f)
 312 {
 313         if (!IS_ENABLED(CONFIG_PPC_RADIX_MMU))
 314                 return 0;
 315
 316         cur_cpu_spec->mmu_features |= MMU_FTR_KERNEL_RO;
 317         cur_cpu_spec->mmu_features |= MMU_FTR_TYPE_RADIX;
 318         cur_cpu_spec->mmu_features |= MMU_FTR_GTSE;
 319         cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
 320
 321         return 1;
 322 }
 323
 324 static int __init feat_enable_dscr(struct dt_cpu_feature *f)
 325 {
 326         u64 lpcr;
 327
 328         /*
 329          * Linux relies on FSCR[DSCR] being clear, so that we can take the
 330          * facility unavailable interrupt and track the task's usage of DSCR.
 331          * See facility_unavailable_exception().
 332          * Clear the bit here so that feat_enable() doesn't set it.
 333          */
 334         f->fscr_bit_nr = -1;
 335
 336         feat_enable(f);
 337
 338         lpcr = mfspr(SPRN_LPCR);
 339         lpcr &= ~LPCR_DPFD;
 340         lpcr |=  (4UL << LPCR_DPFD_SH);
 341         mtspr(SPRN_LPCR, lpcr);
 342
 343         return 1;
 344 }
 345
 346 static void __init hfscr_pmu_enable(void)
 347 {
 348         u64 hfscr = mfspr(SPRN_HFSCR);
 349         hfscr |= PPC_BIT(60);
 350         mtspr(SPRN_HFSCR, hfscr);
 351 }
 352
 353 static void init_pmu_power8(void)
 354 {
 355         if (hv_mode) {
 356                 mtspr(SPRN_MMCRC, 0);
 357                 mtspr(SPRN_MMCRH, 0);
 358         }
 359
 360         mtspr(SPRN_MMCRA, 0);
 361         mtspr(SPRN_MMCR0, MMCR0_FC);
 362         mtspr(SPRN_MMCR1, 0);
 363         mtspr(SPRN_MMCR2, 0);
 364         mtspr(SPRN_MMCRS, 0);
 365 }
 366
 367 static int __init feat_enable_mce_power8(struct dt_cpu_feature *f)
 368 {
 369         cur_cpu_spec->platform = "power8";
 370         cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p8;
 371
 372         return 1;
 373 }
 374
 375 static int __init feat_enable_pmu_power8(struct dt_cpu_feature *f)
 376 {
 377         hfscr_pmu_enable();
 378
 379         init_pmu_power8();
 380         init_pmu_registers = init_pmu_power8;
 381
 382         cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;
 383         cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;
 384         if (pvr_version_is(PVR_POWER8E))
 385                 cur_cpu_spec->cpu_features |= CPU_FTR_PMAO_BUG;
 386
 387         cur_cpu_spec->num_pmcs          = 6;
 388         cur_cpu_spec->pmc_type          = PPC_PMC_IBM;
 389
 390         return 1;
 391 }
 392
 393 static void init_pmu_power9(void)
 394 {
 395         if (hv_mode)
 396                 mtspr(SPRN_MMCRC, 0);
 397
 398         mtspr(SPRN_MMCRA, 0);
 399         mtspr(SPRN_MMCR0, MMCR0_FC);
 400         mtspr(SPRN_MMCR1, 0);
 401         mtspr(SPRN_MMCR2, 0);
 402 }
 403
 404 static int __init feat_enable_mce_power9(struct dt_cpu_feature *f)
 405 {
 406         cur_cpu_spec->platform = "power9";
 407         cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p9;
 408
 409         return 1;
 410 }
 411
 412 static int __init feat_enable_pmu_power9(struct dt_cpu_feature *f)
 413 {
 414         hfscr_pmu_enable();
 415
 416         init_pmu_power9();
 417         init_pmu_registers = init_pmu_power9;
 418
 419         cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;
 420         cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;
 421
 422         cur_cpu_spec->num_pmcs          = 6;
 423         cur_cpu_spec->pmc_type          = PPC_PMC_IBM;
 424
 425         return 1;
 426 }
 427
 428 static void init_pmu_power10(void)
 429 {
 430         init_pmu_power9();
 431
 432         mtspr(SPRN_MMCR3, 0);
 433         mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE);
 434         mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMCCEXT);
 435 }
 436
 437 static int __init feat_enable_pmu_power10(struct dt_cpu_feature *f)
 438 {
 439         hfscr_pmu_enable();
 440
 441         init_pmu_power10();
 442         init_pmu_registers = init_pmu_power10;
 443
 444         cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;
 445         cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;
 446
 447         cur_cpu_spec->num_pmcs          = 6;
 448         cur_cpu_spec->pmc_type          = PPC_PMC_IBM;
 449
 450         return 1;
 451 }
 452
 453 static int __init feat_enable_mce_power10(struct dt_cpu_feature *f)
 454 {
 455         cur_cpu_spec->platform = "power10";
 456         cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p10;
 457
 458         return 1;
 459 }
 460
 461 static int __init feat_enable_tm(struct dt_cpu_feature *f)
 462 {
 463 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 464         feat_enable(f);
 465         cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NOSC;
 466         return 1;
 467 #endif
 468         return 0;
 469 }
 470
 471 static int __init feat_enable_fp(struct dt_cpu_feature *f)
 472 {
 473         feat_enable(f);
 474         cur_cpu_spec->cpu_features &= ~CPU_FTR_FPU_UNAVAILABLE;
 475
 476         return 1;
 477 }
 478
 479 static int __init feat_enable_vector(struct dt_cpu_feature *f)
 480 {
 481 #ifdef CONFIG_ALTIVEC
 482         feat_enable(f);
 483         cur_cpu_spec->cpu_features |= CPU_FTR_ALTIVEC;
 484         cur_cpu_spec->cpu_features |= CPU_FTR_VMX_COPY;
 485         cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_ALTIVEC;
 486
 487         return 1;
 488 #endif
 489         return 0;
 490 }
 491
 492 static int __init feat_enable_vsx(struct dt_cpu_feature *f)
 493 {
 494 #ifdef CONFIG_VSX
 495         feat_enable(f);
 496         cur_cpu_spec->cpu_features |= CPU_FTR_VSX;
 497         cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_VSX;
 498
 499         return 1;
 500 #endif
 501         return 0;
 502 }
 503
 504 static int __init feat_enable_purr(struct dt_cpu_feature *f)
 505 {
 506         cur_cpu_spec->cpu_features |= CPU_FTR_PURR | CPU_FTR_SPURR;
 507
 508         return 1;
 509 }
 510
 511 static int __init feat_enable_ebb(struct dt_cpu_feature *f)
 512 {
 513         /*
 514          * PPC_FEATURE2_EBB is enabled in PMU init code because it has
 515          * historically been related to the PMU facility. This may have
 516          * to be decoupled if EBB becomes more generic. For now, follow
 517          * existing convention.
 518          */
 519         f->hwcap_bit_nr = -1;
 520         feat_enable(f);
 521
 522         return 1;
 523 }
 524
 525 static int __init feat_enable_dbell(struct dt_cpu_feature *f)
 526 {
 527         u64 lpcr;
 528
 529         /* P9 has an HFSCR for privileged state */
 530         feat_enable(f);
 531
 532         cur_cpu_spec->cpu_features |= CPU_FTR_DBELL;
 533
 534         lpcr = mfspr(SPRN_LPCR);
 535         lpcr |=  LPCR_PECEDH; /* hyp doorbell wakeup */
 536         mtspr(SPRN_LPCR, lpcr);
 537
 538         return 1;
 539 }
 540
 541 static int __init feat_enable_hvi(struct dt_cpu_feature *f)
 542 {
 543         u64 lpcr;
 544
 545         /*
 546          * POWER9 XIVE interrupts including in OPAL XICS compatibility
 547          * are always delivered as hypervisor virtualization interrupts (HVI)
 548          * rather than EE.
 549          *
 550          * However LPES0 is not set here, in the chance that an EE does get
 551          * delivered to the host somehow, the EE handler would not expect it
 552          * to be delivered in LPES0 mode (e.g., using SRR[01]). This could
 553          * happen if there is a bug in interrupt controller code, or IC is
 554          * misconfigured in systemsim.
 555          */
 556
 557         lpcr = mfspr(SPRN_LPCR);
 558         lpcr |= LPCR_HVICE;     /* enable hvi interrupts */
 559         lpcr |= LPCR_HEIC;      /* disable ee interrupts when MSR_HV */
 560         lpcr |= LPCR_PECE_HVEE; /* hvi can wake from stop */
 561         mtspr(SPRN_LPCR, lpcr);
 562
 563         return 1;
 564 }
 565
 566 static int __init feat_enable_large_ci(struct dt_cpu_feature *f)
 567 {
 568         cur_cpu_spec->mmu_features |= MMU_FTR_CI_LARGE_PAGE;
 569
 570         return 1;
 571 }
 572
 573 static int __init feat_enable_mma(struct dt_cpu_feature *f)
 574 {
 575         u64 pcr;
 576
 577         feat_enable(f);
 578         pcr = mfspr(SPRN_PCR);
 579         pcr &= ~PCR_MMA_DIS;
 580         mtspr(SPRN_PCR, pcr);
 581
 582         return 1;
 583 }
 584
 585 struct dt_cpu_feature_match {
 586         const char *name;
 587         int (*enable)(struct dt_cpu_feature *f);
 588         u64 cpu_ftr_bit_mask;
 589 };
 590
 591 static struct dt_cpu_feature_match __initdata
 592                 dt_cpu_feature_match_table[] = {
 593         {"hypervisor", feat_enable_hv, 0},
 594         {"big-endian", feat_enable, 0},
 595         {"little-endian", feat_enable_le, CPU_FTR_REAL_LE},
 596         {"smt", feat_enable_smt, 0},
 597         {"interrupt-facilities", feat_enable, 0},
 598         {"system-call-vectored", feat_enable, 0},
 599         {"timer-facilities", feat_enable, 0},
 600         {"timer-facilities-v3", feat_enable, 0},
 601         {"debug-facilities", feat_enable, 0},
 602         {"come-from-address-register", feat_enable, CPU_FTR_CFAR},
 603         {"branch-tracing", feat_enable, 0},
 604         {"floating-point", feat_enable_fp, 0},
 605         {"vector", feat_enable_vector, 0},
 606         {"vector-scalar", feat_enable_vsx, 0},
 607         {"vector-scalar-v3", feat_enable, 0},
 608         {"decimal-floating-point", feat_enable, 0},
 609         {"decimal-integer", feat_enable, 0},
 610         {"quadword-load-store", feat_enable, 0},
 611         {"vector-crypto", feat_enable, 0},
 612         {"mmu-hash", feat_enable_mmu_hash, 0},
 613         {"mmu-radix", feat_enable_mmu_radix, 0},
 614         {"mmu-hash-v3", feat_enable_mmu_hash_v3, 0},
 615         {"virtual-page-class-key-protection", feat_enable, 0},
 616         {"transactional-memory", feat_enable_tm, CPU_FTR_TM},
 617         {"transactional-memory-v3", feat_enable_tm, 0},
 618         {"tm-suspend-hypervisor-assist", feat_enable, CPU_FTR_P9_TM_HV_ASSIST},
 619         {"tm-suspend-xer-so-bug", feat_enable, CPU_FTR_P9_TM_XER_SO_BUG},
 620         {"idle-nap", feat_enable_idle_nap, 0},
 621         /* alignment-interrupt-dsisr ignored */
 622         {"idle-stop", feat_enable_idle_stop, 0},
 623         {"machine-check-power8", feat_enable_mce_power8, 0},
 624         {"performance-monitor-power8", feat_enable_pmu_power8, 0},
 625         {"data-stream-control-register", feat_enable_dscr, CPU_FTR_DSCR},
 626         {"event-based-branch", feat_enable_ebb, 0},
 627         {"target-address-register", feat_enable, 0},
 628         {"branch-history-rolling-buffer", feat_enable, 0},
 629         {"control-register", feat_enable, CPU_FTR_CTRL},
 630         {"processor-control-facility", feat_enable_dbell, CPU_FTR_DBELL},
 631         {"processor-control-facility-v3", feat_enable_dbell, CPU_FTR_DBELL},
 632         {"processor-utilization-of-resources-register", feat_enable_purr, 0},
 633         {"no-execute", feat_enable, 0},
 634         {"strong-access-ordering", feat_enable, CPU_FTR_SAO},
 635         {"cache-inhibited-large-page", feat_enable_large_ci, 0},
 636         {"coprocessor-icswx", feat_enable, 0},
 637         {"hypervisor-virtualization-interrupt", feat_enable_hvi, 0},
 638         {"program-priority-register", feat_enable, CPU_FTR_HAS_PPR},
 639         {"wait", feat_enable, 0},
 640         {"atomic-memory-operations", feat_enable, 0},
 641         {"branch-v3", feat_enable, 0},
 642         {"copy-paste", feat_enable, 0},
 643         {"decimal-floating-point-v3", feat_enable, 0},
 644         {"decimal-integer-v3", feat_enable, 0},
 645         {"fixed-point-v3", feat_enable, 0},
 646         {"floating-point-v3", feat_enable, 0},
 647         {"group-start-register", feat_enable, 0},
 648         {"pc-relative-addressing", feat_enable, 0},
 649         {"machine-check-power9", feat_enable_mce_power9, 0},
 650         {"machine-check-power10", feat_enable_mce_power10, 0},
 651         {"performance-monitor-power9", feat_enable_pmu_power9, 0},
 652         {"performance-monitor-power10", feat_enable_pmu_power10, 0},
 653         {"event-based-branch-v3", feat_enable, 0},
 654         {"random-number-generator", feat_enable, 0},
 655         {"system-call-vectored", feat_disable, 0},
 656         {"trace-interrupt-v3", feat_enable, 0},
 657         {"vector-v3", feat_enable, 0},
 658         {"vector-binary128", feat_enable, 0},
 659         {"vector-binary16", feat_enable, 0},
 660         {"wait-v3", feat_enable, 0},
 661         {"prefix-instructions", feat_enable, 0},
 662         {"matrix-multiply-assist", feat_enable_mma, 0},
 663         {"debug-facilities-v31", feat_enable, CPU_FTR_DAWR1},
 664 };
 665
 666 static bool __initdata using_dt_cpu_ftrs;
 667 static bool __initdata enable_unknown = true;
 668
 669 static int __init dt_cpu_ftrs_parse(char *str)
 670 {
 671         if (!str)
 672                 return 0;
 673
 674         if (!strcmp(str, "off"))
 675                 using_dt_cpu_ftrs = false;
 676         else if (!strcmp(str, "known"))
 677                 enable_unknown = false;
 678         else
 679                 return 1;
 680
 681         return 0;
 682 }
 683 early_param("dt_cpu_ftrs", dt_cpu_ftrs_parse);
 684
 685 static void __init cpufeatures_setup_start(u32 isa)
 686 {
 687         pr_info("setup for ISA %d\n", isa);
 688
 689         if (isa >= ISA_V3_0B) {
 690                 cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_300;
 691                 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_00;
 692         }
 693
 694         if (isa >= ISA_V3_1) {
 695                 cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_31;
 696                 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_1;
 697         }
 698 }
 699
 700 static bool __init cpufeatures_process_feature(struct dt_cpu_feature *f)
 701 {
 702         const struct dt_cpu_feature_match *m;
 703         bool known = false;
 704         int i;
 705
 706         for (i = 0; i < ARRAY_SIZE(dt_cpu_feature_match_table); i++) {
 707                 m = &dt_cpu_feature_match_table[i];
 708                 if (!strcmp(f->name, m->name)) {
 709                         known = true;
 710                         if (m->enable(f)) {
 711                                 cur_cpu_spec->cpu_features |= m->cpu_ftr_bit_mask;
 712                                 break;
 713                         }
 714
 715                         pr_info("not enabling: %s (disabled or unsupported by kernel)\n",
 716                                 f->name);
 717                         return false;
 718                 }
 719         }
 720
 721         if (!known && (!enable_unknown || !feat_try_enable_unknown(f))) {
 722                 pr_info("not enabling: %s (unknown and unsupported by kernel)\n",
 723                         f->name);
 724                 return false;
 725         }
 726
 727         if (known)
 728                 pr_debug("enabling: %s\n", f->name);
 729         else
 730                 pr_debug("enabling: %s (unknown)\n", f->name);
 731
 732         return true;
 733 }
 734
 735 /*
 736  * Handle POWER9 broadcast tlbie invalidation issue using
 737  * cpu feature flag.
 738  */
 739 static __init void update_tlbie_feature_flag(unsigned long pvr)
 740 {
 741         if (PVR_VER(pvr) == PVR_POWER9) {
 742                 /*
 743                  * Set the tlbie feature flag for anything below
 744                  * Nimbus DD 2.3 and Cumulus DD 1.3
 745                  */
 746                 if ((pvr & 0xe000) == 0) {
 747                         /* Nimbus */
 748                         if ((pvr & 0xfff) < 0x203)
 749                                 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG;
 750                 } else if ((pvr & 0xc000) == 0) {
 751                         /* Cumulus */
 752                         if ((pvr & 0xfff) < 0x103)
 753                                 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG;
 754                 } else {
 755                         WARN_ONCE(1, "Unknown PVR");
 756                         cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG;
 757                 }
 758
 759                 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_ERAT_BUG;
 760         }
 761 }
 762
 763 static __init void cpufeatures_cpu_quirks(void)
 764 {
 765         unsigned long version = mfspr(SPRN_PVR);
 766
 767         /*
 768          * Not all quirks can be derived from the cpufeatures device tree.
 769          */
 770         if ((version & 0xffffefff) == 0x004e0200) {
 771                 /* DD2.0 has no feature flag */
 772                 cur_cpu_spec->cpu_features |= CPU_FTR_P9_RADIX_PREFETCH_BUG;
 773                 cur_cpu_spec->cpu_features &= ~(CPU_FTR_DAWR);
 774         } else if ((version & 0xffffefff) == 0x004e0201) {
 775                 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
 776                 cur_cpu_spec->cpu_features |= CPU_FTR_P9_RADIX_PREFETCH_BUG;
 777                 cur_cpu_spec->cpu_features &= ~(CPU_FTR_DAWR);
 778         } else if ((version & 0xffffefff) == 0x004e0202) {
 779                 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_HV_ASSIST;
 780                 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_XER_SO_BUG;
 781                 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
 782                 cur_cpu_spec->cpu_features &= ~(CPU_FTR_DAWR);
 783         } else if ((version & 0xffffefff) == 0x004e0203) {
 784                 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_HV_ASSIST;
 785                 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_XER_SO_BUG;
 786                 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
 787         } else if ((version & 0xffff0000) == 0x004e0000) {
 788                 /* DD2.1 and up have DD2_1 */
 789                 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
 790         }
 791
 792         if ((version & 0xffff0000) == 0x004e0000) {
 793                 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TIDR;
 794         }
 795
 796         update_tlbie_feature_flag(version);
 797 }
 798
 799 static void __init cpufeatures_setup_finished(void)
 800 {
 801         cpufeatures_cpu_quirks();
 802
 803         if (hv_mode && !(cur_cpu_spec->cpu_features & CPU_FTR_HVMODE)) {
 804                 pr_err("hypervisor not present in device tree but HV mode is enabled in the CPU. Enabling.\n");
 805                 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
 806         }
 807
 808         /* Make sure powerpc_base_platform is non-NULL */
 809         powerpc_base_platform = cur_cpu_spec->platform;
 810
 811         system_registers.lpcr = mfspr(SPRN_LPCR);
 812         system_registers.hfscr = mfspr(SPRN_HFSCR);
 813         system_registers.fscr = mfspr(SPRN_FSCR);
 814         system_registers.pcr = mfspr(SPRN_PCR);
 815
 816         pr_info("final cpu/mmu features = 0x%016lx 0x%08x\n",
 817                 cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features);
 818 }
 819
 820 static int __init disabled_on_cmdline(void)
 821 {
 822         unsigned long root, chosen;
 823         const char *p;
 824
 825         root = of_get_flat_dt_root();
 826         chosen = of_get_flat_dt_subnode_by_name(root, "chosen");
 827         if (chosen == -FDT_ERR_NOTFOUND)
 828                 return false;
 829
 830         p = of_get_flat_dt_prop(chosen, "bootargs", NULL);
 831         if (!p)
 832                 return false;
 833
 834         if (strstr(p, "dt_cpu_ftrs=off"))
 835                 return true;
 836
 837         return false;
 838 }
 839
 840 static int __init fdt_find_cpu_features(unsigned long node, const char *uname,
 841                                         int depth, void *data)
 842 {
 843         if (of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features")
 844             && of_get_flat_dt_prop(node, "isa", NULL))
 845                 return 1;
 846
 847         return 0;
 848 }
 849
 850 bool __init dt_cpu_ftrs_in_use(void)
 851 {
 852         return using_dt_cpu_ftrs;
 853 }
 854
 855 bool __init dt_cpu_ftrs_init(void *fdt)
 856 {
 857         using_dt_cpu_ftrs = false;
 858
 859         /* Setup and verify the FDT, if it fails we just bail */
 860         if (!early_init_dt_verify(fdt))
 861                 return false;
 862
 863         if (!of_scan_flat_dt(fdt_find_cpu_features, NULL))
 864                 return false;
 865
 866         if (disabled_on_cmdline())
 867                 return false;
 868
 869         cpufeatures_setup_cpu();
 870
 871         using_dt_cpu_ftrs = true;
 872         return true;
 873 }
 874
 875 static int nr_dt_cpu_features;
 876 static struct dt_cpu_feature *dt_cpu_features;
 877
 878 static int __init process_cpufeatures_node(unsigned long node,
 879                                           const char *uname, int i)
 880 {
 881         const __be32 *prop;
 882         struct dt_cpu_feature *f;
 883         int len;
 884
 885         f = &dt_cpu_features[i];
 886
 887         f->node = node;
 888
 889         f->name = uname;
 890
 891         prop = of_get_flat_dt_prop(node, "isa", &len);
 892         if (!prop) {
 893                 pr_warn("%s: missing isa property\n", uname);
 894                 return 0;
 895         }
 896         f->isa = be32_to_cpup(prop);
 897
 898         prop = of_get_flat_dt_prop(node, "usable-privilege", &len);
 899         if (!prop) {
 900                 pr_warn("%s: missing usable-privilege property", uname);
 901                 return 0;
 902         }
 903         f->usable_privilege = be32_to_cpup(prop);
 904
 905         prop = of_get_flat_dt_prop(node, "hv-support", &len);
 906         if (prop)
 907                 f->hv_support = be32_to_cpup(prop);
 908         else
 909                 f->hv_support = HV_SUPPORT_NONE;
 910
 911         prop = of_get_flat_dt_prop(node, "os-support", &len);
 912         if (prop)
 913                 f->os_support = be32_to_cpup(prop);
 914         else
 915                 f->os_support = OS_SUPPORT_NONE;
 916
 917         prop = of_get_flat_dt_prop(node, "hfscr-bit-nr", &len);
 918         if (prop)
 919                 f->hfscr_bit_nr = be32_to_cpup(prop);
 920         else
 921                 f->hfscr_bit_nr = -1;
 922         prop = of_get_flat_dt_prop(node, "fscr-bit-nr", &len);
 923         if (prop)
 924                 f->fscr_bit_nr = be32_to_cpup(prop);
 925         else
 926                 f->fscr_bit_nr = -1;
 927         prop = of_get_flat_dt_prop(node, "hwcap-bit-nr", &len);
 928         if (prop)
 929                 f->hwcap_bit_nr = be32_to_cpup(prop);
 930         else
 931                 f->hwcap_bit_nr = -1;
 932
 933         if (f->usable_privilege & USABLE_HV) {
 934                 if (!(mfmsr() & MSR_HV)) {
 935                         pr_warn("%s: HV feature passed to guest\n", uname);
 936                         return 0;
 937                 }
 938
 939                 if (f->hv_support == HV_SUPPORT_NONE && f->hfscr_bit_nr != -1) {
 940                         pr_warn("%s: unwanted hfscr_bit_nr\n", uname);
 941                         return 0;
 942                 }
 943
 944                 if (f->hv_support == HV_SUPPORT_HFSCR) {
 945                         if (f->hfscr_bit_nr == -1) {
 946                                 pr_warn("%s: missing hfscr_bit_nr\n", uname);
 947                                 return 0;
 948                         }
 949                 }
 950         } else {
 951                 if (f->hv_support != HV_SUPPORT_NONE || f->hfscr_bit_nr != -1) {
 952                         pr_warn("%s: unwanted hv_support/hfscr_bit_nr\n", uname);
 953                         return 0;
 954                 }
 955         }
 956
 957         if (f->usable_privilege & USABLE_OS) {
 958                 if (f->os_support == OS_SUPPORT_NONE && f->fscr_bit_nr != -1) {
 959                         pr_warn("%s: unwanted fscr_bit_nr\n", uname);
 960                         return 0;
 961                 }
 962
 963                 if (f->os_support == OS_SUPPORT_FSCR) {
 964                         if (f->fscr_bit_nr == -1) {
 965                                 pr_warn("%s: missing fscr_bit_nr\n", uname);
 966                                 return 0;
 967                         }
 968                 }
 969         } else {
 970                 if (f->os_support != OS_SUPPORT_NONE || f->fscr_bit_nr != -1) {
 971                         pr_warn("%s: unwanted os_support/fscr_bit_nr\n", uname);
 972                         return 0;
 973                 }
 974         }
 975
 976         if (!(f->usable_privilege & USABLE_PR)) {
 977                 if (f->hwcap_bit_nr != -1) {
 978                         pr_warn("%s: unwanted hwcap_bit_nr\n", uname);
 979                         return 0;
 980                 }
 981         }
 982
 983         /* Do all the independent features in the first pass */
 984         if (!of_get_flat_dt_prop(node, "dependencies", &len)) {
 985                 if (cpufeatures_process_feature(f))
 986                         f->enabled = 1;
 987                 else
 988                         f->disabled = 1;
 989         }
 990
 991         return 0;
 992 }
 993
 994 static void __init cpufeatures_deps_enable(struct dt_cpu_feature *f)
 995 {
 996         const __be32 *prop;
 997         int len;
 998         int nr_deps;
 999         int i;
1000
1001         if (f->enabled || f->disabled)
1002                 return;
1003
1004         prop = of_get_flat_dt_prop(f->node, "dependencies", &len);
1005         if (!prop) {
1006                 pr_warn("%s: missing dependencies property", f->name);
1007                 return;
1008         }
1009
1010         nr_deps = len / sizeof(int);
1011
1012         for (i = 0; i < nr_deps; i++) {
1013                 unsigned long phandle = be32_to_cpu(prop[i]);
1014                 int j;
1015
1016                 for (j = 0; j < nr_dt_cpu_features; j++) {
1017                         struct dt_cpu_feature *d = &dt_cpu_features[j];
1018
1019                         if (of_get_flat_dt_phandle(d->node) == phandle) {
1020                                 cpufeatures_deps_enable(d);
1021                                 if (d->disabled) {
1022                                         f->disabled = 1;
1023                                         return;
1024                                 }
1025                         }
1026                 }
1027         }
1028
1029         if (cpufeatures_process_feature(f))
1030                 f->enabled = 1;
1031         else
1032                 f->disabled = 1;
1033 }
1034
1035 static int __init scan_cpufeatures_subnodes(unsigned long node,
1036                                           const char *uname,
1037                                           void *data)
1038 {
1039         int *count = data;
1040
1041         process_cpufeatures_node(node, uname, *count);
1042
1043         (*count)++;
1044
1045         return 0;
1046 }
1047
1048 static int __init count_cpufeatures_subnodes(unsigned long node,
1049                                           const char *uname,
1050                                           void *data)
1051 {
1052         int *count = data;
1053
1054         (*count)++;
1055
1056         return 0;
1057 }
1058
1059 static int __init dt_cpu_ftrs_scan_callback(unsigned long node, const char
1060                                             *uname, int depth, void *data)
1061 {
1062         const __be32 *prop;
1063         int count, i;
1064         u32 isa;
1065
1066         /* We are scanning "ibm,powerpc-cpu-features" nodes only */
1067         if (!of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features"))
1068                 return 0;
1069
1070         prop = of_get_flat_dt_prop(node, "isa", NULL);
1071         if (!prop)
1072                 /* We checked before, "can't happen" */
1073                 return 0;
1074
1075         isa = be32_to_cpup(prop);
1076
1077         /* Count and allocate space for cpu features */
1078         of_scan_flat_dt_subnodes(node, count_cpufeatures_subnodes,
1079                                                 &nr_dt_cpu_features);
1080         dt_cpu_features = memblock_alloc(sizeof(struct dt_cpu_feature) * nr_dt_cpu_features, PAGE_SIZE);
1081         if (!dt_cpu_features)
1082                 panic("%s: Failed to allocate %zu bytes align=0x%lx\n",
1083                       __func__,
1084                       sizeof(struct dt_cpu_feature) * nr_dt_cpu_features,
1085                       PAGE_SIZE);
1086
1087         cpufeatures_setup_start(isa);
1088
1089         /* Scan nodes into dt_cpu_features and enable those without deps  */
1090         count = 0;
1091         of_scan_flat_dt_subnodes(node, scan_cpufeatures_subnodes, &count);
1092
1093         /* Recursive enable remaining features with dependencies */
1094         for (i = 0; i < nr_dt_cpu_features; i++) {
1095                 struct dt_cpu_feature *f = &dt_cpu_features[i];
1096
1097                 cpufeatures_deps_enable(f);
1098         }
1099
1100         prop = of_get_flat_dt_prop(node, "display-name", NULL);
1101         if (prop && strlen((char *)prop) != 0) {
1102                 strscpy(dt_cpu_name, (char *)prop, sizeof(dt_cpu_name));
1103                 cur_cpu_spec->cpu_name = dt_cpu_name;
1104         }
1105
1106         cpufeatures_setup_finished();
1107
1108         memblock_free(dt_cpu_features,
1109                       sizeof(struct dt_cpu_feature) * nr_dt_cpu_features);
1110
1111         return 0;
1112 }
1113
1114 void __init dt_cpu_ftrs_scan(void)
1115 {
1116         if (!using_dt_cpu_ftrs)
1117                 return;
1118
1119         of_scan_flat_dt(dt_cpu_ftrs_scan_callback, NULL);
1120 }