2 * This file contains low level CPU setup functions.
3 * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
12 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/ppc_asm.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/cache.h>
18 #include <asm/book3s/64/mmu-hash.h>
20 /* Entry: r3 = crap, r4 = ptr to cputable entry
22 * Note that we can be called twice for pseudo-PVRs
24 _GLOBAL(__setup_cpu_power7)
33 li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
39 _GLOBAL(__restore_cpu_power7)
48 li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
54 _GLOBAL(__setup_cpu_power8)
66 ori r3, r3, LPCR_PECEDH
67 li r4,0 /* LPES = 0 */
72 bl __init_PMU_HV_ISA207
76 _GLOBAL(__restore_cpu_power8)
89 ori r3, r3, LPCR_PECEDH
90 li r4,0 /* LPES = 0 */
95 bl __init_PMU_HV_ISA207
99 _GLOBAL(__setup_cpu_power9)
112 LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
114 LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
116 li r4,0 /* LPES = 0 */
117 bl __init_LPCR_ISA300
124 _GLOBAL(__restore_cpu_power9)
138 LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
140 LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
142 li r4,0 /* LPES = 0 */
143 bl __init_LPCR_ISA300
151 /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
155 ld r5,CPU_SPEC_FEATURES(r4)
156 LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
158 std r5,CPU_SPEC_FEATURES(r4)
162 /* Setup a sane LPCR:
163 * Called with initial LPCR in R3 and desired LPES 2-bit value in R4
165 * LPES = 0b01 (HSRR0/1 used for 0x500)
169 * VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
170 * VRMASD = 0b10000 (L=1, LP=00)
172 * Other bits untouched for now
175 rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
177 /* POWER9 has no VRMASD */
179 rldimi r3,r4, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
180 ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
182 rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
183 clrrdi r3,r3,1 /* clear HDICE */
185 rldimi r3,r5, LPCR_VC_SH, 0
192 ori r3,r3,FSCR_TAR|FSCR_EBB
198 ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
199 HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB|HFSCR_MSGP
204 * Clear the TLB using the specified IS form of tlbiel instruction
205 * (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
208 li r6,POWER7_TLB_SETS
210 li r7,0xc00 /* IS field = 0b11 */
219 li r6,POWER8_TLB_SETS
221 li r7,0xc00 /* IS field = 0b11 */
230 * Flush the TLB in hash mode. Hash must flush with RIC=2 once for process
231 * and one for partition scope to clear process and partition table entries.
234 li r6,POWER9_TLB_SETS_HASH - 1
236 li r7,0xc00 /* IS field = 0b11 */
239 PPC_TLBIEL(7, 8, 2, 1, 0)
240 PPC_TLBIEL(7, 8, 2, 0, 0)
242 PPC_TLBIEL(7, 8, 0, 0, 0)
252 __init_PMU_HV_ISA207: