2 * This file contains low level CPU setup functions.
3 * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
12 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/ppc_asm.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/cache.h>
19 /* Entry: r3 = crap, r4 = ptr to cputable entry
21 * Note that we can be called twice for pseudo-PVRs
23 _GLOBAL(__setup_cpu_power7)
37 _GLOBAL(__restore_cpu_power7)
51 _GLOBAL(__setup_cpu_power8)
62 ori r3, r3, LPCR_PECEDH
70 _GLOBAL(__restore_cpu_power8)
82 ori r3, r3, LPCR_PECEDH
91 /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
95 ld r5,CPU_SPEC_FEATURES(r4)
96 LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
98 std r5,CPU_SPEC_FEATURES(r4)
102 /* Setup a sane LPCR:
103 * Called with initial LPCR in R3
105 * LPES = 0b01 (HSRR0/1 used for 0x500)
109 * VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
110 * VRMASD = 0b10000 (L=1, LP=00)
112 * Other bits untouched for now
115 rldimi r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
116 ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
118 rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
119 clrrdi r3,r3,1 /* clear HDICE */
121 rldimi r3,r5, LPCR_VC_SH, 0
123 rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
130 ori r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
136 ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
137 HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB
142 * Clear the TLB using the specified IS form of tlbiel instruction
143 * (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
148 li r7,0xc00 /* IS field = 0b11 */
159 li r7,0xc00 /* IS field = 0b11 */