1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains low level CPU setup functions.
4 * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
7 #include <linux/linkage.h>
9 #include <asm/processor.h>
11 #include <asm/cputable.h>
12 #include <asm/ppc_asm.h>
13 #include <asm/asm-offsets.h>
14 #include <asm/cache.h>
16 #include <asm/feature-fixups.h>
18 _GLOBAL(__setup_cpu_603)
22 mtspr SPRN_SPRG_603_LRU,r10 /* init SW LRU tracking */
23 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
26 bl __init_fpu_registers
27 END_FTR_SECTION_IFCLR(CPU_FTR_FPU_UNAVAILABLE)
28 bl setup_common_caches
31 _GLOBAL(__setup_cpu_604)
33 bl setup_common_caches
37 _GLOBAL(__setup_cpu_750)
39 bl __init_fpu_registers
40 bl setup_common_caches
41 bl setup_750_7400_hid0
44 _GLOBAL(__setup_cpu_750cx)
46 bl __init_fpu_registers
47 bl setup_common_caches
48 bl setup_750_7400_hid0
52 _GLOBAL(__setup_cpu_750fx)
54 bl __init_fpu_registers
55 bl setup_common_caches
56 bl setup_750_7400_hid0
60 _GLOBAL(__setup_cpu_7400)
62 bl __init_fpu_registers
63 bl setup_7400_workarounds
64 bl setup_common_caches
65 bl setup_750_7400_hid0
68 _GLOBAL(__setup_cpu_7410)
70 bl __init_fpu_registers
71 bl setup_7410_workarounds
72 bl setup_common_caches
73 bl setup_750_7400_hid0
78 _GLOBAL(__setup_cpu_745x)
80 bl setup_common_caches
81 bl setup_745x_specifics
85 /* Enable caches for 603's, 604, 750 & 7400 */
86 SYM_FUNC_START_LOCAL(setup_common_caches)
89 ori r11,r11,HID0_ICE|HID0_DCE
91 bne 1f /* don't invalidate the D-cache */
92 ori r8,r8,HID0_DCI /* unless it wasn't enabled */
94 mtspr SPRN_HID0,r8 /* enable and invalidate caches */
96 mtspr SPRN_HID0,r11 /* enable caches */
100 SYM_FUNC_END(setup_common_caches)
102 /* 604, 604e, 604ev, ...
103 * Enable superscalar execution & branch history table
105 SYM_FUNC_START_LOCAL(setup_604_hid0)
107 ori r11,r11,HID0_SIED|HID0_BHTE
110 mtspr SPRN_HID0,r8 /* flush branch target address cache */
111 sync /* on 604e/604r */
116 SYM_FUNC_END(setup_604_hid0)
118 /* 7400 <= rev 2.7 and 7410 rev = 1.0 suffer from some
119 * erratas we work around here.
120 * Moto MPC710CE.pdf describes them, those are errata
122 * Note that we assume the firmware didn't choose to
123 * apply other workarounds (there are other ones documented
124 * in the .pdf). It appear that Apple firmware only works
125 * around #3 and with the same fix we use. We may want to
126 * check if the CPU is using 60x bus mode in which case
127 * the workaround for errata #4 is useless. Also, we may
128 * want to explicitly clear HID0_NOPDST as this is not
129 * needed once we have applied workaround #5 (though it's
130 * not set by Apple's firmware at least).
132 SYM_FUNC_START_LOCAL(setup_7400_workarounds)
138 SYM_FUNC_END(setup_7400_workarounds)
139 SYM_FUNC_START_LOCAL(setup_7410_workarounds)
145 mfspr r11,SPRN_MSSSR0
146 /* Errata #3: Set L1OPQ_SIZE to 0x10 */
149 /* Errata #4: Set L2MQ_SIZE to 1 (check for MPX mode first ?) */
151 /* Errata #5: Set DRLT_SIZE to 0x01 */
155 mtspr SPRN_MSSSR0,r11
159 SYM_FUNC_END(setup_7410_workarounds)
162 * Enable Store Gathering (SGE), Address Broadcast (ABE),
163 * Branch History Table (BHTE), Branch Target ICache (BTIC)
164 * Dynamic Power Management (DPM), Speculative (SPD)
165 * Clear Instruction cache throttling (ICTC)
167 SYM_FUNC_START_LOCAL(setup_750_7400_hid0)
169 ori r11,r11,HID0_SGE | HID0_ABE | HID0_BHTE | HID0_BTIC
170 oris r11,r11,HID0_DPM@h
172 xori r11,r11,HID0_BTIC
173 END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
175 xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */
176 END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
178 andc r11,r11,r3 /* clear SPD: enable speculative */
180 mtspr SPRN_ICTC,r3 /* Instruction Cache Throttling off */
186 SYM_FUNC_END(setup_750_7400_hid0)
189 * Looks like we have to disable NAP feature for some PLL settings...
190 * (waiting for confirmation)
192 SYM_FUNC_START_LOCAL(setup_750cx)
194 rlwinm r10,r10,4,28,31
198 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
199 cror 4*cr0+eq,4*cr0+eq,4*cr2+eq
201 lwz r6,CPU_SPEC_FEATURES(r4)
202 li r7,CPU_FTR_CAN_NAP
204 stw r6,CPU_SPEC_FEATURES(r4)
206 SYM_FUNC_END(setup_750cx)
210 SYM_FUNC_START_LOCAL(setup_750fx)
212 SYM_FUNC_END(setup_750fx)
215 * Enable Store Gathering (SGE), Branch Folding (FOLD)
216 * Branch History Table (BHTE), Branch Target ICache (BTIC)
217 * Dynamic Power Management (DPM), Speculative (SPD)
218 * Ensure our data cache instructions really operate.
219 * Timebase has to be running or we wouldn't have made it here,
220 * just ensure we don't disable it.
221 * Clear Instruction cache throttling (ICTC)
222 * Enable L2 HW prefetch
224 SYM_FUNC_START_LOCAL(setup_745x_specifics)
225 /* We check for the presence of an L3 cache setup by
226 * the firmware. If any, we disable NAP capability as
227 * it's known to be bogus on rev 2.1 and earlier
231 andis. r11,r11,L3CR_L3E@h
233 END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
234 lwz r6,CPU_SPEC_FEATURES(r4)
235 andis. r0,r6,CPU_FTR_L3_DISABLE_NAP@h
237 li r7,CPU_FTR_CAN_NAP
239 stw r6,CPU_SPEC_FEATURES(r4)
243 /* All of the bits we have to set.....
245 ori r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE
246 ori r11,r11,HID0_LRSTK | HID0_BTIC
247 oris r11,r11,HID0_DPM@h
248 BEGIN_MMU_FTR_SECTION
249 oris r11,r11,HID0_HIGH_BAT@h
250 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
252 xori r11,r11,HID0_BTIC
253 END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
255 xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */
256 END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
258 /* All of the bits we have to clear....
260 li r3,HID0_SPD | HID0_NOPDST | HID0_NOPTI
261 andc r11,r11,r3 /* clear SPD: enable speculative */
264 mtspr SPRN_ICTC,r3 /* Instruction Cache Throttling off */
270 /* Enable L2 HW prefetch, if L2 is enabled
273 andis. r3,r3,L2CR_L2E@h
282 SYM_FUNC_END(setup_745x_specifics)
285 * Initialize the FPU registers. This is needed to work around an errata
286 * in some 750 cpus where using a not yet initialized FPU register after
287 * power on reset may hang the CPU
289 _GLOBAL(__init_fpu_registers)
294 addis r9,r3,empty_zero_page@ha
295 addi r9,r9,empty_zero_page@l
301 _ASM_NOKPROBE_SYMBOL(__init_fpu_registers)
304 /* Definitions for the table use to save CPU states */
316 .balign L1_CACHE_BYTES
319 .balign L1_CACHE_BYTES,0
322 /* Called in normal context to backup CPU 0 state. This
323 * does not include cache settings. This function is also
324 * called for machine sleep. This does not include the MMU
325 * setup, BATs, etc... but rather the "special" registers
326 * like HID0, HID1, MSSCR0, etc...
328 _GLOBAL(__save_cpu_setup)
329 /* Some CR fields are volatile, we back it up all */
332 /* Get storage ptr */
333 lis r5,cpu_state_storage@h
334 ori r5,r5,cpu_state_storage@l
336 /* Save HID0 (common to all CONFIG_PPC_BOOK3S_32 cpus) */
340 /* Now deal with CPU type dependent registers */
343 cmplwi cr0,r3,0x8000 /* 7450 */
344 cmplwi cr1,r3,0x000c /* 7400 */
345 cmplwi cr2,r3,0x800c /* 7410 */
346 cmplwi cr3,r3,0x8001 /* 7455 */
347 cmplwi cr4,r3,0x8002 /* 7457 */
348 cmplwi cr5,r3,0x8003 /* 7447A */
349 cmplwi cr6,r3,0x7000 /* 750FX */
350 cmplwi cr7,r3,0x8004 /* 7448 */
351 /* cr1 is 7400 || 7410 */
352 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
354 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
355 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
356 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
357 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq
358 cror 4*cr0+eq,4*cr0+eq,4*cr7+eq
360 /* Backup 74xx specific regs */
366 /* Backup 745x specific registers */
377 /* Backup 750FX specific registers */
380 /* If rev 2.x, backup HID2 */
391 /* Called with no MMU context (typically MSR:IR/DR off) to
392 * restore CPU state as backed up by the previous
393 * function. This does not include cache setting
395 _GLOBAL(__restore_cpu_setup)
396 /* Some CR fields are volatile, we back it up all */
399 /* Get storage ptr */
400 lis r5,(cpu_state_storage-KERNELBASE)@h
401 ori r5,r5,cpu_state_storage@l
411 /* Now deal with CPU type dependent registers */
414 cmplwi cr0,r3,0x8000 /* 7450 */
415 cmplwi cr1,r3,0x000c /* 7400 */
416 cmplwi cr2,r3,0x800c /* 7410 */
417 cmplwi cr3,r3,0x8001 /* 7455 */
418 cmplwi cr4,r3,0x8002 /* 7457 */
419 cmplwi cr5,r3,0x8003 /* 7447A */
420 cmplwi cr6,r3,0x7000 /* 750FX */
421 cmplwi cr7,r3,0x8004 /* 7448 */
422 /* cr1 is 7400 || 7410 */
423 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
425 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
426 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
427 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
428 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq
429 cror 4*cr0+eq,4*cr0+eq,4*cr7+eq
431 /* Restore 74xx specific regs */
443 /* Clear 7410 L2CR2 */
447 /* Restore 745x specific registers */
469 /* Restore 750FX specific registers
470 * that is restore HID2 on rev 2.x and PLL config & switch
473 /* If rev 2.x, restore HID2 with low voltage bit cleared */
486 /* Wait for PLL to stabilize */
492 /* Setup final PLL */
497 _ASM_NOKPROBE_SYMBOL(__restore_cpu_setup)