1 /* align.c - handle alignment exceptions for the Power PC.
3 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
4 * Copyright (c) 1998-1999 TiVo, Inc.
5 * PowerPC 403GCX modifications.
6 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
7 * PowerPC 403GCX/405GP modifications.
8 * Copyright (c) 2001-2002 PPC64 team, IBM Corp
9 * 64-bit and Power4 support
10 * Copyright (c) 2005 Benjamin Herrenschmidt, IBM Corp
11 * <benh@kernel.crashing.org>
12 * Merge ppc32 and ppc64 implementations
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
20 #include <linux/kernel.h>
22 #include <asm/processor.h>
23 #include <asm/uaccess.h>
24 #include <asm/cache.h>
25 #include <asm/cputable.h>
26 #include <asm/emulated_ops.h>
27 #include <asm/switch_to.h>
28 #include <asm/disassemble.h>
36 #define INVALID { 0, 0 }
38 /* Bits in the flags field */
39 #define LD 0 /* load */
40 #define ST 1 /* store */
41 #define SE 2 /* sign-extend value, or FP ld/st as word */
42 #define F 4 /* to/from fp regs */
43 #define U 8 /* update index register */
44 #define M 0x10 /* multiple load/store */
45 #define SW 0x20 /* byte swap */
46 #define S 0x40 /* single-precision fp or... */
47 #define SX 0x40 /* ... byte count in XER */
48 #define HARD 0x80 /* string, stwcx. */
49 #define E4 0x40 /* SPE endianness is word */
50 #define E8 0x80 /* SPE endianness is double word */
51 #define SPLT 0x80 /* VSX SPLAT load */
53 /* DSISR bits reported for a DCBZ instruction: */
54 #define DCBZ 0x5f /* 8xx/82xx dcbz faults when cache not enabled */
57 * The PowerPC stores certain bits of the instruction that caused the
58 * alignment exception in the DSISR register. This array maps those
59 * bits to information about the operand length and what the
60 * instruction would do.
62 static struct aligninfo aligninfo[128] = {
63 { 4, LD }, /* 00 0 0000: lwz / lwarx */
64 INVALID, /* 00 0 0001 */
65 { 4, ST }, /* 00 0 0010: stw */
66 INVALID, /* 00 0 0011 */
67 { 2, LD }, /* 00 0 0100: lhz */
68 { 2, LD+SE }, /* 00 0 0101: lha */
69 { 2, ST }, /* 00 0 0110: sth */
70 { 4, LD+M }, /* 00 0 0111: lmw */
71 { 4, LD+F+S }, /* 00 0 1000: lfs */
72 { 8, LD+F }, /* 00 0 1001: lfd */
73 { 4, ST+F+S }, /* 00 0 1010: stfs */
74 { 8, ST+F }, /* 00 0 1011: stfd */
75 { 16, LD }, /* 00 0 1100: lq */
76 { 8, LD }, /* 00 0 1101: ld/ldu/lwa */
77 INVALID, /* 00 0 1110 */
78 { 8, ST }, /* 00 0 1111: std/stdu */
79 { 4, LD+U }, /* 00 1 0000: lwzu */
80 INVALID, /* 00 1 0001 */
81 { 4, ST+U }, /* 00 1 0010: stwu */
82 INVALID, /* 00 1 0011 */
83 { 2, LD+U }, /* 00 1 0100: lhzu */
84 { 2, LD+SE+U }, /* 00 1 0101: lhau */
85 { 2, ST+U }, /* 00 1 0110: sthu */
86 { 4, ST+M }, /* 00 1 0111: stmw */
87 { 4, LD+F+S+U }, /* 00 1 1000: lfsu */
88 { 8, LD+F+U }, /* 00 1 1001: lfdu */
89 { 4, ST+F+S+U }, /* 00 1 1010: stfsu */
90 { 8, ST+F+U }, /* 00 1 1011: stfdu */
91 { 16, LD+F }, /* 00 1 1100: lfdp */
92 INVALID, /* 00 1 1101 */
93 { 16, ST+F }, /* 00 1 1110: stfdp */
94 INVALID, /* 00 1 1111 */
95 { 8, LD }, /* 01 0 0000: ldx */
96 INVALID, /* 01 0 0001 */
97 { 8, ST }, /* 01 0 0010: stdx */
98 INVALID, /* 01 0 0011 */
99 INVALID, /* 01 0 0100 */
100 { 4, LD+SE }, /* 01 0 0101: lwax */
101 INVALID, /* 01 0 0110 */
102 INVALID, /* 01 0 0111 */
103 { 4, LD+M+HARD+SX }, /* 01 0 1000: lswx */
104 { 4, LD+M+HARD }, /* 01 0 1001: lswi */
105 { 4, ST+M+HARD+SX }, /* 01 0 1010: stswx */
106 { 4, ST+M+HARD }, /* 01 0 1011: stswi */
107 INVALID, /* 01 0 1100 */
108 { 8, LD+U }, /* 01 0 1101: ldu */
109 INVALID, /* 01 0 1110 */
110 { 8, ST+U }, /* 01 0 1111: stdu */
111 { 8, LD+U }, /* 01 1 0000: ldux */
112 INVALID, /* 01 1 0001 */
113 { 8, ST+U }, /* 01 1 0010: stdux */
114 INVALID, /* 01 1 0011 */
115 INVALID, /* 01 1 0100 */
116 { 4, LD+SE+U }, /* 01 1 0101: lwaux */
117 INVALID, /* 01 1 0110 */
118 INVALID, /* 01 1 0111 */
119 INVALID, /* 01 1 1000 */
120 INVALID, /* 01 1 1001 */
121 INVALID, /* 01 1 1010 */
122 INVALID, /* 01 1 1011 */
123 INVALID, /* 01 1 1100 */
124 INVALID, /* 01 1 1101 */
125 INVALID, /* 01 1 1110 */
126 INVALID, /* 01 1 1111 */
127 INVALID, /* 10 0 0000 */
128 INVALID, /* 10 0 0001 */
129 INVALID, /* 10 0 0010: stwcx. */
130 INVALID, /* 10 0 0011 */
131 INVALID, /* 10 0 0100 */
132 INVALID, /* 10 0 0101 */
133 INVALID, /* 10 0 0110 */
134 INVALID, /* 10 0 0111 */
135 { 4, LD+SW }, /* 10 0 1000: lwbrx */
136 INVALID, /* 10 0 1001 */
137 { 4, ST+SW }, /* 10 0 1010: stwbrx */
138 INVALID, /* 10 0 1011 */
139 { 2, LD+SW }, /* 10 0 1100: lhbrx */
140 { 4, LD+SE }, /* 10 0 1101 lwa */
141 { 2, ST+SW }, /* 10 0 1110: sthbrx */
142 { 16, ST }, /* 10 0 1111: stq */
143 INVALID, /* 10 1 0000 */
144 INVALID, /* 10 1 0001 */
145 INVALID, /* 10 1 0010 */
146 INVALID, /* 10 1 0011 */
147 INVALID, /* 10 1 0100 */
148 INVALID, /* 10 1 0101 */
149 INVALID, /* 10 1 0110 */
150 INVALID, /* 10 1 0111 */
151 INVALID, /* 10 1 1000 */
152 INVALID, /* 10 1 1001 */
153 INVALID, /* 10 1 1010 */
154 INVALID, /* 10 1 1011 */
155 INVALID, /* 10 1 1100 */
156 INVALID, /* 10 1 1101 */
157 INVALID, /* 10 1 1110 */
158 { 0, ST+HARD }, /* 10 1 1111: dcbz */
159 { 4, LD }, /* 11 0 0000: lwzx */
160 INVALID, /* 11 0 0001 */
161 { 4, ST }, /* 11 0 0010: stwx */
162 INVALID, /* 11 0 0011 */
163 { 2, LD }, /* 11 0 0100: lhzx */
164 { 2, LD+SE }, /* 11 0 0101: lhax */
165 { 2, ST }, /* 11 0 0110: sthx */
166 INVALID, /* 11 0 0111 */
167 { 4, LD+F+S }, /* 11 0 1000: lfsx */
168 { 8, LD+F }, /* 11 0 1001: lfdx */
169 { 4, ST+F+S }, /* 11 0 1010: stfsx */
170 { 8, ST+F }, /* 11 0 1011: stfdx */
171 { 16, LD+F }, /* 11 0 1100: lfdpx */
172 { 4, LD+F+SE }, /* 11 0 1101: lfiwax */
173 { 16, ST+F }, /* 11 0 1110: stfdpx */
174 { 4, ST+F }, /* 11 0 1111: stfiwx */
175 { 4, LD+U }, /* 11 1 0000: lwzux */
176 INVALID, /* 11 1 0001 */
177 { 4, ST+U }, /* 11 1 0010: stwux */
178 INVALID, /* 11 1 0011 */
179 { 2, LD+U }, /* 11 1 0100: lhzux */
180 { 2, LD+SE+U }, /* 11 1 0101: lhaux */
181 { 2, ST+U }, /* 11 1 0110: sthux */
182 INVALID, /* 11 1 0111 */
183 { 4, LD+F+S+U }, /* 11 1 1000: lfsux */
184 { 8, LD+F+U }, /* 11 1 1001: lfdux */
185 { 4, ST+F+S+U }, /* 11 1 1010: stfsux */
186 { 8, ST+F+U }, /* 11 1 1011: stfdux */
187 INVALID, /* 11 1 1100 */
188 { 4, LD+F }, /* 11 1 1101: lfiwzx */
189 INVALID, /* 11 1 1110 */
190 INVALID, /* 11 1 1111 */
194 * The dcbz (data cache block zero) instruction
195 * gives an alignment fault if used on non-cacheable
196 * memory. We handle the fault mainly for the
197 * case when we are running with the cache disabled
200 static int emulate_dcbz(struct pt_regs *regs, unsigned char __user *addr)
206 size = ppc64_caches.dline_size;
208 size = L1_CACHE_BYTES;
210 p = (long __user *) (regs->dar & -size);
211 if (user_mode(regs) && !access_ok(VERIFY_WRITE, p, size))
213 for (i = 0; i < size / sizeof(long); ++i)
214 if (__put_user_inatomic(0, p+i))
220 * Emulate load & store multiple instructions
221 * On 64-bit machines, these instructions only affect/use the
222 * bottom 4 bytes of each register, and the loads clear the
223 * top 4 bytes of the affected register.
225 #ifdef __BIG_ENDIAN__
227 #define REG_BYTE(rp, i) *((u8 *)((rp) + ((i) >> 2)) + ((i) & 3) + 4)
229 #define REG_BYTE(rp, i) *((u8 *)(rp) + (i))
233 #ifdef __LITTLE_ENDIAN__
234 #define REG_BYTE(rp, i) (*(((u8 *)((rp) + ((i)>>2)) + ((i)&3))))
237 #define SWIZ_PTR(p) ((unsigned char __user *)((p) ^ swiz))
239 #define __get_user_or_set_dar(_regs, _dest, _addr) \
242 typeof(_addr) __addr = (_addr); \
243 if (__get_user_inatomic(_dest, __addr)) { \
244 _regs->dar = (unsigned long)__addr; \
250 #define __put_user_or_set_dar(_regs, _src, _addr) \
253 typeof(_addr) __addr = (_addr); \
254 if (__put_user_inatomic(_src, __addr)) { \
255 _regs->dar = (unsigned long)__addr; \
261 static int emulate_multiple(struct pt_regs *regs, unsigned char __user *addr,
262 unsigned int reg, unsigned int nb,
263 unsigned int flags, unsigned int instr,
267 unsigned int nb0, i, bswiz;
271 * We do not try to emulate 8 bytes multiple as they aren't really
272 * available in our operating environments and we don't try to
273 * emulate multiples operations in kernel land as they should never
274 * be used/generated there at least not on unaligned boundaries
276 if (unlikely((nb > 4) || !user_mode(regs)))
279 /* lmw, stmw, lswi/x, stswi/x */
283 nb = regs->xer & 127;
287 unsigned long pc = regs->nip ^ (swiz & 4);
289 if (__get_user_or_set_dar(regs, instr,
290 (unsigned int __user *)pc))
293 if (swiz == 0 && (flags & SW))
294 instr = cpu_to_le32(instr);
295 nb = (instr >> 11) & 0x1f;
299 if (nb + reg * 4 > 128) {
300 nb0 = nb + reg * 4 - 128;
303 #ifdef __LITTLE_ENDIAN__
305 * String instructions are endian neutral but the code
306 * below is not. Force byte swapping on so that the
307 * effects of swizzling are undone in the load/store
317 if (!access_ok((flags & ST ? VERIFY_WRITE: VERIFY_READ), addr, nb+nb0))
318 return -EFAULT; /* bad address */
320 rptr = ®s->gpr[reg];
321 p = (unsigned long) addr;
322 bswiz = (flags & SW)? 3: 0;
326 * This zeroes the top 4 bytes of the affected registers
327 * in 64-bit mode, and also zeroes out any remaining
328 * bytes of the last register for lsw*.
330 memset(rptr, 0, ((nb + 3) / 4) * sizeof(unsigned long));
332 memset(®s->gpr[0], 0,
333 ((nb0 + 3) / 4) * sizeof(unsigned long));
335 for (i = 0; i < nb; ++i, ++p)
336 if (__get_user_or_set_dar(regs, REG_BYTE(rptr, i ^ bswiz),
340 rptr = ®s->gpr[0];
342 for (i = 0; i < nb0; ++i, ++p)
343 if (__get_user_or_set_dar(regs,
344 REG_BYTE(rptr, i ^ bswiz),
350 for (i = 0; i < nb; ++i, ++p)
351 if (__put_user_or_set_dar(regs, REG_BYTE(rptr, i ^ bswiz),
355 rptr = ®s->gpr[0];
357 for (i = 0; i < nb0; ++i, ++p)
358 if (__put_user_or_set_dar(regs,
359 REG_BYTE(rptr, i ^ bswiz),
368 * Emulate floating-point pair loads and stores.
369 * Only POWER6 has these instructions, and it does true little-endian,
370 * so we don't need the address swizzling.
372 static int emulate_fp_pair(struct pt_regs *regs, unsigned char __user *addr,
373 unsigned int reg, unsigned int flags)
375 char *ptr0 = (char *) ¤t->thread.TS_FPR(reg);
376 char *ptr1 = (char *) ¤t->thread.TS_FPR(reg+1);
380 return 0; /* invalid form: FRS/FRT must be even */
384 for (i = 0; i < 8; ++i) {
386 if (__get_user_or_set_dar(regs, ptr0[i^sw], addr + i))
388 if (__get_user_or_set_dar(regs, ptr1[i^sw], addr + i + 8))
391 if (__put_user_or_set_dar(regs, ptr0[i^sw], addr + i))
393 if (__put_user_or_set_dar(regs, ptr1[i^sw], addr + i + 8))
398 return 1; /* exception handled and fixed up */
402 static int emulate_lq_stq(struct pt_regs *regs, unsigned char __user *addr,
403 unsigned int reg, unsigned int flags)
405 char *ptr0 = (char *)®s->gpr[reg];
406 char *ptr1 = (char *)®s->gpr[reg+1];
410 return 0; /* invalid form: GPR must be even */
414 for (i = 0; i < 8; ++i) {
416 if (__get_user_or_set_dar(regs, ptr0[i^sw], addr + i))
418 if (__get_user_or_set_dar(regs, ptr1[i^sw], addr + i + 8))
421 if (__put_user_or_set_dar(regs, ptr0[i^sw], addr + i))
423 if (__put_user_or_set_dar(regs, ptr1[i^sw], addr + i + 8))
428 return 1; /* exception handled and fixed up */
430 #endif /* CONFIG_PPC64 */
434 static struct aligninfo spe_aligninfo[32] = {
435 { 8, LD+E8 }, /* 0 00 00: evldd[x] */
436 { 8, LD+E4 }, /* 0 00 01: evldw[x] */
437 { 8, LD }, /* 0 00 10: evldh[x] */
438 INVALID, /* 0 00 11 */
439 { 2, LD }, /* 0 01 00: evlhhesplat[x] */
440 INVALID, /* 0 01 01 */
441 { 2, LD }, /* 0 01 10: evlhhousplat[x] */
442 { 2, LD+SE }, /* 0 01 11: evlhhossplat[x] */
443 { 4, LD }, /* 0 10 00: evlwhe[x] */
444 INVALID, /* 0 10 01 */
445 { 4, LD }, /* 0 10 10: evlwhou[x] */
446 { 4, LD+SE }, /* 0 10 11: evlwhos[x] */
447 { 4, LD+E4 }, /* 0 11 00: evlwwsplat[x] */
448 INVALID, /* 0 11 01 */
449 { 4, LD }, /* 0 11 10: evlwhsplat[x] */
450 INVALID, /* 0 11 11 */
452 { 8, ST+E8 }, /* 1 00 00: evstdd[x] */
453 { 8, ST+E4 }, /* 1 00 01: evstdw[x] */
454 { 8, ST }, /* 1 00 10: evstdh[x] */
455 INVALID, /* 1 00 11 */
456 INVALID, /* 1 01 00 */
457 INVALID, /* 1 01 01 */
458 INVALID, /* 1 01 10 */
459 INVALID, /* 1 01 11 */
460 { 4, ST }, /* 1 10 00: evstwhe[x] */
461 INVALID, /* 1 10 01 */
462 { 4, ST }, /* 1 10 10: evstwho[x] */
463 INVALID, /* 1 10 11 */
464 { 4, ST+E4 }, /* 1 11 00: evstwwe[x] */
465 INVALID, /* 1 11 01 */
466 { 4, ST+E4 }, /* 1 11 10: evstwwo[x] */
467 INVALID, /* 1 11 11 */
473 #define EVLHHESPLAT 0x04
474 #define EVLHHOUSPLAT 0x06
475 #define EVLHHOSSPLAT 0x07
479 #define EVLWWSPLAT 0x0C
480 #define EVLWHSPLAT 0x0E
490 * Emulate SPE loads and stores.
491 * Only Book-E has these instructions, and it does true little-endian,
492 * so we don't need the address swizzling.
494 static int emulate_spe(struct pt_regs *regs, unsigned int reg,
504 unsigned char __user *p, *addr;
505 unsigned long *evr = ¤t->thread.evr[reg];
506 unsigned int nb, flags;
508 instr = (instr >> 1) & 0x1f;
510 /* DAR has the operand effective address */
511 addr = (unsigned char __user *)regs->dar;
513 nb = spe_aligninfo[instr].len;
514 flags = spe_aligninfo[instr].flags;
516 /* Verify the address of the operand */
517 if (unlikely(user_mode(regs) &&
518 !access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ),
523 if (unlikely(!user_mode(regs)))
526 flush_spe_to_thread(current);
528 /* If we are loading, get the data from user space, else
529 * get it from register values
538 data.w[1] = regs->gpr[reg];
541 data.h[2] = *evr >> 16;
542 data.h[3] = regs->gpr[reg] >> 16;
545 data.h[2] = *evr & 0xffff;
546 data.h[3] = regs->gpr[reg] & 0xffff;
552 data.w[1] = regs->gpr[reg];
558 temp.ll = data.ll = 0;
564 ret |= __get_user_inatomic(temp.v[0], p++);
565 ret |= __get_user_inatomic(temp.v[1], p++);
566 ret |= __get_user_inatomic(temp.v[2], p++);
567 ret |= __get_user_inatomic(temp.v[3], p++);
569 ret |= __get_user_inatomic(temp.v[4], p++);
570 ret |= __get_user_inatomic(temp.v[5], p++);
572 ret |= __get_user_inatomic(temp.v[6], p++);
573 ret |= __get_user_inatomic(temp.v[7], p++);
585 data.h[0] = temp.h[3];
586 data.h[2] = temp.h[3];
590 data.h[1] = temp.h[3];
591 data.h[3] = temp.h[3];
594 data.h[0] = temp.h[2];
595 data.h[2] = temp.h[3];
599 data.h[1] = temp.h[2];
600 data.h[3] = temp.h[3];
603 data.w[0] = temp.w[1];
604 data.w[1] = temp.w[1];
607 data.h[0] = temp.h[2];
608 data.h[1] = temp.h[2];
609 data.h[2] = temp.h[3];
610 data.h[3] = temp.h[3];
618 switch (flags & 0xf0) {
620 data.ll = swab64(data.ll);
623 data.w[0] = swab32(data.w[0]);
624 data.w[1] = swab32(data.w[1]);
626 /* Its half word endian */
628 data.h[0] = swab16(data.h[0]);
629 data.h[1] = swab16(data.h[1]);
630 data.h[2] = swab16(data.h[2]);
631 data.h[3] = swab16(data.h[3]);
637 data.w[0] = (s16)data.h[1];
638 data.w[1] = (s16)data.h[3];
641 /* Store result to memory or update registers */
647 ret |= __put_user_inatomic(data.v[0], p++);
648 ret |= __put_user_inatomic(data.v[1], p++);
649 ret |= __put_user_inatomic(data.v[2], p++);
650 ret |= __put_user_inatomic(data.v[3], p++);
652 ret |= __put_user_inatomic(data.v[4], p++);
653 ret |= __put_user_inatomic(data.v[5], p++);
655 ret |= __put_user_inatomic(data.v[6], p++);
656 ret |= __put_user_inatomic(data.v[7], p++);
662 regs->gpr[reg] = data.w[1];
667 #endif /* CONFIG_SPE */
671 * Emulate VSX instructions...
673 static int emulate_vsx(unsigned char __user *addr, unsigned int reg,
674 unsigned int areg, struct pt_regs *regs,
675 unsigned int flags, unsigned int length,
685 if (unlikely(!user_mode(regs)))
688 flush_vsx_to_thread(current);
691 ptr = (char *) ¤t->thread.fp_state.fpr[reg][0];
693 ptr = (char *) ¤t->thread.vr_state.vr[reg - 32];
695 lptr = (unsigned long *) ptr;
697 #ifdef __LITTLE_ENDIAN__
703 * The elements are BE ordered, even in LE mode, so process
704 * them in reverse order.
706 addr += length - elsize;
708 /* 8 byte memory accesses go in the top 8 bytes of the VR */
717 for (j = 0; j < length; j += elsize) {
718 for (i = 0; i < elsize; ++i) {
720 ret = __put_user_or_set_dar(regs, ptr[i^sw],
723 ret = __get_user_or_set_dar(regs, ptr[i^sw],
730 #ifdef __LITTLE_ENDIAN__
737 #ifdef __BIG_ENDIAN__
747 regs->gpr[areg] = regs->dar;
749 /* Splat load copies the same data to top and bottom 8 bytes */
751 lptr[VSX_LO] = lptr[VSX_HI];
752 /* For 8 byte loads, zero the low 8 bytes */
753 else if (!(flags & ST) && (8 == length))
763 * Called on alignment exception. Attempts to fixup
765 * Return 1 on success
766 * Return 0 if unable to handle the interrupt
767 * Return -EFAULT if data address is bad
770 int fix_alignment(struct pt_regs *regs)
772 unsigned int instr, nb, flags, instruction = 0;
773 unsigned int reg, areg;
775 unsigned char __user *addr;
776 unsigned long p, swiz;
783 #ifdef __LITTLE_ENDIAN__
792 #ifdef __LITTLE_ENDIAN__
794 unsigned char hi48[6];
796 unsigned char hi48[6];
803 * We require a complete register set, if not, then our assembly
806 CHECK_FULL_REGS(regs);
810 /* Some processors don't provide us with a DSISR we can use here,
811 * let's make one up from the instruction
813 if (cpu_has_feature(CPU_FTR_NODSISRALIGN)) {
814 unsigned long pc = regs->nip;
816 if (cpu_has_feature(CPU_FTR_PPC_LE) && (regs->msr & MSR_LE))
818 if (unlikely(__get_user_inatomic(instr,
819 (unsigned int __user *)pc)))
821 if (cpu_has_feature(CPU_FTR_REAL_LE) && (regs->msr & MSR_LE))
822 instr = cpu_to_le32(instr);
823 dsisr = make_dsisr(instr);
827 /* extract the operation and registers from the dsisr */
828 reg = (dsisr >> 5) & 0x1f; /* source/dest register */
829 areg = dsisr & 0x1f; /* register to update */
832 if ((instr >> 26) == 0x4) {
833 PPC_WARN_ALIGNMENT(spe, regs);
834 return emulate_spe(regs, reg, instr);
838 instr = (dsisr >> 10) & 0x7f;
839 instr |= (dsisr >> 13) & 0x60;
841 /* Lookup the operation in our table */
842 nb = aligninfo[instr].len;
843 flags = aligninfo[instr].flags;
846 * Handle some cases which give overlaps in the DSISR values.
848 if (IS_XFORM(instruction)) {
849 switch (get_xop(instruction)) {
850 case 532: /* ldbrx */
854 case 660: /* stdbrx */
860 case 116: /* lharx */
861 case 276: /* lqarx */
862 return 0; /* not emulated ever */
866 /* Byteswap little endian loads and stores */
868 if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) {
870 #ifdef __BIG_ENDIAN__
872 * So-called "PowerPC little endian" mode works by
873 * swizzling addresses rather than by actually doing
874 * any byte-swapping. To emulate this, we XOR each
875 * byte address with 7. We also byte-swap, because
876 * the processor's address swizzling depends on the
877 * operand size (it xors the address with 7 for bytes,
878 * 6 for halfwords, 4 for words, 0 for doublewords) but
879 * we will xor with 7 and load/store each byte separately.
881 if (cpu_has_feature(CPU_FTR_PPC_LE))
886 /* DAR has the operand effective address */
887 addr = (unsigned char __user *)regs->dar;
890 if ((instruction & 0xfc00003e) == 0x7c000018) {
893 /* Additional register addressing bit (64 VSX vs 32 FPR/GPR) */
894 reg |= (instruction & 0x1) << 5;
895 /* Simple inline decoder instead of a table */
896 /* VSX has only 8 and 16 byte memory accesses */
898 if (instruction & 0x200)
901 /* Vector stores in little-endian mode swap individual
902 elements, so process them separately */
904 if (instruction & 0x80)
908 if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE))
910 if (instruction & 0x100)
912 if (instruction & 0x040)
914 /* splat load needs a special decoder */
915 if ((instruction & 0x400) == 0){
919 PPC_WARN_ALIGNMENT(vsx, regs);
920 return emulate_vsx(addr, reg, areg, regs, flags, nb, elsize);
923 /* A size of 0 indicates an instruction we don't support, with
924 * the exception of DCBZ which is handled as a special case here
927 PPC_WARN_ALIGNMENT(dcbz, regs);
928 return emulate_dcbz(regs, addr);
930 if (unlikely(nb == 0))
933 /* Load/Store Multiple instructions are handled in their own
937 PPC_WARN_ALIGNMENT(multiple, regs);
938 return emulate_multiple(regs, addr, reg, nb,
942 /* Verify the address of the operand */
943 if (unlikely(user_mode(regs) &&
944 !access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ),
948 /* Force the fprs into the save area so we can reference them */
951 if (unlikely(!user_mode(regs)))
953 flush_fp_to_thread(current);
958 /* Special case for 16-byte FP loads and stores */
959 PPC_WARN_ALIGNMENT(fp_pair, regs);
960 return emulate_fp_pair(regs, addr, reg, flags);
963 /* Special case for 16-byte loads and stores */
964 PPC_WARN_ALIGNMENT(lq_stq, regs);
965 return emulate_lq_stq(regs, addr, reg, flags);
972 PPC_WARN_ALIGNMENT(unaligned, regs);
974 /* If we are loading, get the data from user space, else
975 * get it from register values
978 unsigned int start = 0;
982 start = offsetof(union data, x32.low32);
985 start = offsetof(union data, x16.low16);
990 p = (unsigned long)addr;
992 for (i = 0; i < nb; i++)
993 if (__get_user_or_set_dar(regs, data.v[start + i],
997 } else if (flags & F) {
998 data.ll = current->thread.TS_FPR(reg);
1000 /* Single-precision FP store requires conversion... */
1001 #ifdef CONFIG_PPC_FPU
1004 cvt_df(&data.dd, (float *)&data.x32.low32);
1011 data.ll = regs->gpr[reg];
1016 data.ll = swab64(data.ll);
1019 data.x32.low32 = swab32(data.x32.low32);
1022 data.x16.low16 = swab16(data.x16.low16);
1027 /* Perform other misc operations like sign extension
1028 * or floating point single precision conversion
1030 switch (flags & ~(U|SW)) {
1031 case LD+SE: /* sign extending integer loads */
1032 case LD+F+SE: /* sign extend for lfiwax */
1034 data.ll = data.x16.low16;
1035 else /* nb must be 4 */
1036 data.ll = data.x32.low32;
1039 /* Single-precision FP load requires conversion... */
1041 #ifdef CONFIG_PPC_FPU
1044 cvt_fd((float *)&data.x32.low32, &data.dd);
1052 /* Store result to memory or update registers */
1054 unsigned int start = 0;
1058 start = offsetof(union data, x32.low32);
1061 start = offsetof(union data, x16.low16);
1065 p = (unsigned long)addr;
1067 for (i = 0; i < nb; i++)
1068 if (__put_user_or_set_dar(regs, data.v[start + i],
1072 } else if (flags & F)
1073 current->thread.TS_FPR(reg) = data.ll;
1075 regs->gpr[reg] = data.ll;
1077 /* Update RA as needed */
1079 regs->gpr[areg] = regs->dar;