1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 #ifndef _UAPI_ASM_POWERPC_PERF_REGS_H
3 #define _UAPI_ASM_POWERPC_PERF_REGS_H
5 enum perf_event_powerpc_regs {
40 PERF_REG_POWERPC_ORIG_R3,
42 PERF_REG_POWERPC_LINK,
45 PERF_REG_POWERPC_SOFTE,
46 PERF_REG_POWERPC_TRAP,
48 PERF_REG_POWERPC_DSISR,
49 PERF_REG_POWERPC_SIER,
50 PERF_REG_POWERPC_MMCRA,
51 /* Extended registers */
52 PERF_REG_POWERPC_MMCR0,
53 PERF_REG_POWERPC_MMCR1,
54 PERF_REG_POWERPC_MMCR2,
55 PERF_REG_POWERPC_MMCR3,
56 PERF_REG_POWERPC_SIER2,
57 PERF_REG_POWERPC_SIER3,
58 PERF_REG_POWERPC_PMC1,
59 PERF_REG_POWERPC_PMC2,
60 PERF_REG_POWERPC_PMC3,
61 PERF_REG_POWERPC_PMC4,
62 PERF_REG_POWERPC_PMC5,
63 PERF_REG_POWERPC_PMC6,
64 PERF_REG_POWERPC_SDAR,
65 PERF_REG_POWERPC_SIAR,
66 /* Max mask value for interrupt regs w/o extended regs */
67 PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1,
68 /* Max mask value for interrupt regs including extended regs */
69 PERF_REG_EXTENDED_MAX = PERF_REG_POWERPC_SIAR + 1,
72 #define PERF_REG_PMU_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1)
75 * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300
76 * includes 11 SPRS from MMCR0 to SIAR excluding the
77 * unsupported SPRS MMCR3, SIER2 and SIER3.
79 #define PERF_REG_PMU_MASK_300 \
80 ((1ULL << PERF_REG_POWERPC_MMCR0) | (1ULL << PERF_REG_POWERPC_MMCR1) | \
81 (1ULL << PERF_REG_POWERPC_MMCR2) | (1ULL << PERF_REG_POWERPC_PMC1) | \
82 (1ULL << PERF_REG_POWERPC_PMC2) | (1ULL << PERF_REG_POWERPC_PMC3) | \
83 (1ULL << PERF_REG_POWERPC_PMC4) | (1ULL << PERF_REG_POWERPC_PMC5) | \
84 (1ULL << PERF_REG_POWERPC_PMC6) | (1ULL << PERF_REG_POWERPC_SDAR) | \
85 (1ULL << PERF_REG_POWERPC_SIAR))
88 * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31
89 * includes 14 SPRs from MMCR0 to SIAR.
91 #define PERF_REG_PMU_MASK_31 \
92 (PERF_REG_PMU_MASK_300 | (1ULL << PERF_REG_POWERPC_MMCR3) | \
93 (1ULL << PERF_REG_POWERPC_SIER2) | (1ULL << PERF_REG_POWERPC_SIER3))
95 #endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */