2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
4 #ifndef _ASM_POWERPC_PPC_ASM_H
5 #define _ASM_POWERPC_PPC_ASM_H
7 #include <linux/stringify.h>
8 #include <asm/asm-compat.h>
9 #include <asm/processor.h>
10 #include <asm/ppc-opcode.h>
11 #include <asm/firmware.h>
12 #include <asm/feature-fixups.h>
13 #include <asm/extable.h>
17 #define SZL (BITS_PER_LONG/8)
20 * This expands to a sequence of operations with reg incrementing from
21 * start to end inclusive, of this form:
23 * op reg, (offset + (width * reg))(base)
25 * Note that offset is not the offset of the first operation unless start
26 * is zero (or width is zero).
28 .macro OP_REGS op, width, start, end, base, offset
30 .rept (\end - \start + 1)
31 \op .Lreg, \offset + \width * .Lreg(\base)
37 * This expands to a sequence of register clears for regs start to end
38 * inclusive, of the form:
42 .macro ZEROIZE_REGS start, end
44 .rept (\end - \start + 1)
51 * Macros for storing registers into and loading registers from
55 #define SAVE_GPRS(start, end, base) OP_REGS std, 8, start, end, base, GPR0
56 #define REST_GPRS(start, end, base) OP_REGS ld, 8, start, end, base, GPR0
57 #define SAVE_NVGPRS(base) SAVE_GPRS(14, 31, base)
58 #define REST_NVGPRS(base) REST_GPRS(14, 31, base)
60 #define SAVE_GPRS(start, end, base) OP_REGS stw, 4, start, end, base, GPR0
61 #define REST_GPRS(start, end, base) OP_REGS lwz, 4, start, end, base, GPR0
62 #define SAVE_NVGPRS(base) SAVE_GPRS(13, 31, base)
63 #define REST_NVGPRS(base) REST_GPRS(13, 31, base)
66 #define ZEROIZE_GPRS(start, end) ZEROIZE_REGS start, end
68 #define ZEROIZE_NVGPRS() ZEROIZE_GPRS(14, 31)
70 #define ZEROIZE_NVGPRS() ZEROIZE_GPRS(13, 31)
72 #define ZEROIZE_GPR(n) ZEROIZE_GPRS(n, n)
74 #define SAVE_GPR(n, base) SAVE_GPRS(n, n, base)
75 #define REST_GPR(n, base) REST_GPRS(n, n, base)
77 /* macros for handling user register sanitisation */
78 #ifdef CONFIG_INTERRUPT_SANITIZE_REGISTERS
79 #define SANITIZE_SYSCALL_GPRS() ZEROIZE_GPR(0); \
80 ZEROIZE_GPRS(5, 12); \
82 #define SANITIZE_GPR(n) ZEROIZE_GPR(n)
83 #define SANITIZE_GPRS(start, end) ZEROIZE_GPRS(start, end)
84 #define SANITIZE_NVGPRS() ZEROIZE_NVGPRS()
85 #define SANITIZE_RESTORE_NVGPRS() REST_NVGPRS(r1)
86 #define HANDLER_RESTORE_NVGPRS()
88 #define SANITIZE_SYSCALL_GPRS()
89 #define SANITIZE_GPR(n)
90 #define SANITIZE_GPRS(start, end)
91 #define SANITIZE_NVGPRS()
92 #define SANITIZE_RESTORE_NVGPRS()
93 #define HANDLER_RESTORE_NVGPRS() REST_NVGPRS(r1)
94 #endif /* CONFIG_INTERRUPT_SANITIZE_REGISTERS */
96 #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base)
97 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
98 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
99 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
100 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
101 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
102 #define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base)
103 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
104 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
105 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
106 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
107 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
109 #define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b
110 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
111 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
112 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
113 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
114 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
115 #define REST_VR(n,b,base) li b,16*(n); lvx n,base,b
116 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
117 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
118 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
119 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
120 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
122 #ifdef __BIG_ENDIAN__
123 #define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base)
124 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base)
126 #define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \
130 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \
133 /* Save the lower 32 VSRs in the thread VSR region */
134 #define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b)
135 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
136 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
137 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
138 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
139 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
140 #define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b)
141 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
142 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
143 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
144 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
145 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
148 * b = base register for addressing, o = base offset from register of 1st EVR
149 * n = first EVR, s = scratch
151 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b)
152 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
153 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
154 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
155 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
156 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
157 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n
158 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
159 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
160 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
161 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
162 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
164 /* Macros to adjust thread priority for hardware multithreading */
165 #define HMT_VERY_LOW or 31,31,31 # very low priority
166 #define HMT_LOW or 1,1,1
167 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
168 #define HMT_MEDIUM or 2,2,2
169 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
170 #define HMT_HIGH or 3,3,3
171 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only
178 #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
179 #define VCPU_GPR(n) __VCPU_GPR(__REG_##n)
184 * Used to name C functions called from asm
186 #ifdef CONFIG_PPC_KERNEL_PCREL
187 #define CFUNC(name) name@notoc
189 #define CFUNC(name) name
193 * We use __powerpc64__ here because we want the compat VDSO to use the 32-bit
194 * version below in the else case of the ifdef.
198 #define STACKFRAMESIZE 256
199 #define __STK_REG(i) (112 + ((i)-14)*8)
200 #define STK_REG(i) __STK_REG(__REG_##i)
202 #ifdef CONFIG_PPC64_ELF_ABI_V2
204 #define __STK_PARAM(i) (32 + ((i)-3)*8)
207 #define __STK_PARAM(i) (48 + ((i)-3)*8)
209 #define STK_PARAM(i) __STK_PARAM(__REG_##i)
211 #ifdef CONFIG_PPC64_ELF_ABI_V2
213 #define _GLOBAL(name) \
215 .type name,@function; \
219 #ifdef CONFIG_PPC_KERNEL_PCREL
220 #define _GLOBAL_TOC _GLOBAL
222 #define _GLOBAL_TOC(name) \
224 .type name,@function; \
227 0: addis r2,r12,(.TOC.-0b)@ha; \
228 addi r2,r2,(.TOC.-0b)@l; \
229 .localentry name,.-name
236 #define XGLUE(a,b) a##b
237 #define GLUE(a,b) XGLUE(a,b)
239 #define _GLOBAL(name) \
242 .globl GLUE(.,name); \
243 .pushsection ".opd","aw"; \
245 .quad GLUE(.,name); \
246 .quad .TOC.@tocbase; \
249 .type GLUE(.,name),@function; \
252 #define _GLOBAL_TOC(name) _GLOBAL(name)
254 #define DOTSYM(a) GLUE(.,a)
264 #define _GLOBAL_TOC(name) _GLOBAL(name)
271 * __kprobes (the C annotation) puts the symbol into the .kprobes.text
272 * section, which gets emitted at the end of regular text.
274 * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to
275 * a blacklist. The former is for core kprobe functions/data, the
276 * latter is for those that incdentially must be excluded from probing
277 * and allows them to be linked at more optimal location within text.
279 #ifdef CONFIG_KPROBES
280 #define _ASM_NOKPROBE_SYMBOL(entry) \
281 .pushsection "_kprobe_blacklist","aw"; \
285 #define _ASM_NOKPROBE_SYMBOL(entry)
288 #define FUNC_START(name) _GLOBAL(name)
289 #define FUNC_END(name)
292 * LOAD_REG_IMMEDIATE(rn, expr)
293 * Loads the value of the constant expression 'expr' into register 'rn'
294 * using immediate instructions only. Use this when it's important not
295 * to reference other data (i.e. on ppc64 when the TOC pointer is not
296 * valid) and when 'expr' is a constant or absolute address.
298 * LOAD_REG_ADDR(rn, name)
299 * Loads the address of label 'name' into register 'rn'. Use this when
300 * you don't particularly need immediate instructions only, but you need
301 * the whole address in one register (e.g. it's a structure address and
302 * you want to access various offsets within it). On ppc32 this is
303 * identical to LOAD_REG_IMMEDIATE.
305 * LOAD_REG_ADDR_PIC(rn, name)
306 * Loads the address of label 'name' into register 'run'. Use this when
307 * the kernel doesn't run at the linked or relocated address. Please
308 * note that this macro will clobber the lr register.
310 * LOAD_REG_ADDRBASE(rn, name)
312 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
313 * register 'rn'. ADDROFF(name) returns the remainder of the address as
314 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
315 * in size, so is suitable for use directly as an offset in load and store
316 * instructions. Use this when loading/storing a single word or less as:
317 * LOAD_REG_ADDRBASE(rX, name)
318 * ld rY,ADDROFF(name)(rX)
321 /* Be careful, this will clobber the lr register. */
322 #define LOAD_REG_ADDR_PIC(reg, name) \
325 addis reg,reg,(name - 0b)@ha; \
326 addi reg,reg,(name - 0b)@l;
328 #if defined(__powerpc64__) && defined(HAVE_AS_ATHIGH)
329 #define __AS_ATHIGH high
331 #define __AS_ATHIGH h
334 .macro __LOAD_REG_IMMEDIATE_32 r, x
335 .if (\x) >= 0x8000 || (\x) < -0x8000
336 lis \r, (\x)@__AS_ATHIGH
337 .if (\x) & 0xffff != 0
345 .macro __LOAD_REG_IMMEDIATE r, x
346 .if (\x) >= 0x80000000 || (\x) < -0x80000000
347 __LOAD_REG_IMMEDIATE_32 \r, (\x) >> 32
349 .if (\x) & 0xffff0000 != 0
350 oris \r, \r, (\x)@__AS_ATHIGH
352 .if (\x) & 0xffff != 0
356 __LOAD_REG_IMMEDIATE_32 \r, \x
362 #ifdef CONFIG_PPC_KERNEL_PCREL
363 #define __LOAD_PACA_TOC(reg) \
366 #define __LOAD_PACA_TOC(reg) \
370 #define LOAD_PACA_TOC() \
373 #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr
375 #define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \
376 lis tmp, (expr)@highest; \
377 lis reg, (expr)@__AS_ATHIGH; \
378 ori tmp, tmp, (expr)@higher; \
379 ori reg, reg, (expr)@l; \
380 rldimi reg, tmp, 32, 0
382 #ifdef CONFIG_PPC_KERNEL_PCREL
383 #define LOAD_REG_ADDR(reg,name) \
387 #define LOAD_REG_ADDR(reg,name) \
388 addis reg,r2,name@toc@ha; \
389 addi reg,reg,name@toc@l
392 #ifdef CONFIG_PPC_BOOK3E_64
394 * This is used in register-constrained interrupt handlers. Not to be used
395 * by BOOK3S. ld complains with "got/toc optimization is not supported" if r2
396 * is not used for the TOC offset, so use @got(tocreg). If the interrupt
397 * handlers saved r2 instead, LOAD_REG_ADDR could be used.
399 #define LOAD_REG_ADDR_ALTTOC(reg,tocreg,name) \
400 ld reg,name@got(tocreg)
403 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
404 #define ADDROFF(name) 0
406 /* offsets for stack frame layout */
410 * GCC stack frames follow a different pattern on 32 vs 64. This can be used
411 * to make asm frames be consistent with C.
413 #define PPC_CREATE_STACK_FRAME(size) \
420 #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr
422 #define LOAD_REG_IMMEDIATE_SYM(reg,expr) \
424 addi reg,reg,(expr)@l;
426 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE_SYM(reg, name)
428 #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha
429 #define ADDROFF(name) name@l
431 /* offsets for stack frame layout */
434 #define PPC_CREATE_STACK_FRAME(size) \
435 stwu r1,-(size)(r1); \
441 /* various errata or part fixups */
442 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_E500)
444 90: mfspr dest, SPRN_TBRL; \
445 BEGIN_FTR_SECTION_NESTED(96); \
448 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
450 #define MFTB(dest) MFTBL(dest)
453 #ifdef CONFIG_PPC_8xx
454 #define MFTBL(dest) mftb dest
455 #define MFTBU(dest) mftbu dest
457 #define MFTBL(dest) mfspr dest, SPRN_TBRL
458 #define MFTBU(dest) mfspr dest, SPRN_TBRU
464 #define TLBSYNC tlbsync; sync
468 #define MTOCRF(FXM, RS) \
469 BEGIN_FTR_SECTION_NESTED(848); \
471 FTR_SECTION_ELSE_NESTED(848); \
473 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
477 * This instruction is not implemented on the PPC 603 or 601; however, on
478 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
479 * All of these instructions exist in the 8xx, they have magical powers,
480 * and they must be used.
483 #if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx)
487 lis r4,KERNELBASE@h; \
497 #ifdef CONFIG_IBM440EP_ERR42
498 #define PPC440EP_ERR42 isync
500 #define PPC440EP_ERR42
503 /* The following stops all load and store data streams associated with stream
504 * ID (ie. streams created explicitly). The embedded and server mnemonics for
505 * dcbt are different so this must only be used for server.
507 #define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch) \
508 lis scratch,0x60000000@h; \
509 dcbt 0,scratch,0b01010
512 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
513 * keep the address intact to be compatible with code shared with
516 * On the other hand, I find it useful to have them behave as expected
517 * by their name (ie always do the addition) on 64-bit BookE
519 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
524 * We use addis to ensure compatibility with the "classic" ppc versions of
525 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
526 * converting the address in r0, and so this version has to do that too
527 * (i.e. set register rd to 0 when rs == 0).
529 #define tophys(rd,rs) \
532 #define tovirt(rd,rs) \
535 #elif defined(CONFIG_PPC64)
536 #define toreal(rd) /* we can access c000... in real mode */
539 #define tophys(rd,rs) \
542 #define tovirt(rd,rs) \
544 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
547 #define toreal(rd) tophys(rd,rd)
548 #define fromreal(rd) tovirt(rd,rd)
550 #define tophys(rd, rs) addis rd, rs, -PAGE_OFFSET@h
551 #define tovirt(rd, rs) addis rd, rs, PAGE_OFFSET@h
554 #ifdef CONFIG_PPC_BOOK3S_64
555 #define MTMSRD(r) mtmsrd r
556 #define MTMSR_EERI(reg) mtmsrd reg,1
558 #define MTMSRD(r) mtmsr r
559 #define MTMSR_EERI(reg) mtmsr reg
562 #endif /* __KERNEL__ */
564 /* The boring bits... */
566 /* Condition Register Bit Fields */
579 * General Purpose Registers (GPRs)
581 * The lower case r0-r31 should be used in preference to the upper
582 * case R0-R31 as they provide more error checking in the assembler.
583 * Use R0-31 only when really nessesary.
620 /* Floating Point Registers (FPRs) */
655 /* AltiVec Registers (VPRs) */
690 /* VSX Registers (VSRs) */
757 /* SPE Registers (EVPRs) */
792 #define RFSCV .long 0x4c0000a4
795 * Create an endian fixup trampoline
797 * This starts with a "tdi 0,0,0x48" instruction which is
798 * essentially a "trap never", and thus akin to a nop.
800 * The opcode for this instruction read with the wrong endian
801 * however results in a b . + 8
803 * So essentially we use that trick to execute the following
804 * trampoline in "reverse endian" if we are running with the
805 * MSR_LE bit set the "wrong" way for whatever endianness the
806 * kernel is built for.
809 #ifdef CONFIG_PPC_BOOK3E_64
813 * This version may be used in HV or non-HV context.
814 * MSR[EE] must be disabled.
816 #define FIXUP_ENDIAN \
817 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
818 b 191f; /* Skip trampoline if endian is good */ \
819 .long 0xa600607d; /* mfmsr r11 */ \
820 .long 0x01006b69; /* xori r11,r11,1 */ \
821 .long 0x00004039; /* li r10,0 */ \
822 .long 0x6401417d; /* mtmsrd r10,1 */ \
823 .long 0x05009f42; /* bcl 20,31,$+4 */ \
824 .long 0xa602487d; /* mflr r10 */ \
825 .long 0x14004a39; /* addi r10,r10,20 */ \
826 .long 0xa6035a7d; /* mtsrr0 r10 */ \
827 .long 0xa6037b7d; /* mtsrr1 r11 */ \
828 .long 0x2400004c; /* rfid */ \
832 * This version that may only be used with MSR[HV]=1
833 * - Does not clear MSR[RI], so more robust.
834 * - Slightly smaller and faster.
836 #define FIXUP_ENDIAN_HV \
837 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
838 b 191f; /* Skip trampoline if endian is good */ \
839 .long 0xa600607d; /* mfmsr r11 */ \
840 .long 0x01006b69; /* xori r11,r11,1 */ \
841 .long 0x05009f42; /* bcl 20,31,$+4 */ \
842 .long 0xa602487d; /* mflr r10 */ \
843 .long 0x14004a39; /* addi r10,r10,20 */ \
844 .long 0xa64b5a7d; /* mthsrr0 r10 */ \
845 .long 0xa64b7b7d; /* mthsrr1 r11 */ \
846 .long 0x2402004c; /* hrfid */ \
849 #endif /* !CONFIG_PPC_BOOK3E_64 */
851 #endif /* __ASSEMBLY__ */
853 #define SOFT_MASK_TABLE(_start, _end) \
854 stringify_in_c(.section __soft_mask_table,"a";)\
855 stringify_in_c(.balign 8;) \
856 stringify_in_c(.llong (_start);) \
857 stringify_in_c(.llong (_end);) \
858 stringify_in_c(.previous)
860 #define RESTART_TABLE(_start, _end, _target) \
861 stringify_in_c(.section __restart_table,"a";)\
862 stringify_in_c(.balign 8;) \
863 stringify_in_c(.llong (_start);) \
864 stringify_in_c(.llong (_end);) \
865 stringify_in_c(.llong (_target);) \
866 stringify_in_c(.previous)
868 #ifdef CONFIG_PPC_E500
869 #define BTB_FLUSH(reg) \
870 lis reg,BUCSR_INIT@h; \
871 ori reg,reg,BUCSR_INIT@l; \
872 mtspr SPRN_BUCSR,reg; \
875 #define BTB_FLUSH(reg)
876 #endif /* CONFIG_PPC_E500 */
878 #if defined(CONFIG_PPC64_ELF_ABI_V1)
879 #define STACK_FRAME_PARAMS 48
880 #elif defined(CONFIG_PPC64_ELF_ABI_V2)
881 #define STACK_FRAME_PARAMS 32
882 #elif defined(CONFIG_PPC32)
883 #define STACK_FRAME_PARAMS 8
886 #endif /* _ASM_POWERPC_PPC_ASM_H */