2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
4 #ifndef _ASM_POWERPC_PPC_ASM_H
5 #define _ASM_POWERPC_PPC_ASM_H
7 #include <linux/stringify.h>
8 #include <asm/asm-compat.h>
9 #include <asm/processor.h>
10 #include <asm/ppc-opcode.h>
11 #include <asm/firmware.h>
12 #include <asm/feature-fixups.h>
13 #include <asm/extable.h>
17 #define SZL (BITS_PER_LONG/8)
20 * This expands to a sequence of operations with reg incrementing from
21 * start to end inclusive, of this form:
23 * op reg, (offset + (width * reg))(base)
25 * Note that offset is not the offset of the first operation unless start
26 * is zero (or width is zero).
28 .macro OP_REGS op, width, start, end, base, offset
30 .rept (\end - \start + 1)
31 \op .Lreg, \offset + \width * .Lreg(\base)
37 * Macros for storing registers into and loading registers from
41 #define SAVE_GPRS(start, end, base) OP_REGS std, 8, start, end, base, GPR0
42 #define REST_GPRS(start, end, base) OP_REGS ld, 8, start, end, base, GPR0
43 #define SAVE_NVGPRS(base) SAVE_GPRS(14, 31, base)
44 #define REST_NVGPRS(base) REST_GPRS(14, 31, base)
46 #define SAVE_GPRS(start, end, base) OP_REGS stw, 4, start, end, base, GPR0
47 #define REST_GPRS(start, end, base) OP_REGS lwz, 4, start, end, base, GPR0
48 #define SAVE_NVGPRS(base) SAVE_GPRS(13, 31, base)
49 #define REST_NVGPRS(base) REST_GPRS(13, 31, base)
52 #define SAVE_GPR(n, base) SAVE_GPRS(n, n, base)
53 #define REST_GPR(n, base) REST_GPRS(n, n, base)
55 #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base)
56 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
57 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
58 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
59 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
60 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
61 #define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base)
62 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
63 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
64 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
65 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
66 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
68 #define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b
69 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
70 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
71 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
72 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
73 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
74 #define REST_VR(n,b,base) li b,16*(n); lvx n,base,b
75 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
76 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
77 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
78 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
79 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
82 #define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base)
83 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base)
85 #define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \
89 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \
92 /* Save the lower 32 VSRs in the thread VSR region */
93 #define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b)
94 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
95 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
96 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
97 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
98 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
99 #define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b)
100 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
101 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
102 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
103 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
104 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
107 * b = base register for addressing, o = base offset from register of 1st EVR
108 * n = first EVR, s = scratch
110 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b)
111 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
112 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
113 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
114 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
115 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
116 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n
117 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
118 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
119 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
120 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
121 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
123 /* Macros to adjust thread priority for hardware multithreading */
124 #define HMT_VERY_LOW or 31,31,31 # very low priority
125 #define HMT_LOW or 1,1,1
126 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
127 #define HMT_MEDIUM or 2,2,2
128 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
129 #define HMT_HIGH or 3,3,3
130 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only
137 #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
138 #define VCPU_GPR(n) __VCPU_GPR(__REG_##n)
143 * We use __powerpc64__ here because we want the compat VDSO to use the 32-bit
144 * version below in the else case of the ifdef.
148 #define STACKFRAMESIZE 256
149 #define __STK_REG(i) (112 + ((i)-14)*8)
150 #define STK_REG(i) __STK_REG(__REG_##i)
152 #ifdef PPC64_ELF_ABI_v2
154 #define __STK_PARAM(i) (32 + ((i)-3)*8)
157 #define __STK_PARAM(i) (48 + ((i)-3)*8)
159 #define STK_PARAM(i) __STK_PARAM(__REG_##i)
161 #ifdef PPC64_ELF_ABI_v2
163 #define _GLOBAL(name) \
165 .type name,@function; \
169 #define _GLOBAL_TOC(name) \
171 .type name,@function; \
174 0: addis r2,r12,(.TOC.-0b)@ha; \
175 addi r2,r2,(.TOC.-0b)@l; \
176 .localentry name,.-name
182 #define XGLUE(a,b) a##b
183 #define GLUE(a,b) XGLUE(a,b)
185 #define _GLOBAL(name) \
188 .globl GLUE(.,name); \
189 .pushsection ".opd","aw"; \
191 .quad GLUE(.,name); \
192 .quad .TOC.@tocbase; \
195 .type GLUE(.,name),@function; \
198 #define _GLOBAL_TOC(name) _GLOBAL(name)
200 #define DOTSYM(a) GLUE(.,a)
211 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
215 #define _GLOBAL_TOC(name) _GLOBAL(name)
222 * __kprobes (the C annotation) puts the symbol into the .kprobes.text
223 * section, which gets emitted at the end of regular text.
225 * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to
226 * a blacklist. The former is for core kprobe functions/data, the
227 * latter is for those that incdentially must be excluded from probing
228 * and allows them to be linked at more optimal location within text.
230 #ifdef CONFIG_KPROBES
231 #define _ASM_NOKPROBE_SYMBOL(entry) \
232 .pushsection "_kprobe_blacklist","aw"; \
236 #define _ASM_NOKPROBE_SYMBOL(entry)
239 #define FUNC_START(name) _GLOBAL(name)
240 #define FUNC_END(name)
243 * LOAD_REG_IMMEDIATE(rn, expr)
244 * Loads the value of the constant expression 'expr' into register 'rn'
245 * using immediate instructions only. Use this when it's important not
246 * to reference other data (i.e. on ppc64 when the TOC pointer is not
247 * valid) and when 'expr' is a constant or absolute address.
249 * LOAD_REG_ADDR(rn, name)
250 * Loads the address of label 'name' into register 'rn'. Use this when
251 * you don't particularly need immediate instructions only, but you need
252 * the whole address in one register (e.g. it's a structure address and
253 * you want to access various offsets within it). On ppc32 this is
254 * identical to LOAD_REG_IMMEDIATE.
256 * LOAD_REG_ADDR_PIC(rn, name)
257 * Loads the address of label 'name' into register 'run'. Use this when
258 * the kernel doesn't run at the linked or relocated address. Please
259 * note that this macro will clobber the lr register.
261 * LOAD_REG_ADDRBASE(rn, name)
263 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
264 * register 'rn'. ADDROFF(name) returns the remainder of the address as
265 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
266 * in size, so is suitable for use directly as an offset in load and store
267 * instructions. Use this when loading/storing a single word or less as:
268 * LOAD_REG_ADDRBASE(rX, name)
269 * ld rY,ADDROFF(name)(rX)
272 /* Be careful, this will clobber the lr register. */
273 #define LOAD_REG_ADDR_PIC(reg, name) \
276 addis reg,reg,(name - 0b)@ha; \
277 addi reg,reg,(name - 0b)@l;
279 #if defined(__powerpc64__) && defined(HAVE_AS_ATHIGH)
280 #define __AS_ATHIGH high
282 #define __AS_ATHIGH h
285 .macro __LOAD_REG_IMMEDIATE_32 r, x
286 .if (\x) >= 0x8000 || (\x) < -0x8000
287 lis \r, (\x)@__AS_ATHIGH
288 .if (\x) & 0xffff != 0
296 .macro __LOAD_REG_IMMEDIATE r, x
297 .if (\x) >= 0x80000000 || (\x) < -0x80000000
298 __LOAD_REG_IMMEDIATE_32 \r, (\x) >> 32
300 .if (\x) & 0xffff0000 != 0
301 oris \r, \r, (\x)@__AS_ATHIGH
303 .if (\x) & 0xffff != 0
307 __LOAD_REG_IMMEDIATE_32 \r, \x
313 #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr
315 #define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \
316 lis tmp, (expr)@highest; \
317 lis reg, (expr)@__AS_ATHIGH; \
318 ori tmp, tmp, (expr)@higher; \
319 ori reg, reg, (expr)@l; \
320 rldimi reg, tmp, 32, 0
322 #define LOAD_REG_ADDR(reg,name) \
325 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
326 #define ADDROFF(name) 0
328 /* offsets for stack frame layout */
333 #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr
335 #define LOAD_REG_IMMEDIATE_SYM(reg,expr) \
337 addi reg,reg,(expr)@l;
339 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE_SYM(reg, name)
341 #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha
342 #define ADDROFF(name) name@l
344 /* offsets for stack frame layout */
349 /* various errata or part fixups */
350 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
352 90: mfspr dest, SPRN_TBRL; \
353 BEGIN_FTR_SECTION_NESTED(96); \
356 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
358 #define MFTB(dest) MFTBL(dest)
361 #ifdef CONFIG_PPC_8xx
362 #define MFTBL(dest) mftb dest
363 #define MFTBU(dest) mftbu dest
365 #define MFTBL(dest) mfspr dest, SPRN_TBRL
366 #define MFTBU(dest) mfspr dest, SPRN_TBRU
372 #define TLBSYNC tlbsync; sync
376 #define MTOCRF(FXM, RS) \
377 BEGIN_FTR_SECTION_NESTED(848); \
379 FTR_SECTION_ELSE_NESTED(848); \
381 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
385 * This instruction is not implemented on the PPC 603 or 601; however, on
386 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
387 * All of these instructions exist in the 8xx, they have magical powers,
388 * and they must be used.
391 #if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx)
395 lis r4,KERNELBASE@h; \
405 #ifdef CONFIG_IBM440EP_ERR42
406 #define PPC440EP_ERR42 isync
408 #define PPC440EP_ERR42
411 /* The following stops all load and store data streams associated with stream
412 * ID (ie. streams created explicitly). The embedded and server mnemonics for
413 * dcbt are different so this must only be used for server.
415 #define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch) \
416 lis scratch,0x60000000@h; \
417 dcbt 0,scratch,0b01010
420 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
421 * keep the address intact to be compatible with code shared with
424 * On the other hand, I find it useful to have them behave as expected
425 * by their name (ie always do the addition) on 64-bit BookE
427 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
432 * We use addis to ensure compatibility with the "classic" ppc versions of
433 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
434 * converting the address in r0, and so this version has to do that too
435 * (i.e. set register rd to 0 when rs == 0).
437 #define tophys(rd,rs) \
440 #define tovirt(rd,rs) \
443 #elif defined(CONFIG_PPC64)
444 #define toreal(rd) /* we can access c000... in real mode */
447 #define tophys(rd,rs) \
450 #define tovirt(rd,rs) \
452 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
455 #define toreal(rd) tophys(rd,rd)
456 #define fromreal(rd) tovirt(rd,rd)
458 #define tophys(rd, rs) addis rd, rs, -PAGE_OFFSET@h
459 #define tovirt(rd, rs) addis rd, rs, PAGE_OFFSET@h
462 #ifdef CONFIG_PPC_BOOK3S_64
463 #define MTMSRD(r) mtmsrd r
464 #define MTMSR_EERI(reg) mtmsrd reg,1
466 #define MTMSRD(r) mtmsr r
467 #define MTMSR_EERI(reg) mtmsr reg
470 #endif /* __KERNEL__ */
472 /* The boring bits... */
474 /* Condition Register Bit Fields */
487 * General Purpose Registers (GPRs)
489 * The lower case r0-r31 should be used in preference to the upper
490 * case R0-R31 as they provide more error checking in the assembler.
491 * Use R0-31 only when really nessesary.
528 /* Floating Point Registers (FPRs) */
563 /* AltiVec Registers (VPRs) */
598 /* VSX Registers (VSRs) */
665 /* SPE Registers (EVPRs) */
700 /* some stab codes */
706 #define RFSCV .long 0x4c0000a4
709 * Create an endian fixup trampoline
711 * This starts with a "tdi 0,0,0x48" instruction which is
712 * essentially a "trap never", and thus akin to a nop.
714 * The opcode for this instruction read with the wrong endian
715 * however results in a b . + 8
717 * So essentially we use that trick to execute the following
718 * trampoline in "reverse endian" if we are running with the
719 * MSR_LE bit set the "wrong" way for whatever endianness the
720 * kernel is built for.
723 #ifdef CONFIG_PPC_BOOK3E
727 * This version may be used in HV or non-HV context.
728 * MSR[EE] must be disabled.
730 #define FIXUP_ENDIAN \
731 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
732 b 191f; /* Skip trampoline if endian is good */ \
733 .long 0xa600607d; /* mfmsr r11 */ \
734 .long 0x01006b69; /* xori r11,r11,1 */ \
735 .long 0x00004039; /* li r10,0 */ \
736 .long 0x6401417d; /* mtmsrd r10,1 */ \
737 .long 0x05009f42; /* bcl 20,31,$+4 */ \
738 .long 0xa602487d; /* mflr r10 */ \
739 .long 0x14004a39; /* addi r10,r10,20 */ \
740 .long 0xa6035a7d; /* mtsrr0 r10 */ \
741 .long 0xa6037b7d; /* mtsrr1 r11 */ \
742 .long 0x2400004c; /* rfid */ \
746 * This version that may only be used with MSR[HV]=1
747 * - Does not clear MSR[RI], so more robust.
748 * - Slightly smaller and faster.
750 #define FIXUP_ENDIAN_HV \
751 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
752 b 191f; /* Skip trampoline if endian is good */ \
753 .long 0xa600607d; /* mfmsr r11 */ \
754 .long 0x01006b69; /* xori r11,r11,1 */ \
755 .long 0x05009f42; /* bcl 20,31,$+4 */ \
756 .long 0xa602487d; /* mflr r10 */ \
757 .long 0x14004a39; /* addi r10,r10,20 */ \
758 .long 0xa64b5a7d; /* mthsrr0 r10 */ \
759 .long 0xa64b7b7d; /* mthsrr1 r11 */ \
760 .long 0x2402004c; /* hrfid */ \
763 #endif /* !CONFIG_PPC_BOOK3E */
765 #endif /* __ASSEMBLY__ */
767 #define SOFT_MASK_TABLE(_start, _end) \
768 stringify_in_c(.section __soft_mask_table,"a";)\
769 stringify_in_c(.balign 8;) \
770 stringify_in_c(.llong (_start);) \
771 stringify_in_c(.llong (_end);) \
772 stringify_in_c(.previous)
774 #define RESTART_TABLE(_start, _end, _target) \
775 stringify_in_c(.section __restart_table,"a";)\
776 stringify_in_c(.balign 8;) \
777 stringify_in_c(.llong (_start);) \
778 stringify_in_c(.llong (_end);) \
779 stringify_in_c(.llong (_target);) \
780 stringify_in_c(.previous)
782 #ifdef CONFIG_PPC_FSL_BOOK3E
783 #define BTB_FLUSH(reg) \
784 lis reg,BUCSR_INIT@h; \
785 ori reg,reg,BUCSR_INIT@l; \
786 mtspr SPRN_BUCSR,reg; \
789 #define BTB_FLUSH(reg)
790 #endif /* CONFIG_PPC_FSL_BOOK3E */
792 #endif /* _ASM_POWERPC_PPC_ASM_H */