2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
4 #ifndef _ASM_POWERPC_PPC_ASM_H
5 #define _ASM_POWERPC_PPC_ASM_H
7 #include <linux/stringify.h>
8 #include <asm/asm-compat.h>
9 #include <asm/processor.h>
10 #include <asm/ppc-opcode.h>
11 #include <asm/firmware.h>
12 #include <asm/feature-fixups.h>
13 #include <asm/extable.h>
17 #define SZL (BITS_PER_LONG/8)
20 * This expands to a sequence of operations with reg incrementing from
21 * start to end inclusive, of this form:
23 * op reg, (offset + (width * reg))(base)
25 * Note that offset is not the offset of the first operation unless start
26 * is zero (or width is zero).
28 .macro OP_REGS op, width, start, end, base, offset
30 .rept (\end - \start + 1)
31 \op .Lreg, \offset + \width * .Lreg(\base)
37 * This expands to a sequence of register clears for regs start to end
38 * inclusive, of the form:
42 .macro ZEROIZE_REGS start, end
44 .rept (\end - \start + 1)
51 * Macros for storing registers into and loading registers from
55 #define SAVE_GPRS(start, end, base) OP_REGS std, 8, start, end, base, GPR0
56 #define REST_GPRS(start, end, base) OP_REGS ld, 8, start, end, base, GPR0
57 #define SAVE_NVGPRS(base) SAVE_GPRS(14, 31, base)
58 #define REST_NVGPRS(base) REST_GPRS(14, 31, base)
60 #define SAVE_GPRS(start, end, base) OP_REGS stw, 4, start, end, base, GPR0
61 #define REST_GPRS(start, end, base) OP_REGS lwz, 4, start, end, base, GPR0
62 #define SAVE_NVGPRS(base) SAVE_GPRS(13, 31, base)
63 #define REST_NVGPRS(base) REST_GPRS(13, 31, base)
66 #define ZEROIZE_GPRS(start, end) ZEROIZE_REGS start, end
68 #define ZEROIZE_NVGPRS() ZEROIZE_GPRS(14, 31)
70 #define ZEROIZE_NVGPRS() ZEROIZE_GPRS(13, 31)
72 #define ZEROIZE_GPR(n) ZEROIZE_GPRS(n, n)
74 #define SAVE_GPR(n, base) SAVE_GPRS(n, n, base)
75 #define REST_GPR(n, base) REST_GPRS(n, n, base)
77 #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base)
78 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
79 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
80 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
81 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
82 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
83 #define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base)
84 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
85 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
86 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
87 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
88 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
90 #define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b
91 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
92 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
93 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
94 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
95 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
96 #define REST_VR(n,b,base) li b,16*(n); lvx n,base,b
97 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
98 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
99 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
100 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
101 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
103 #ifdef __BIG_ENDIAN__
104 #define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base)
105 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base)
107 #define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \
111 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \
114 /* Save the lower 32 VSRs in the thread VSR region */
115 #define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b)
116 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
117 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
118 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
119 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
120 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
121 #define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b)
122 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
123 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
124 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
125 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
126 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
129 * b = base register for addressing, o = base offset from register of 1st EVR
130 * n = first EVR, s = scratch
132 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b)
133 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
134 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
135 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
136 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
137 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
138 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n
139 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
140 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
141 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
142 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
143 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
145 /* Macros to adjust thread priority for hardware multithreading */
146 #define HMT_VERY_LOW or 31,31,31 # very low priority
147 #define HMT_LOW or 1,1,1
148 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
149 #define HMT_MEDIUM or 2,2,2
150 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
151 #define HMT_HIGH or 3,3,3
152 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only
159 #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
160 #define VCPU_GPR(n) __VCPU_GPR(__REG_##n)
165 * We use __powerpc64__ here because we want the compat VDSO to use the 32-bit
166 * version below in the else case of the ifdef.
170 #define STACKFRAMESIZE 256
171 #define __STK_REG(i) (112 + ((i)-14)*8)
172 #define STK_REG(i) __STK_REG(__REG_##i)
174 #ifdef CONFIG_PPC64_ELF_ABI_V2
176 #define __STK_PARAM(i) (32 + ((i)-3)*8)
179 #define __STK_PARAM(i) (48 + ((i)-3)*8)
181 #define STK_PARAM(i) __STK_PARAM(__REG_##i)
183 #ifdef CONFIG_PPC64_ELF_ABI_V2
185 #define _GLOBAL(name) \
187 .type name,@function; \
191 #define _GLOBAL_TOC(name) \
193 .type name,@function; \
196 0: addis r2,r12,(.TOC.-0b)@ha; \
197 addi r2,r2,(.TOC.-0b)@l; \
198 .localentry name,.-name
204 #define XGLUE(a,b) a##b
205 #define GLUE(a,b) XGLUE(a,b)
207 #define _GLOBAL(name) \
210 .globl GLUE(.,name); \
211 .pushsection ".opd","aw"; \
213 .quad GLUE(.,name); \
214 .quad .TOC.@tocbase; \
217 .type GLUE(.,name),@function; \
220 #define _GLOBAL_TOC(name) _GLOBAL(name)
222 #define DOTSYM(a) GLUE(.,a)
232 #define _GLOBAL_TOC(name) _GLOBAL(name)
239 * __kprobes (the C annotation) puts the symbol into the .kprobes.text
240 * section, which gets emitted at the end of regular text.
242 * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to
243 * a blacklist. The former is for core kprobe functions/data, the
244 * latter is for those that incdentially must be excluded from probing
245 * and allows them to be linked at more optimal location within text.
247 #ifdef CONFIG_KPROBES
248 #define _ASM_NOKPROBE_SYMBOL(entry) \
249 .pushsection "_kprobe_blacklist","aw"; \
253 #define _ASM_NOKPROBE_SYMBOL(entry)
256 #define FUNC_START(name) _GLOBAL(name)
257 #define FUNC_END(name)
260 * LOAD_REG_IMMEDIATE(rn, expr)
261 * Loads the value of the constant expression 'expr' into register 'rn'
262 * using immediate instructions only. Use this when it's important not
263 * to reference other data (i.e. on ppc64 when the TOC pointer is not
264 * valid) and when 'expr' is a constant or absolute address.
266 * LOAD_REG_ADDR(rn, name)
267 * Loads the address of label 'name' into register 'rn'. Use this when
268 * you don't particularly need immediate instructions only, but you need
269 * the whole address in one register (e.g. it's a structure address and
270 * you want to access various offsets within it). On ppc32 this is
271 * identical to LOAD_REG_IMMEDIATE.
273 * LOAD_REG_ADDR_PIC(rn, name)
274 * Loads the address of label 'name' into register 'run'. Use this when
275 * the kernel doesn't run at the linked or relocated address. Please
276 * note that this macro will clobber the lr register.
278 * LOAD_REG_ADDRBASE(rn, name)
280 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
281 * register 'rn'. ADDROFF(name) returns the remainder of the address as
282 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
283 * in size, so is suitable for use directly as an offset in load and store
284 * instructions. Use this when loading/storing a single word or less as:
285 * LOAD_REG_ADDRBASE(rX, name)
286 * ld rY,ADDROFF(name)(rX)
289 /* Be careful, this will clobber the lr register. */
290 #define LOAD_REG_ADDR_PIC(reg, name) \
293 addis reg,reg,(name - 0b)@ha; \
294 addi reg,reg,(name - 0b)@l;
296 #if defined(__powerpc64__) && defined(HAVE_AS_ATHIGH)
297 #define __AS_ATHIGH high
299 #define __AS_ATHIGH h
302 .macro __LOAD_REG_IMMEDIATE_32 r, x
303 .if (\x) >= 0x8000 || (\x) < -0x8000
304 lis \r, (\x)@__AS_ATHIGH
305 .if (\x) & 0xffff != 0
313 .macro __LOAD_REG_IMMEDIATE r, x
314 .if (\x) >= 0x80000000 || (\x) < -0x80000000
315 __LOAD_REG_IMMEDIATE_32 \r, (\x) >> 32
317 .if (\x) & 0xffff0000 != 0
318 oris \r, \r, (\x)@__AS_ATHIGH
320 .if (\x) & 0xffff != 0
324 __LOAD_REG_IMMEDIATE_32 \r, \x
330 #define __LOAD_PACA_TOC(reg) \
333 #define LOAD_PACA_TOC() \
336 #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr
338 #define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \
339 lis tmp, (expr)@highest; \
340 lis reg, (expr)@__AS_ATHIGH; \
341 ori tmp, tmp, (expr)@higher; \
342 ori reg, reg, (expr)@l; \
343 rldimi reg, tmp, 32, 0
345 #define LOAD_REG_ADDR(reg,name) \
346 addis reg,r2,name@toc@ha; \
347 addi reg,reg,name@toc@l
349 #ifdef CONFIG_PPC_BOOK3E_64
351 * This is used in register-constrained interrupt handlers. Not to be used
352 * by BOOK3S. ld complains with "got/toc optimization is not supported" if r2
353 * is not used for the TOC offset, so use @got(tocreg). If the interrupt
354 * handlers saved r2 instead, LOAD_REG_ADDR could be used.
356 #define LOAD_REG_ADDR_ALTTOC(reg,tocreg,name) \
357 ld reg,name@got(tocreg)
360 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
361 #define ADDROFF(name) 0
363 /* offsets for stack frame layout */
368 #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr
370 #define LOAD_REG_IMMEDIATE_SYM(reg,expr) \
372 addi reg,reg,(expr)@l;
374 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE_SYM(reg, name)
376 #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha
377 #define ADDROFF(name) name@l
379 /* offsets for stack frame layout */
384 /* various errata or part fixups */
385 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_E500)
387 90: mfspr dest, SPRN_TBRL; \
388 BEGIN_FTR_SECTION_NESTED(96); \
391 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
393 #define MFTB(dest) MFTBL(dest)
396 #ifdef CONFIG_PPC_8xx
397 #define MFTBL(dest) mftb dest
398 #define MFTBU(dest) mftbu dest
400 #define MFTBL(dest) mfspr dest, SPRN_TBRL
401 #define MFTBU(dest) mfspr dest, SPRN_TBRU
407 #define TLBSYNC tlbsync; sync
411 #define MTOCRF(FXM, RS) \
412 BEGIN_FTR_SECTION_NESTED(848); \
414 FTR_SECTION_ELSE_NESTED(848); \
416 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
420 * This instruction is not implemented on the PPC 603 or 601; however, on
421 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
422 * All of these instructions exist in the 8xx, they have magical powers,
423 * and they must be used.
426 #if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx)
430 lis r4,KERNELBASE@h; \
440 #ifdef CONFIG_IBM440EP_ERR42
441 #define PPC440EP_ERR42 isync
443 #define PPC440EP_ERR42
446 /* The following stops all load and store data streams associated with stream
447 * ID (ie. streams created explicitly). The embedded and server mnemonics for
448 * dcbt are different so this must only be used for server.
450 #define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch) \
451 lis scratch,0x60000000@h; \
452 dcbt 0,scratch,0b01010
455 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
456 * keep the address intact to be compatible with code shared with
459 * On the other hand, I find it useful to have them behave as expected
460 * by their name (ie always do the addition) on 64-bit BookE
462 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
467 * We use addis to ensure compatibility with the "classic" ppc versions of
468 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
469 * converting the address in r0, and so this version has to do that too
470 * (i.e. set register rd to 0 when rs == 0).
472 #define tophys(rd,rs) \
475 #define tovirt(rd,rs) \
478 #elif defined(CONFIG_PPC64)
479 #define toreal(rd) /* we can access c000... in real mode */
482 #define tophys(rd,rs) \
485 #define tovirt(rd,rs) \
487 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
490 #define toreal(rd) tophys(rd,rd)
491 #define fromreal(rd) tovirt(rd,rd)
493 #define tophys(rd, rs) addis rd, rs, -PAGE_OFFSET@h
494 #define tovirt(rd, rs) addis rd, rs, PAGE_OFFSET@h
497 #ifdef CONFIG_PPC_BOOK3S_64
498 #define MTMSRD(r) mtmsrd r
499 #define MTMSR_EERI(reg) mtmsrd reg,1
501 #define MTMSRD(r) mtmsr r
502 #define MTMSR_EERI(reg) mtmsr reg
505 #endif /* __KERNEL__ */
507 /* The boring bits... */
509 /* Condition Register Bit Fields */
522 * General Purpose Registers (GPRs)
524 * The lower case r0-r31 should be used in preference to the upper
525 * case R0-R31 as they provide more error checking in the assembler.
526 * Use R0-31 only when really nessesary.
563 /* Floating Point Registers (FPRs) */
598 /* AltiVec Registers (VPRs) */
633 /* VSX Registers (VSRs) */
700 /* SPE Registers (EVPRs) */
735 #define RFSCV .long 0x4c0000a4
738 * Create an endian fixup trampoline
740 * This starts with a "tdi 0,0,0x48" instruction which is
741 * essentially a "trap never", and thus akin to a nop.
743 * The opcode for this instruction read with the wrong endian
744 * however results in a b . + 8
746 * So essentially we use that trick to execute the following
747 * trampoline in "reverse endian" if we are running with the
748 * MSR_LE bit set the "wrong" way for whatever endianness the
749 * kernel is built for.
752 #ifdef CONFIG_PPC_BOOK3E_64
756 * This version may be used in HV or non-HV context.
757 * MSR[EE] must be disabled.
759 #define FIXUP_ENDIAN \
760 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
761 b 191f; /* Skip trampoline if endian is good */ \
762 .long 0xa600607d; /* mfmsr r11 */ \
763 .long 0x01006b69; /* xori r11,r11,1 */ \
764 .long 0x00004039; /* li r10,0 */ \
765 .long 0x6401417d; /* mtmsrd r10,1 */ \
766 .long 0x05009f42; /* bcl 20,31,$+4 */ \
767 .long 0xa602487d; /* mflr r10 */ \
768 .long 0x14004a39; /* addi r10,r10,20 */ \
769 .long 0xa6035a7d; /* mtsrr0 r10 */ \
770 .long 0xa6037b7d; /* mtsrr1 r11 */ \
771 .long 0x2400004c; /* rfid */ \
775 * This version that may only be used with MSR[HV]=1
776 * - Does not clear MSR[RI], so more robust.
777 * - Slightly smaller and faster.
779 #define FIXUP_ENDIAN_HV \
780 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
781 b 191f; /* Skip trampoline if endian is good */ \
782 .long 0xa600607d; /* mfmsr r11 */ \
783 .long 0x01006b69; /* xori r11,r11,1 */ \
784 .long 0x05009f42; /* bcl 20,31,$+4 */ \
785 .long 0xa602487d; /* mflr r10 */ \
786 .long 0x14004a39; /* addi r10,r10,20 */ \
787 .long 0xa64b5a7d; /* mthsrr0 r10 */ \
788 .long 0xa64b7b7d; /* mthsrr1 r11 */ \
789 .long 0x2402004c; /* hrfid */ \
792 #endif /* !CONFIG_PPC_BOOK3E_64 */
794 #endif /* __ASSEMBLY__ */
796 #define SOFT_MASK_TABLE(_start, _end) \
797 stringify_in_c(.section __soft_mask_table,"a";)\
798 stringify_in_c(.balign 8;) \
799 stringify_in_c(.llong (_start);) \
800 stringify_in_c(.llong (_end);) \
801 stringify_in_c(.previous)
803 #define RESTART_TABLE(_start, _end, _target) \
804 stringify_in_c(.section __restart_table,"a";)\
805 stringify_in_c(.balign 8;) \
806 stringify_in_c(.llong (_start);) \
807 stringify_in_c(.llong (_end);) \
808 stringify_in_c(.llong (_target);) \
809 stringify_in_c(.previous)
811 #ifdef CONFIG_PPC_E500
812 #define BTB_FLUSH(reg) \
813 lis reg,BUCSR_INIT@h; \
814 ori reg,reg,BUCSR_INIT@l; \
815 mtspr SPRN_BUCSR,reg; \
818 #define BTB_FLUSH(reg)
819 #endif /* CONFIG_PPC_E500 */
821 #endif /* _ASM_POWERPC_PPC_ASM_H */