arch/powerpc/include/asm/opal-api.h

   1 /*
   2  * OPAL API definitions.
   3  *
   4  * Copyright 2011-2015 IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #ifndef __OPAL_API_H
  13 #define __OPAL_API_H
  14
  15 /****** OPAL APIs ******/
  16
  17 /* Return codes */
  18 #define OPAL_SUCCESS            0
  19 #define OPAL_PARAMETER          -1
  20 #define OPAL_BUSY               -2
  21 #define OPAL_PARTIAL            -3
  22 #define OPAL_CONSTRAINED        -4
  23 #define OPAL_CLOSED             -5
  24 #define OPAL_HARDWARE           -6
  25 #define OPAL_UNSUPPORTED        -7
  26 #define OPAL_PERMISSION         -8
  27 #define OPAL_NO_MEM             -9
  28 #define OPAL_RESOURCE           -10
  29 #define OPAL_INTERNAL_ERROR     -11
  30 #define OPAL_BUSY_EVENT         -12
  31 #define OPAL_HARDWARE_FROZEN    -13
  32 #define OPAL_WRONG_STATE        -14
  33 #define OPAL_ASYNC_COMPLETION   -15
  34 #define OPAL_EMPTY              -16
  35 #define OPAL_I2C_TIMEOUT        -17
  36 #define OPAL_I2C_INVALID_CMD    -18
  37 #define OPAL_I2C_LBUS_PARITY    -19
  38 #define OPAL_I2C_BKEND_OVERRUN  -20
  39 #define OPAL_I2C_BKEND_ACCESS   -21
  40 #define OPAL_I2C_ARBT_LOST      -22
  41 #define OPAL_I2C_NACK_RCVD      -23
  42 #define OPAL_I2C_STOP_ERR       -24
  43 #define OPAL_XIVE_PROVISIONING  -31
  44 #define OPAL_XIVE_FREE_ACTIVE   -32
  45 #define OPAL_TIMEOUT            -33
  46
  47 /* API Tokens (in r0) */
  48 #define OPAL_INVALID_CALL                      -1
  49 #define OPAL_TEST                               0
  50 #define OPAL_CONSOLE_WRITE                      1
  51 #define OPAL_CONSOLE_READ                       2
  52 #define OPAL_RTC_READ                           3
  53 #define OPAL_RTC_WRITE                          4
  54 #define OPAL_CEC_POWER_DOWN                     5
  55 #define OPAL_CEC_REBOOT                         6
  56 #define OPAL_READ_NVRAM                         7
  57 #define OPAL_WRITE_NVRAM                        8
  58 #define OPAL_HANDLE_INTERRUPT                   9
  59 #define OPAL_POLL_EVENTS                        10
  60 #define OPAL_PCI_SET_HUB_TCE_MEMORY             11
  61 #define OPAL_PCI_SET_PHB_TCE_MEMORY             12
  62 #define OPAL_PCI_CONFIG_READ_BYTE               13
  63 #define OPAL_PCI_CONFIG_READ_HALF_WORD          14
  64 #define OPAL_PCI_CONFIG_READ_WORD               15
  65 #define OPAL_PCI_CONFIG_WRITE_BYTE              16
  66 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD         17
  67 #define OPAL_PCI_CONFIG_WRITE_WORD              18
  68 #define OPAL_SET_XIVE                           19
  69 #define OPAL_GET_XIVE                           20
  70 #define OPAL_GET_COMPLETION_TOKEN_STATUS        21 /* obsolete */
  71 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER    22
  72 #define OPAL_PCI_EEH_FREEZE_STATUS              23
  73 #define OPAL_PCI_SHPC                           24
  74 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE         25
  75 #define OPAL_PCI_EEH_FREEZE_CLEAR               26
  76 #define OPAL_PCI_PHB_MMIO_ENABLE                27
  77 #define OPAL_PCI_SET_PHB_MEM_WINDOW             28
  78 #define OPAL_PCI_MAP_PE_MMIO_WINDOW             29
  79 #define OPAL_PCI_SET_PHB_TABLE_MEMORY           30
  80 #define OPAL_PCI_SET_PE                         31
  81 #define OPAL_PCI_SET_PELTV                      32
  82 #define OPAL_PCI_SET_MVE                        33
  83 #define OPAL_PCI_SET_MVE_ENABLE                 34
  84 #define OPAL_PCI_GET_XIVE_REISSUE               35
  85 #define OPAL_PCI_SET_XIVE_REISSUE               36
  86 #define OPAL_PCI_SET_XIVE_PE                    37
  87 #define OPAL_GET_XIVE_SOURCE                    38
  88 #define OPAL_GET_MSI_32                         39
  89 #define OPAL_GET_MSI_64                         40
  90 #define OPAL_START_CPU                          41
  91 #define OPAL_QUERY_CPU_STATUS                   42
  92 #define OPAL_WRITE_OPPANEL                      43 /* unimplemented */
  93 #define OPAL_PCI_MAP_PE_DMA_WINDOW              44
  94 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL         45
  95 #define OPAL_PCI_RESET                          49
  96 #define OPAL_PCI_GET_HUB_DIAG_DATA              50
  97 #define OPAL_PCI_GET_PHB_DIAG_DATA              51
  98 #define OPAL_PCI_FENCE_PHB                      52
  99 #define OPAL_PCI_REINIT                         53
 100 #define OPAL_PCI_MASK_PE_ERROR                  54
 101 #define OPAL_SET_SLOT_LED_STATUS                55
 102 #define OPAL_GET_EPOW_STATUS                    56
 103 #define OPAL_SET_SYSTEM_ATTENTION_LED           57
 104 #define OPAL_RESERVED1                          58
 105 #define OPAL_RESERVED2                          59
 106 #define OPAL_PCI_NEXT_ERROR                     60
 107 #define OPAL_PCI_EEH_FREEZE_STATUS2             61
 108 #define OPAL_PCI_POLL                           62
 109 #define OPAL_PCI_MSI_EOI                        63
 110 #define OPAL_PCI_GET_PHB_DIAG_DATA2             64
 111 #define OPAL_XSCOM_READ                         65
 112 #define OPAL_XSCOM_WRITE                        66
 113 #define OPAL_LPC_READ                           67
 114 #define OPAL_LPC_WRITE                          68
 115 #define OPAL_RETURN_CPU                         69
 116 #define OPAL_REINIT_CPUS                        70
 117 #define OPAL_ELOG_READ                          71
 118 #define OPAL_ELOG_WRITE                         72
 119 #define OPAL_ELOG_ACK                           73
 120 #define OPAL_ELOG_RESEND                        74
 121 #define OPAL_ELOG_SIZE                          75
 122 #define OPAL_FLASH_VALIDATE                     76
 123 #define OPAL_FLASH_MANAGE                       77
 124 #define OPAL_FLASH_UPDATE                       78
 125 #define OPAL_RESYNC_TIMEBASE                    79
 126 #define OPAL_CHECK_TOKEN                        80
 127 #define OPAL_DUMP_INIT                          81
 128 #define OPAL_DUMP_INFO                          82
 129 #define OPAL_DUMP_READ                          83
 130 #define OPAL_DUMP_ACK                           84
 131 #define OPAL_GET_MSG                            85
 132 #define OPAL_CHECK_ASYNC_COMPLETION             86
 133 #define OPAL_SYNC_HOST_REBOOT                   87
 134 #define OPAL_SENSOR_READ                        88
 135 #define OPAL_GET_PARAM                          89
 136 #define OPAL_SET_PARAM                          90
 137 #define OPAL_DUMP_RESEND                        91
 138 #define OPAL_ELOG_SEND                          92      /* Deprecated */
 139 #define OPAL_PCI_SET_PHB_CAPI_MODE              93
 140 #define OPAL_DUMP_INFO2                         94
 141 #define OPAL_WRITE_OPPANEL_ASYNC                95
 142 #define OPAL_PCI_ERR_INJECT                     96
 143 #define OPAL_PCI_EEH_FREEZE_SET                 97
 144 #define OPAL_HANDLE_HMI                         98
 145 #define OPAL_CONFIG_CPU_IDLE_STATE              99
 146 #define OPAL_SLW_SET_REG                        100
 147 #define OPAL_REGISTER_DUMP_REGION               101
 148 #define OPAL_UNREGISTER_DUMP_REGION             102
 149 #define OPAL_WRITE_TPO                          103
 150 #define OPAL_READ_TPO                           104
 151 #define OPAL_GET_DPO_STATUS                     105
 152 #define OPAL_OLD_I2C_REQUEST                    106     /* Deprecated */
 153 #define OPAL_IPMI_SEND                          107
 154 #define OPAL_IPMI_RECV                          108
 155 #define OPAL_I2C_REQUEST                        109
 156 #define OPAL_FLASH_READ                         110
 157 #define OPAL_FLASH_WRITE                        111
 158 #define OPAL_FLASH_ERASE                        112
 159 #define OPAL_PRD_MSG                            113
 160 #define OPAL_LEDS_GET_INDICATOR                 114
 161 #define OPAL_LEDS_SET_INDICATOR                 115
 162 #define OPAL_CEC_REBOOT2                        116
 163 #define OPAL_CONSOLE_FLUSH                      117
 164 #define OPAL_GET_DEVICE_TREE                    118
 165 #define OPAL_PCI_GET_PRESENCE_STATE             119
 166 #define OPAL_PCI_GET_POWER_STATE                120
 167 #define OPAL_PCI_SET_POWER_STATE                121
 168 #define OPAL_INT_GET_XIRR                       122
 169 #define OPAL_INT_SET_CPPR                       123
 170 #define OPAL_INT_EOI                            124
 171 #define OPAL_INT_SET_MFRR                       125
 172 #define OPAL_PCI_TCE_KILL                       126
 173 #define OPAL_NMMU_SET_PTCR                      127
 174 #define OPAL_XIVE_RESET                         128
 175 #define OPAL_XIVE_GET_IRQ_INFO                  129
 176 #define OPAL_XIVE_GET_IRQ_CONFIG                130
 177 #define OPAL_XIVE_SET_IRQ_CONFIG                131
 178 #define OPAL_XIVE_GET_QUEUE_INFO                132
 179 #define OPAL_XIVE_SET_QUEUE_INFO                133
 180 #define OPAL_XIVE_DONATE_PAGE                   134
 181 #define OPAL_XIVE_ALLOCATE_VP_BLOCK             135
 182 #define OPAL_XIVE_FREE_VP_BLOCK                 136
 183 #define OPAL_XIVE_GET_VP_INFO                   137
 184 #define OPAL_XIVE_SET_VP_INFO                   138
 185 #define OPAL_XIVE_ALLOCATE_IRQ                  139
 186 #define OPAL_XIVE_FREE_IRQ                      140
 187 #define OPAL_XIVE_SYNC                          141
 188 #define OPAL_XIVE_DUMP                          142
 189 #define OPAL_XIVE_RESERVED3                     143
 190 #define OPAL_XIVE_RESERVED4                     144
 191 #define OPAL_SIGNAL_SYSTEM_RESET                145
 192 #define OPAL_NPU_INIT_CONTEXT                   146
 193 #define OPAL_NPU_DESTROY_CONTEXT                147
 194 #define OPAL_NPU_MAP_LPAR                       148
 195 #define OPAL_IMC_COUNTERS_INIT                  149
 196 #define OPAL_IMC_COUNTERS_START                 150
 197 #define OPAL_IMC_COUNTERS_STOP                  151
 198 #define OPAL_GET_POWERCAP                       152
 199 #define OPAL_SET_POWERCAP                       153
 200 #define OPAL_GET_POWER_SHIFT_RATIO              154
 201 #define OPAL_SET_POWER_SHIFT_RATIO              155
 202 #define OPAL_SENSOR_GROUP_CLEAR                 156
 203 #define OPAL_PCI_SET_P2P                        157
 204 #define OPAL_QUIESCE                            158
 205 #define OPAL_NPU_SPA_SETUP                      159
 206 #define OPAL_NPU_SPA_CLEAR_CACHE                160
 207 #define OPAL_NPU_TL_SET                         161
 208 #define OPAL_SENSOR_READ_U64                    162
 209 #define OPAL_SENSOR_GROUP_ENABLE                163
 210 #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR            164
 211 #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR            165
 212 #define OPAL_NX_COPROC_INIT                     167
 213 #define OPAL_LAST                               167
 214
 215 #define QUIESCE_HOLD                    1 /* Spin all calls at entry */
 216 #define QUIESCE_REJECT                  2 /* Fail all calls with OPAL_BUSY */
 217 #define QUIESCE_LOCK_BREAK              3 /* Set to ignore locks. */
 218 #define QUIESCE_RESUME                  4 /* Un-quiesce */
 219 #define QUIESCE_RESUME_FAST_REBOOT      5 /* Un-quiesce, fast reboot */
 220
 221 /* Device tree flags */
 222
 223 /*
 224  * Flags set in power-mgmt nodes in device tree describing
 225  * idle states that are supported in the platform.
 226  */
 227
 228 #define OPAL_PM_TIMEBASE_STOP           0x00000002
 229 #define OPAL_PM_LOSE_HYP_CONTEXT        0x00002000
 230 #define OPAL_PM_LOSE_FULL_CONTEXT       0x00004000
 231 #define OPAL_PM_NAP_ENABLED             0x00010000
 232 #define OPAL_PM_SLEEP_ENABLED           0x00020000
 233 #define OPAL_PM_WINKLE_ENABLED          0x00040000
 234 #define OPAL_PM_SLEEP_ENABLED_ER1       0x00080000 /* with workaround */
 235 #define OPAL_PM_STOP_INST_FAST          0x00100000
 236 #define OPAL_PM_STOP_INST_DEEP          0x00200000
 237
 238 /*
 239  * OPAL_CONFIG_CPU_IDLE_STATE parameters
 240  */
 241 #define OPAL_CONFIG_IDLE_FASTSLEEP      1
 242 #define OPAL_CONFIG_IDLE_UNDO           0
 243 #define OPAL_CONFIG_IDLE_APPLY          1
 244
 245 #ifndef __ASSEMBLY__
 246
 247 /* Other enums */
 248 enum OpalFreezeState {
 249         OPAL_EEH_STOPPED_NOT_FROZEN = 0,
 250         OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
 251         OPAL_EEH_STOPPED_DMA_FREEZE = 2,
 252         OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
 253         OPAL_EEH_STOPPED_RESET = 4,
 254         OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
 255         OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
 256 };
 257
 258 enum OpalEehFreezeActionToken {
 259         OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
 260         OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
 261         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
 262
 263         OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
 264         OPAL_EEH_ACTION_SET_FREEZE_DMA  = 2,
 265         OPAL_EEH_ACTION_SET_FREEZE_ALL  = 3
 266 };
 267
 268 enum OpalPciStatusToken {
 269         OPAL_EEH_NO_ERROR       = 0,
 270         OPAL_EEH_IOC_ERROR      = 1,
 271         OPAL_EEH_PHB_ERROR      = 2,
 272         OPAL_EEH_PE_ERROR       = 3,
 273         OPAL_EEH_PE_MMIO_ERROR  = 4,
 274         OPAL_EEH_PE_DMA_ERROR   = 5
 275 };
 276
 277 enum OpalPciErrorSeverity {
 278         OPAL_EEH_SEV_NO_ERROR   = 0,
 279         OPAL_EEH_SEV_IOC_DEAD   = 1,
 280         OPAL_EEH_SEV_PHB_DEAD   = 2,
 281         OPAL_EEH_SEV_PHB_FENCED = 3,
 282         OPAL_EEH_SEV_PE_ER      = 4,
 283         OPAL_EEH_SEV_INF        = 5
 284 };
 285
 286 enum OpalErrinjectType {
 287         OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR        = 0,
 288         OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64      = 1,
 289 };
 290
 291 enum OpalErrinjectFunc {
 292         /* IOA bus specific errors */
 293         OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR    = 0,
 294         OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA    = 1,
 295         OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR     = 2,
 296         OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA     = 3,
 297         OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR    = 4,
 298         OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA    = 5,
 299         OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR    = 6,
 300         OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA    = 7,
 301         OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR     = 8,
 302         OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA     = 9,
 303         OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR    = 10,
 304         OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA    = 11,
 305         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR    = 12,
 306         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA    = 13,
 307         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER  = 14,
 308         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET  = 15,
 309         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR    = 16,
 310         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA    = 17,
 311         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER  = 18,
 312         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET  = 19,
 313 };
 314
 315 enum OpalMmioWindowType {
 316         OPAL_M32_WINDOW_TYPE = 1,
 317         OPAL_M64_WINDOW_TYPE = 2,
 318         OPAL_IO_WINDOW_TYPE  = 3
 319 };
 320
 321 enum OpalExceptionHandler {
 322         OPAL_MACHINE_CHECK_HANDLER          = 1,
 323         OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
 324         OPAL_SOFTPATCH_HANDLER              = 3
 325 };
 326
 327 enum OpalPendingState {
 328         OPAL_EVENT_OPAL_INTERNAL   = 0x1,
 329         OPAL_EVENT_NVRAM           = 0x2,
 330         OPAL_EVENT_RTC             = 0x4,
 331         OPAL_EVENT_CONSOLE_OUTPUT  = 0x8,
 332         OPAL_EVENT_CONSOLE_INPUT   = 0x10,
 333         OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
 334         OPAL_EVENT_ERROR_LOG       = 0x40,
 335         OPAL_EVENT_EPOW            = 0x80,
 336         OPAL_EVENT_LED_STATUS      = 0x100,
 337         OPAL_EVENT_PCI_ERROR       = 0x200,
 338         OPAL_EVENT_DUMP_AVAIL      = 0x400,
 339         OPAL_EVENT_MSG_PENDING     = 0x800,
 340 };
 341
 342 enum OpalThreadStatus {
 343         OPAL_THREAD_INACTIVE = 0x0,
 344         OPAL_THREAD_STARTED = 0x1,
 345         OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
 346 };
 347
 348 enum OpalPciBusCompare {
 349         OpalPciBusAny   = 0,    /* Any bus number match */
 350         OpalPciBus3Bits = 2,    /* Match top 3 bits of bus number */
 351         OpalPciBus4Bits = 3,    /* Match top 4 bits of bus number */
 352         OpalPciBus5Bits = 4,    /* Match top 5 bits of bus number */
 353         OpalPciBus6Bits = 5,    /* Match top 6 bits of bus number */
 354         OpalPciBus7Bits = 6,    /* Match top 7 bits of bus number */
 355         OpalPciBusAll   = 7,    /* Match bus number exactly */
 356 };
 357
 358 enum OpalDeviceCompare {
 359         OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
 360         OPAL_COMPARE_RID_DEVICE_NUMBER = 1
 361 };
 362
 363 enum OpalFuncCompare {
 364         OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
 365         OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
 366 };
 367
 368 enum OpalPeAction {
 369         OPAL_UNMAP_PE = 0,
 370         OPAL_MAP_PE = 1
 371 };
 372
 373 enum OpalPeltvAction {
 374         OPAL_REMOVE_PE_FROM_DOMAIN = 0,
 375         OPAL_ADD_PE_TO_DOMAIN = 1
 376 };
 377
 378 enum OpalMveEnableAction {
 379         OPAL_DISABLE_MVE = 0,
 380         OPAL_ENABLE_MVE = 1
 381 };
 382
 383 enum OpalM64Action {
 384         OPAL_DISABLE_M64 = 0,
 385         OPAL_ENABLE_M64_SPLIT = 1,
 386         OPAL_ENABLE_M64_NON_SPLIT = 2
 387 };
 388
 389 enum OpalPciResetScope {
 390         OPAL_RESET_PHB_COMPLETE         = 1,
 391         OPAL_RESET_PCI_LINK             = 2,
 392         OPAL_RESET_PHB_ERROR            = 3,
 393         OPAL_RESET_PCI_HOT              = 4,
 394         OPAL_RESET_PCI_FUNDAMENTAL      = 5,
 395         OPAL_RESET_PCI_IODA_TABLE       = 6
 396 };
 397
 398 enum OpalPciReinitScope {
 399         /*
 400          * Note: we chose values that do not overlap
 401          * OpalPciResetScope as OPAL v2 used the same
 402          * enum for both
 403          */
 404         OPAL_REINIT_PCI_DEV = 1000
 405 };
 406
 407 enum OpalPciResetState {
 408         OPAL_DEASSERT_RESET = 0,
 409         OPAL_ASSERT_RESET   = 1
 410 };
 411
 412 enum OpalPciSlotPresence {
 413         OPAL_PCI_SLOT_EMPTY     = 0,
 414         OPAL_PCI_SLOT_PRESENT   = 1
 415 };
 416
 417 enum OpalPciSlotPower {
 418         OPAL_PCI_SLOT_POWER_OFF = 0,
 419         OPAL_PCI_SLOT_POWER_ON  = 1,
 420         OPAL_PCI_SLOT_OFFLINE   = 2,
 421         OPAL_PCI_SLOT_ONLINE    = 3
 422 };
 423
 424 enum OpalSlotLedType {
 425         OPAL_SLOT_LED_TYPE_ID = 0,      /* IDENTIFY LED */
 426         OPAL_SLOT_LED_TYPE_FAULT = 1,   /* FAULT LED */
 427         OPAL_SLOT_LED_TYPE_ATTN = 2,    /* System Attention LED */
 428         OPAL_SLOT_LED_TYPE_MAX = 3
 429 };
 430
 431 enum OpalSlotLedState {
 432         OPAL_SLOT_LED_STATE_OFF = 0,    /* LED is OFF */
 433         OPAL_SLOT_LED_STATE_ON = 1      /* LED is ON */
 434 };
 435
 436 /*
 437  * Address cycle types for LPC accesses. These also correspond
 438  * to the content of the first cell of the "reg" property for
 439  * device nodes on the LPC bus
 440  */
 441 enum OpalLPCAddressType {
 442         OPAL_LPC_MEM    = 0,
 443         OPAL_LPC_IO     = 1,
 444         OPAL_LPC_FW     = 2,
 445 };
 446
 447 enum opal_msg_type {
 448         OPAL_MSG_ASYNC_COMP     = 0,    /* params[0] = token, params[1] = rc,
 449                                          * additional params function-specific
 450                                          */
 451         OPAL_MSG_MEM_ERR        = 1,
 452         OPAL_MSG_EPOW           = 2,
 453         OPAL_MSG_SHUTDOWN       = 3,    /* params[0] = 1 reboot, 0 shutdown */
 454         OPAL_MSG_HMI_EVT        = 4,
 455         OPAL_MSG_DPO            = 5,
 456         OPAL_MSG_PRD            = 6,
 457         OPAL_MSG_OCC            = 7,
 458         OPAL_MSG_TYPE_MAX,
 459 };
 460
 461 struct opal_msg {
 462         __be32 msg_type;
 463         __be32 reserved;
 464         __be64 params[8];
 465 };
 466
 467 /* System parameter permission */
 468 enum OpalSysparamPerm {
 469         OPAL_SYSPARAM_READ  = 0x1,
 470         OPAL_SYSPARAM_WRITE = 0x2,
 471         OPAL_SYSPARAM_RW    = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
 472 };
 473
 474 enum {
 475         OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
 476 };
 477
 478 struct opal_ipmi_msg {
 479         uint8_t version;
 480         uint8_t netfn;
 481         uint8_t cmd;
 482         uint8_t data[];
 483 };
 484
 485 /* FSP memory errors handling */
 486 enum OpalMemErr_Version {
 487         OpalMemErr_V1 = 1,
 488 };
 489
 490 enum OpalMemErrType {
 491         OPAL_MEM_ERR_TYPE_RESILIENCE    = 0,
 492         OPAL_MEM_ERR_TYPE_DYN_DALLOC,
 493 };
 494
 495 /* Memory Reilience error type */
 496 enum OpalMemErr_ResilErrType {
 497         OPAL_MEM_RESILIENCE_CE          = 0,
 498         OPAL_MEM_RESILIENCE_UE,
 499         OPAL_MEM_RESILIENCE_UE_SCRUB,
 500 };
 501
 502 /* Dynamic Memory Deallocation type */
 503 enum OpalMemErr_DynErrType {
 504         OPAL_MEM_DYNAMIC_DEALLOC        = 0,
 505 };
 506
 507 struct OpalMemoryErrorData {
 508         enum OpalMemErr_Version version:8;      /* 0x00 */
 509         enum OpalMemErrType     type:8;         /* 0x01 */
 510         __be16                  flags;          /* 0x02 */
 511         uint8_t                 reserved_1[4];  /* 0x04 */
 512
 513         union {
 514                 /* Memory Resilience corrected/uncorrected error info */
 515                 struct {
 516                         enum OpalMemErr_ResilErrType    resil_err_type:8;
 517                         uint8_t                         reserved_1[7];
 518                         __be64                          physical_address_start;
 519                         __be64                          physical_address_end;
 520                 } resilience;
 521                 /* Dynamic memory deallocation error info */
 522                 struct {
 523                         enum OpalMemErr_DynErrType      dyn_err_type:8;
 524                         uint8_t                         reserved_1[7];
 525                         __be64                          physical_address_start;
 526                         __be64                          physical_address_end;
 527                 } dyn_dealloc;
 528         } u;
 529 };
 530
 531 /* HMI interrupt event */
 532 enum OpalHMI_Version {
 533         OpalHMIEvt_V1 = 1,
 534         OpalHMIEvt_V2 = 2,
 535 };
 536
 537 enum OpalHMI_Severity {
 538         OpalHMI_SEV_NO_ERROR = 0,
 539         OpalHMI_SEV_WARNING = 1,
 540         OpalHMI_SEV_ERROR_SYNC = 2,
 541         OpalHMI_SEV_FATAL = 3,
 542 };
 543
 544 enum OpalHMI_Disposition {
 545         OpalHMI_DISPOSITION_RECOVERED = 0,
 546         OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
 547 };
 548
 549 enum OpalHMI_ErrType {
 550         OpalHMI_ERROR_MALFUNC_ALERT     = 0,
 551         OpalHMI_ERROR_PROC_RECOV_DONE,
 552         OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
 553         OpalHMI_ERROR_PROC_RECOV_MASKED,
 554         OpalHMI_ERROR_TFAC,
 555         OpalHMI_ERROR_TFMR_PARITY,
 556         OpalHMI_ERROR_HA_OVERFLOW_WARN,
 557         OpalHMI_ERROR_XSCOM_FAIL,
 558         OpalHMI_ERROR_XSCOM_DONE,
 559         OpalHMI_ERROR_SCOM_FIR,
 560         OpalHMI_ERROR_DEBUG_TRIG_FIR,
 561         OpalHMI_ERROR_HYP_RESOURCE,
 562         OpalHMI_ERROR_CAPP_RECOVERY,
 563 };
 564
 565 enum OpalHMI_XstopType {
 566         CHECKSTOP_TYPE_UNKNOWN  =       0,
 567         CHECKSTOP_TYPE_CORE     =       1,
 568         CHECKSTOP_TYPE_NX       =       2,
 569 };
 570
 571 enum OpalHMI_CoreXstopReason {
 572         CORE_CHECKSTOP_IFU_REGFILE              = 0x00000001,
 573         CORE_CHECKSTOP_IFU_LOGIC                = 0x00000002,
 574         CORE_CHECKSTOP_PC_DURING_RECOV          = 0x00000004,
 575         CORE_CHECKSTOP_ISU_REGFILE              = 0x00000008,
 576         CORE_CHECKSTOP_ISU_LOGIC                = 0x00000010,
 577         CORE_CHECKSTOP_FXU_LOGIC                = 0x00000020,
 578         CORE_CHECKSTOP_VSU_LOGIC                = 0x00000040,
 579         CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE   = 0x00000080,
 580         CORE_CHECKSTOP_LSU_REGFILE              = 0x00000100,
 581         CORE_CHECKSTOP_PC_FWD_PROGRESS          = 0x00000200,
 582         CORE_CHECKSTOP_LSU_LOGIC                = 0x00000400,
 583         CORE_CHECKSTOP_PC_LOGIC                 = 0x00000800,
 584         CORE_CHECKSTOP_PC_HYP_RESOURCE          = 0x00001000,
 585         CORE_CHECKSTOP_PC_HANG_RECOV_FAILED     = 0x00002000,
 586         CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED    = 0x00004000,
 587         CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ    = 0x00008000,
 588         CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ      = 0x00010000,
 589 };
 590
 591 enum OpalHMI_NestAccelXstopReason {
 592         NX_CHECKSTOP_SHM_INVAL_STATE_ERR        = 0x00000001,
 593         NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1      = 0x00000002,
 594         NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2      = 0x00000004,
 595         NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR    = 0x00000008,
 596         NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR    = 0x00000010,
 597         NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR    = 0x00000020,
 598         NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR    = 0x00000040,
 599         NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR    = 0x00000080,
 600         NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR    = 0x00000100,
 601         NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR    = 0x00000200,
 602         NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR    = 0x00000400,
 603         NX_CHECKSTOP_DMA_CRB_UE                 = 0x00000800,
 604         NX_CHECKSTOP_DMA_CRB_SUE                = 0x00001000,
 605         NX_CHECKSTOP_PBI_ISN_UE                 = 0x00002000,
 606 };
 607
 608 struct OpalHMIEvent {
 609         uint8_t         version;        /* 0x00 */
 610         uint8_t         severity;       /* 0x01 */
 611         uint8_t         type;           /* 0x02 */
 612         uint8_t         disposition;    /* 0x03 */
 613         uint8_t         reserved_1[4];  /* 0x04 */
 614
 615         __be64          hmer;
 616         /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
 617         __be64          tfmr;
 618
 619         /* version 2 and later */
 620         union {
 621                 /*
 622                  * checkstop info (Core/NX).
 623                  * Valid for OpalHMI_ERROR_MALFUNC_ALERT.
 624                  */
 625                 struct {
 626                         uint8_t xstop_type;     /* enum OpalHMI_XstopType */
 627                         uint8_t reserved_1[3];
 628                         __be32  xstop_reason;
 629                         union {
 630                                 __be32 pir;     /* for CHECKSTOP_TYPE_CORE */
 631                                 __be32 chip_id; /* for CHECKSTOP_TYPE_NX */
 632                         } u;
 633                 } xstop_error;
 634         } u;
 635 };
 636
 637 enum {
 638         OPAL_P7IOC_DIAG_TYPE_NONE       = 0,
 639         OPAL_P7IOC_DIAG_TYPE_RGC        = 1,
 640         OPAL_P7IOC_DIAG_TYPE_BI         = 2,
 641         OPAL_P7IOC_DIAG_TYPE_CI         = 3,
 642         OPAL_P7IOC_DIAG_TYPE_MISC       = 4,
 643         OPAL_P7IOC_DIAG_TYPE_I2C        = 5,
 644         OPAL_P7IOC_DIAG_TYPE_LAST       = 6
 645 };
 646
 647 struct OpalIoP7IOCErrorData {
 648         __be16 type;
 649
 650         /* GEM */
 651         __be64 gemXfir;
 652         __be64 gemRfir;
 653         __be64 gemRirqfir;
 654         __be64 gemMask;
 655         __be64 gemRwof;
 656
 657         /* LEM */
 658         __be64 lemFir;
 659         __be64 lemErrMask;
 660         __be64 lemAction0;
 661         __be64 lemAction1;
 662         __be64 lemWof;
 663
 664         union {
 665                 struct OpalIoP7IOCRgcErrorData {
 666                         __be64 rgcStatus;       /* 3E1C10 */
 667                         __be64 rgcLdcp;         /* 3E1C18 */
 668                 }rgc;
 669                 struct OpalIoP7IOCBiErrorData {
 670                         __be64 biLdcp0;         /* 3C0100, 3C0118 */
 671                         __be64 biLdcp1;         /* 3C0108, 3C0120 */
 672                         __be64 biLdcp2;         /* 3C0110, 3C0128 */
 673                         __be64 biFenceStatus;   /* 3C0130, 3C0130 */
 674
 675                         uint8_t biDownbound;    /* BI Downbound or Upbound */
 676                 }bi;
 677                 struct OpalIoP7IOCCiErrorData {
 678                         __be64 ciPortStatus;    /* 3Dn008 */
 679                         __be64 ciPortLdcp;      /* 3Dn010 */
 680
 681                         uint8_t ciPort;         /* Index of CI port: 0/1 */
 682                 }ci;
 683         };
 684 };
 685
 686 /**
 687  * This structure defines the overlay which will be used to store PHB error
 688  * data upon request.
 689  */
 690 enum {
 691         OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
 692 };
 693
 694 enum {
 695         OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
 696         OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2,
 697         OPAL_PHB_ERROR_DATA_TYPE_PHB4 = 3
 698 };
 699
 700 enum {
 701         OPAL_P7IOC_NUM_PEST_REGS = 128,
 702         OPAL_PHB3_NUM_PEST_REGS = 256,
 703         OPAL_PHB4_NUM_PEST_REGS = 512
 704 };
 705
 706 struct OpalIoPhbErrorCommon {
 707         __be32 version;
 708         __be32 ioType;
 709         __be32 len;
 710 };
 711
 712 struct OpalIoP7IOCPhbErrorData {
 713         struct OpalIoPhbErrorCommon common;
 714
 715         __be32 brdgCtl;
 716
 717         // P7IOC utl regs
 718         __be32 portStatusReg;
 719         __be32 rootCmplxStatus;
 720         __be32 busAgentStatus;
 721
 722         // P7IOC cfg regs
 723         __be32 deviceStatus;
 724         __be32 slotStatus;
 725         __be32 linkStatus;
 726         __be32 devCmdStatus;
 727         __be32 devSecStatus;
 728
 729         // cfg AER regs
 730         __be32 rootErrorStatus;
 731         __be32 uncorrErrorStatus;
 732         __be32 corrErrorStatus;
 733         __be32 tlpHdr1;
 734         __be32 tlpHdr2;
 735         __be32 tlpHdr3;
 736         __be32 tlpHdr4;
 737         __be32 sourceId;
 738
 739         __be32 rsv3;
 740
 741         // Record data about the call to allocate a buffer.
 742         __be64 errorClass;
 743         __be64 correlator;
 744
 745         //P7IOC MMIO Error Regs
 746         __be64 p7iocPlssr;                // n120
 747         __be64 p7iocCsr;                  // n110
 748         __be64 lemFir;                    // nC00
 749         __be64 lemErrorMask;              // nC18
 750         __be64 lemWOF;                    // nC40
 751         __be64 phbErrorStatus;            // nC80
 752         __be64 phbFirstErrorStatus;       // nC88
 753         __be64 phbErrorLog0;              // nCC0
 754         __be64 phbErrorLog1;              // nCC8
 755         __be64 mmioErrorStatus;           // nD00
 756         __be64 mmioFirstErrorStatus;      // nD08
 757         __be64 mmioErrorLog0;             // nD40
 758         __be64 mmioErrorLog1;             // nD48
 759         __be64 dma0ErrorStatus;           // nD80
 760         __be64 dma0FirstErrorStatus;      // nD88
 761         __be64 dma0ErrorLog0;             // nDC0
 762         __be64 dma0ErrorLog1;             // nDC8
 763         __be64 dma1ErrorStatus;           // nE00
 764         __be64 dma1FirstErrorStatus;      // nE08
 765         __be64 dma1ErrorLog0;             // nE40
 766         __be64 dma1ErrorLog1;             // nE48
 767         __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
 768         __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
 769 };
 770
 771 struct OpalIoPhb3ErrorData {
 772         struct OpalIoPhbErrorCommon common;
 773
 774         __be32 brdgCtl;
 775
 776         /* PHB3 UTL regs */
 777         __be32 portStatusReg;
 778         __be32 rootCmplxStatus;
 779         __be32 busAgentStatus;
 780
 781         /* PHB3 cfg regs */
 782         __be32 deviceStatus;
 783         __be32 slotStatus;
 784         __be32 linkStatus;
 785         __be32 devCmdStatus;
 786         __be32 devSecStatus;
 787
 788         /* cfg AER regs */
 789         __be32 rootErrorStatus;
 790         __be32 uncorrErrorStatus;
 791         __be32 corrErrorStatus;
 792         __be32 tlpHdr1;
 793         __be32 tlpHdr2;
 794         __be32 tlpHdr3;
 795         __be32 tlpHdr4;
 796         __be32 sourceId;
 797
 798         __be32 rsv3;
 799
 800         /* Record data about the call to allocate a buffer */
 801         __be64 errorClass;
 802         __be64 correlator;
 803
 804         /* PHB3 MMIO Error Regs */
 805         __be64 nFir;                    /* 000 */
 806         __be64 nFirMask;                /* 003 */
 807         __be64 nFirWOF;         /* 008 */
 808         __be64 phbPlssr;                /* 120 */
 809         __be64 phbCsr;          /* 110 */
 810         __be64 lemFir;          /* C00 */
 811         __be64 lemErrorMask;            /* C18 */
 812         __be64 lemWOF;          /* C40 */
 813         __be64 phbErrorStatus;  /* C80 */
 814         __be64 phbFirstErrorStatus;     /* C88 */
 815         __be64 phbErrorLog0;            /* CC0 */
 816         __be64 phbErrorLog1;            /* CC8 */
 817         __be64 mmioErrorStatus; /* D00 */
 818         __be64 mmioFirstErrorStatus;    /* D08 */
 819         __be64 mmioErrorLog0;           /* D40 */
 820         __be64 mmioErrorLog1;           /* D48 */
 821         __be64 dma0ErrorStatus; /* D80 */
 822         __be64 dma0FirstErrorStatus;    /* D88 */
 823         __be64 dma0ErrorLog0;           /* DC0 */
 824         __be64 dma0ErrorLog1;           /* DC8 */
 825         __be64 dma1ErrorStatus; /* E00 */
 826         __be64 dma1FirstErrorStatus;    /* E08 */
 827         __be64 dma1ErrorLog0;           /* E40 */
 828         __be64 dma1ErrorLog1;           /* E48 */
 829         __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
 830         __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
 831 };
 832
 833 struct OpalIoPhb4ErrorData {
 834         struct OpalIoPhbErrorCommon common;
 835
 836         __be32 brdgCtl;
 837
 838         /* PHB4 cfg regs */
 839         __be32 deviceStatus;
 840         __be32 slotStatus;
 841         __be32 linkStatus;
 842         __be32 devCmdStatus;
 843         __be32 devSecStatus;
 844
 845         /* cfg AER regs */
 846         __be32 rootErrorStatus;
 847         __be32 uncorrErrorStatus;
 848         __be32 corrErrorStatus;
 849         __be32 tlpHdr1;
 850         __be32 tlpHdr2;
 851         __be32 tlpHdr3;
 852         __be32 tlpHdr4;
 853         __be32 sourceId;
 854
 855         /* PHB4 ETU Error Regs */
 856         __be64 nFir;                            /* 000 */
 857         __be64 nFirMask;                        /* 003 */
 858         __be64 nFirWOF;                         /* 008 */
 859         __be64 phbPlssr;                        /* 120 */
 860         __be64 phbCsr;                          /* 110 */
 861         __be64 lemFir;                          /* C00 */
 862         __be64 lemErrorMask;                    /* C18 */
 863         __be64 lemWOF;                          /* C40 */
 864         __be64 phbErrorStatus;                  /* C80 */
 865         __be64 phbFirstErrorStatus;             /* C88 */
 866         __be64 phbErrorLog0;                    /* CC0 */
 867         __be64 phbErrorLog1;                    /* CC8 */
 868         __be64 phbTxeErrorStatus;               /* D00 */
 869         __be64 phbTxeFirstErrorStatus;          /* D08 */
 870         __be64 phbTxeErrorLog0;                 /* D40 */
 871         __be64 phbTxeErrorLog1;                 /* D48 */
 872         __be64 phbRxeArbErrorStatus;            /* D80 */
 873         __be64 phbRxeArbFirstErrorStatus;       /* D88 */
 874         __be64 phbRxeArbErrorLog0;              /* DC0 */
 875         __be64 phbRxeArbErrorLog1;              /* DC8 */
 876         __be64 phbRxeMrgErrorStatus;            /* E00 */
 877         __be64 phbRxeMrgFirstErrorStatus;       /* E08 */
 878         __be64 phbRxeMrgErrorLog0;              /* E40 */
 879         __be64 phbRxeMrgErrorLog1;              /* E48 */
 880         __be64 phbRxeTceErrorStatus;            /* E80 */
 881         __be64 phbRxeTceFirstErrorStatus;       /* E88 */
 882         __be64 phbRxeTceErrorLog0;              /* EC0 */
 883         __be64 phbRxeTceErrorLog1;              /* EC8 */
 884
 885         /* PHB4 REGB Error Regs */
 886         __be64 phbPblErrorStatus;               /* 1900 */
 887         __be64 phbPblFirstErrorStatus;          /* 1908 */
 888         __be64 phbPblErrorLog0;                 /* 1940 */
 889         __be64 phbPblErrorLog1;                 /* 1948 */
 890         __be64 phbPcieDlpErrorLog1;             /* 1AA0 */
 891         __be64 phbPcieDlpErrorLog2;             /* 1AA8 */
 892         __be64 phbPcieDlpErrorStatus;           /* 1AB0 */
 893         __be64 phbRegbErrorStatus;              /* 1C00 */
 894         __be64 phbRegbFirstErrorStatus;         /* 1C08 */
 895         __be64 phbRegbErrorLog0;                /* 1C40 */
 896         __be64 phbRegbErrorLog1;                /* 1C48 */
 897
 898         __be64 pestA[OPAL_PHB4_NUM_PEST_REGS];
 899         __be64 pestB[OPAL_PHB4_NUM_PEST_REGS];
 900 };
 901
 902 enum {
 903         OPAL_REINIT_CPUS_HILE_BE        = (1 << 0),
 904         OPAL_REINIT_CPUS_HILE_LE        = (1 << 1),
 905
 906         /* These two define the base MMU mode of the host on P9
 907          *
 908          * On P9 Nimbus DD2.0 and Cumlus (and later), KVM can still
 909          * create hash guests in "radix" mode with care (full core
 910          * switch only).
 911          */
 912         OPAL_REINIT_CPUS_MMU_HASH       = (1 << 2),
 913         OPAL_REINIT_CPUS_MMU_RADIX      = (1 << 3),
 914
 915         OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED = (1 << 4),
 916 };
 917
 918 typedef struct oppanel_line {
 919         __be64 line;
 920         __be64 line_len;
 921 } oppanel_line_t;
 922
 923 enum opal_prd_msg_type {
 924         OPAL_PRD_MSG_TYPE_INIT = 0,     /* HBRT --> OPAL */
 925         OPAL_PRD_MSG_TYPE_FINI,         /* HBRT/kernel --> OPAL */
 926         OPAL_PRD_MSG_TYPE_ATTN,         /* HBRT <-- OPAL */
 927         OPAL_PRD_MSG_TYPE_ATTN_ACK,     /* HBRT --> OPAL */
 928         OPAL_PRD_MSG_TYPE_OCC_ERROR,    /* HBRT <-- OPAL */
 929         OPAL_PRD_MSG_TYPE_OCC_RESET,    /* HBRT <-- OPAL */
 930 };
 931
 932 struct opal_prd_msg_header {
 933         uint8_t         type;
 934         uint8_t         pad[1];
 935         __be16          size;
 936 };
 937
 938 struct opal_prd_msg;
 939
 940 #define OCC_RESET                       0
 941 #define OCC_LOAD                        1
 942 #define OCC_THROTTLE                    2
 943 #define OCC_MAX_THROTTLE_STATUS         5
 944
 945 struct opal_occ_msg {
 946         __be64 type;
 947         __be64 chip;
 948         __be64 throttle_status;
 949 };
 950
 951 /*
 952  * SG entries
 953  *
 954  * WARNING: The current implementation requires each entry
 955  * to represent a block that is 4k aligned *and* each block
 956  * size except the last one in the list to be as well.
 957  */
 958 struct opal_sg_entry {
 959         __be64 data;
 960         __be64 length;
 961 };
 962
 963 /*
 964  * Candidate image SG list.
 965  *
 966  * length = VER | length
 967  */
 968 struct opal_sg_list {
 969         __be64 length;
 970         __be64 next;
 971         struct opal_sg_entry entry[];
 972 };
 973
 974 /*
 975  * Dump region ID range usable by the OS
 976  */
 977 #define OPAL_DUMP_REGION_HOST_START             0x80
 978 #define OPAL_DUMP_REGION_LOG_BUF                0x80
 979 #define OPAL_DUMP_REGION_HOST_END               0xFF
 980
 981 /* CAPI modes for PHB */
 982 enum {
 983         OPAL_PHB_CAPI_MODE_PCIE         = 0,
 984         OPAL_PHB_CAPI_MODE_CAPI         = 1,
 985         OPAL_PHB_CAPI_MODE_SNOOP_OFF    = 2,
 986         OPAL_PHB_CAPI_MODE_SNOOP_ON     = 3,
 987         OPAL_PHB_CAPI_MODE_DMA          = 4,
 988         OPAL_PHB_CAPI_MODE_DMA_TVT1     = 5,
 989 };
 990
 991 /* OPAL I2C request */
 992 struct opal_i2c_request {
 993         uint8_t type;
 994 #define OPAL_I2C_RAW_READ       0
 995 #define OPAL_I2C_RAW_WRITE      1
 996 #define OPAL_I2C_SM_READ        2
 997 #define OPAL_I2C_SM_WRITE       3
 998         uint8_t flags;
 999 #define OPAL_I2C_ADDR_10        0x01    /* Not supported yet */
1000         uint8_t subaddr_sz;             /* Max 4 */
1001         uint8_t reserved;
1002         __be16 addr;                    /* 7 or 10 bit address */
1003         __be16 reserved2;
1004         __be32 subaddr;         /* Sub-address if any */
1005         __be32 size;                    /* Data size */
1006         __be64 buffer_ra;               /* Buffer real address */
1007 };
1008
1009 /*
1010  * EPOW status sharing (OPAL and the host)
1011  *
1012  * The host will pass on OPAL, a buffer of length OPAL_SYSEPOW_MAX
1013  * with individual elements being 16 bits wide to fetch the system
1014  * wide EPOW status. Each element in the buffer will contain the
1015  * EPOW status in it's bit representation for a particular EPOW sub
1016  * class as defined here. So multiple detailed EPOW status bits
1017  * specific for any sub class can be represented in a single buffer
1018  * element as it's bit representation.
1019  */
1020
1021 /* System EPOW type */
1022 enum OpalSysEpow {
1023         OPAL_SYSEPOW_POWER      = 0,    /* Power EPOW */
1024         OPAL_SYSEPOW_TEMP       = 1,    /* Temperature EPOW */
1025         OPAL_SYSEPOW_COOLING    = 2,    /* Cooling EPOW */
1026         OPAL_SYSEPOW_MAX        = 3,    /* Max EPOW categories */
1027 };
1028
1029 /* Power EPOW */
1030 enum OpalSysPower {
1031         OPAL_SYSPOWER_UPS       = 0x0001, /* System on UPS power */
1032         OPAL_SYSPOWER_CHNG      = 0x0002, /* System power config change */
1033         OPAL_SYSPOWER_FAIL      = 0x0004, /* System impending power failure */
1034         OPAL_SYSPOWER_INCL      = 0x0008, /* System incomplete power */
1035 };
1036
1037 /* Temperature EPOW */
1038 enum OpalSysTemp {
1039         OPAL_SYSTEMP_AMB        = 0x0001, /* System over ambient temperature */
1040         OPAL_SYSTEMP_INT        = 0x0002, /* System over internal temperature */
1041         OPAL_SYSTEMP_HMD        = 0x0004, /* System over ambient humidity */
1042 };
1043
1044 /* Cooling EPOW */
1045 enum OpalSysCooling {
1046         OPAL_SYSCOOL_INSF       = 0x0001, /* System insufficient cooling */
1047 };
1048
1049 /* Argument to OPAL_CEC_REBOOT2() */
1050 enum {
1051         OPAL_REBOOT_NORMAL              = 0,
1052         OPAL_REBOOT_PLATFORM_ERROR      = 1,
1053 };
1054
1055 /* Argument to OPAL_PCI_TCE_KILL */
1056 enum {
1057         OPAL_PCI_TCE_KILL_PAGES,
1058         OPAL_PCI_TCE_KILL_PE,
1059         OPAL_PCI_TCE_KILL_ALL,
1060 };
1061
1062 /* The xive operation mode indicates the active "API" and
1063  * corresponds to the "mode" parameter of the opal_xive_reset()
1064  * call
1065  */
1066 enum {
1067         OPAL_XIVE_MODE_EMU      = 0,
1068         OPAL_XIVE_MODE_EXPL     = 1,
1069 };
1070
1071 /* Flags for OPAL_XIVE_GET_IRQ_INFO */
1072 enum {
1073         OPAL_XIVE_IRQ_TRIGGER_PAGE      = 0x00000001,
1074         OPAL_XIVE_IRQ_STORE_EOI         = 0x00000002,
1075         OPAL_XIVE_IRQ_LSI               = 0x00000004,
1076         OPAL_XIVE_IRQ_SHIFT_BUG         = 0x00000008,
1077         OPAL_XIVE_IRQ_MASK_VIA_FW       = 0x00000010,
1078         OPAL_XIVE_IRQ_EOI_VIA_FW        = 0x00000020,
1079 };
1080
1081 /* Flags for OPAL_XIVE_GET/SET_QUEUE_INFO */
1082 enum {
1083         OPAL_XIVE_EQ_ENABLED            = 0x00000001,
1084         OPAL_XIVE_EQ_ALWAYS_NOTIFY      = 0x00000002,
1085         OPAL_XIVE_EQ_ESCALATE           = 0x00000004,
1086 };
1087
1088 /* Flags for OPAL_XIVE_GET/SET_VP_INFO */
1089 enum {
1090         OPAL_XIVE_VP_ENABLED            = 0x00000001,
1091         OPAL_XIVE_VP_SINGLE_ESCALATION  = 0x00000002,
1092 };
1093
1094 /* "Any chip" replacement for chip ID for allocation functions */
1095 enum {
1096         OPAL_XIVE_ANY_CHIP              = 0xffffffff,
1097 };
1098
1099 /* Xive sync options */
1100 enum {
1101         /* This bits are cumulative, arg is a girq */
1102         XIVE_SYNC_EAS                   = 0x00000001, /* Sync irq source */
1103         XIVE_SYNC_QUEUE                 = 0x00000002, /* Sync irq target */
1104 };
1105
1106 /* Dump options */
1107 enum {
1108         XIVE_DUMP_TM_HYP        = 0,
1109         XIVE_DUMP_TM_POOL       = 1,
1110         XIVE_DUMP_TM_OS         = 2,
1111         XIVE_DUMP_TM_USER       = 3,
1112         XIVE_DUMP_VP            = 4,
1113         XIVE_DUMP_EMU_STATE     = 5,
1114 };
1115
1116 /* "type" argument options for OPAL_IMC_COUNTERS_* calls */
1117 enum {
1118         OPAL_IMC_COUNTERS_NEST = 1,
1119         OPAL_IMC_COUNTERS_CORE = 2,
1120 };
1121
1122
1123 /* PCI p2p descriptor */
1124 #define OPAL_PCI_P2P_ENABLE             0x1
1125 #define OPAL_PCI_P2P_LOAD               0x2
1126 #define OPAL_PCI_P2P_STORE              0x4
1127
1128 #endif /* __ASSEMBLY__ */
1129
1130 #endif /* __OPAL_API_H */