1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_MMU_8XX_H_
3 #define _ASM_POWERPC_MMU_8XX_H_
8 /* Control/status registers for the MPC8xx.
9 * A write operation to these registers causes serialized access.
10 * During software tablewalk, the registers used perform mask/shift-add
11 * operations when written/read. A TLB entry is created when the Mx_RPN
12 * is written, and the contents of several registers are used to
15 #define SPRN_MI_CTR 784 /* Instruction TLB control register */
16 #define MI_GPM 0x80000000 /* Set domain manager mode */
17 #define MI_PPM 0x40000000 /* Set subpage protection */
18 #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
19 #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
20 #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
21 #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
22 #define MI_RESETVAL 0x00000000 /* Value of register at reset */
24 /* These are the Ks and Kp from the PowerPC books. For proper operation,
27 #define SPRN_MI_AP 786
28 #define MI_Ks 0x80000000 /* Should not be set */
29 #define MI_Kp 0x40000000 /* Should always be set */
32 * All pages' PP exec bits are set to 000, which means Execute for Supervisor
33 * and no Execute for User.
34 * Then we use the APG to say whether accesses are according to Page rules,
35 * "all Supervisor" rules (Exec for all) and "all User" rules (Exec for noone)
36 * Therefore, we define 4 APG groups. msb is _PAGE_EXEC, lsb is _PAGE_USER
37 * 0 (00) => Not User, no exec => 11 (all accesses performed as user)
38 * 1 (01) => User but no exec => 11 (all accesses performed as user)
39 * 2 (10) => Not User, exec => 01 (rights according to page definition)
40 * 3 (11) => User, exec => 00 (all accesses performed as supervisor)
42 #define MI_APG_INIT 0xf4ffffff
44 /* The effective page number register. When read, contains the information
45 * about the last instruction TLB miss. When MI_RPN is written, bits in
46 * this register are used to create the TLB entry.
48 #define SPRN_MI_EPN 787
49 #define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
50 #define MI_EVALID 0x00000200 /* Entry is valid */
51 #define MI_ASIDMASK 0x0000000f /* ASID match value */
52 /* Reset value is undefined */
54 /* A "level 1" or "segment" or whatever you want to call it register.
55 * For the instruction TLB, it contains bits that get loaded into the
56 * TLB entry when the MI_RPN is written.
58 #define SPRN_MI_TWC 789
59 #define MI_APG 0x000001e0 /* Access protection group (0) */
60 #define MI_GUARDED 0x00000010 /* Guarded storage */
61 #define MI_PSMASK 0x0000000c /* Mask of page size bits */
62 #define MI_PS8MEG 0x0000000c /* 8M page size */
63 #define MI_PS512K 0x00000004 /* 512K page size */
64 #define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
65 #define MI_SVALID 0x00000001 /* Segment entry is valid */
66 /* Reset value is undefined */
68 /* Real page number. Defined by the pte. Writing this register
69 * causes a TLB entry to be created for the instruction TLB, using
70 * additional information from the MI_EPN, and MI_TWC registers.
72 #define SPRN_MI_RPN 790
73 #define MI_SPS16K 0x00000008 /* Small page size (0 = 4k, 1 = 16k) */
75 /* Define an RPN value for mapping kernel memory to large virtual
76 * pages for boot initialization. This has real page number of 0,
77 * large page size, shared page, cache enabled, and valid.
78 * Also mark all subpages valid and write access.
80 #define MI_BOOTINIT 0x000001fd
82 #define SPRN_MD_CTR 792 /* Data TLB control register */
83 #define MD_GPM 0x80000000 /* Set domain manager mode */
84 #define MD_PPM 0x40000000 /* Set subpage protection */
85 #define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
86 #define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
87 #define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
88 #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
89 #define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
90 #define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
91 #define MD_RESETVAL 0x04000000 /* Value of register at reset */
93 #define SPRN_M_CASID 793 /* Address space ID (context) to match */
94 #define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
97 /* These are the Ks and Kp from the PowerPC books. For proper operation,
100 #define SPRN_MD_AP 794
101 #define MD_Ks 0x80000000 /* Should not be set */
102 #define MD_Kp 0x40000000 /* Should always be set */
105 * All pages' PP data bits are set to either 000 or 011, which means
106 * respectively RW for Supervisor and no access for User, or RO for
107 * Supervisor and no access for user.
108 * Then we use the APG to say whether accesses are according to Page rules or
109 * "all Supervisor" rules (Access to all)
110 * Therefore, we define 2 APG groups. lsb is _PAGE_USER
111 * 0 => No user => 01 (all accesses performed according to page definition)
112 * 1 => User => 00 (all accesses performed as supervisor
113 * according to page definition)
115 #define MD_APG_INIT 0x4fffffff
117 /* The effective page number register. When read, contains the information
118 * about the last instruction TLB miss. When MD_RPN is written, bits in
119 * this register are used to create the TLB entry.
121 #define SPRN_MD_EPN 795
122 #define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
123 #define MD_EVALID 0x00000200 /* Entry is valid */
124 #define MD_ASIDMASK 0x0000000f /* ASID match value */
125 /* Reset value is undefined */
127 /* The pointer to the base address of the first level page table.
128 * During a software tablewalk, reading this register provides the address
129 * of the entry associated with MD_EPN.
131 #define SPRN_M_TWB 796
132 #define M_L1TB 0xfffff000 /* Level 1 table base address */
133 #define M_L1INDX 0x00000ffc /* Level 1 index, when read */
134 /* Reset value is undefined */
136 /* A "level 1" or "segment" or whatever you want to call it register.
137 * For the data TLB, it contains bits that get loaded into the TLB entry
138 * when the MD_RPN is written. It is also provides the hardware assist
139 * for finding the PTE address during software tablewalk.
141 #define SPRN_MD_TWC 797
142 #define MD_L2TB 0xfffff000 /* Level 2 table base address */
143 #define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
144 #define MD_APG 0x000001e0 /* Access protection group (0) */
145 #define MD_GUARDED 0x00000010 /* Guarded storage */
146 #define MD_PSMASK 0x0000000c /* Mask of page size bits */
147 #define MD_PS8MEG 0x0000000c /* 8M page size */
148 #define MD_PS512K 0x00000004 /* 512K page size */
149 #define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
150 #define MD_WT 0x00000002 /* Use writethrough page attribute */
151 #define MD_SVALID 0x00000001 /* Segment entry is valid */
152 /* Reset value is undefined */
155 /* Real page number. Defined by the pte. Writing this register
156 * causes a TLB entry to be created for the data TLB, using
157 * additional information from the MD_EPN, and MD_TWC registers.
159 #define SPRN_MD_RPN 798
160 #define MD_SPS16K 0x00000008 /* Small page size (0 = 4k, 1 = 16k) */
162 /* This is a temporary storage register that could be used to save
163 * a processor working register during a tablewalk.
165 #define SPRN_M_TW 799
171 unsigned long vdso_base;
172 #ifdef CONFIG_PPC_MM_SLICES
173 u16 user_psize; /* page size index */
174 u64 low_slices_psize; /* page size encodings */
175 unsigned char high_slices_psize[0];
176 unsigned long addr_limit;
180 #define PHYS_IMMR_BASE (mfspr(SPRN_IMMR) & 0xfff80000)
181 #define VIRT_IMMR_BASE (__fix_to_virt(FIX_IMMR_BASE))
183 /* Page size definitions, common between 32 and 64-bit
185 * shift : is the "PAGE_SHIFT" value for that page size
186 * penc : is the pte encoding mask
189 struct mmu_psize_def {
190 unsigned int shift; /* number of bits */
191 unsigned int enc; /* PTE encoding */
192 unsigned int ind; /* Corresponding indirect page size shift */
194 #define MMU_PAGE_SIZE_DIRECT 0x1 /* Supported as a direct size */
195 #define MMU_PAGE_SIZE_INDIRECT 0x2 /* Supported as an indirect size */
198 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
200 static inline int shift_to_mmu_psize(unsigned int shift)
204 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
205 if (mmu_psize_defs[psize].shift == shift)
210 static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
212 if (mmu_psize_defs[mmu_psize].shift)
213 return mmu_psize_defs[mmu_psize].shift;
217 #endif /* !__ASSEMBLY__ */
219 #if defined(CONFIG_PPC_4K_PAGES)
220 #define mmu_virtual_psize MMU_PAGE_4K
221 #elif defined(CONFIG_PPC_16K_PAGES)
222 #define mmu_virtual_psize MMU_PAGE_16K
224 #error "Unsupported PAGE_SIZE"
227 #define mmu_linear_psize MMU_PAGE_8M
229 #endif /* _ASM_POWERPC_MMU_8XX_H_ */