1 #ifndef _ASM_POWERPC_IO_H
2 #define _ASM_POWERPC_IO_H
5 #define ARCH_HAS_IOREMAP_WC
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
14 /* Check of existence of legacy devices */
15 extern int check_legacy_ioport(unsigned long base_port);
16 #define I8042_DATA_REG 0x60
17 #define FDC_BASE 0x3f0
19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
20 extern struct pci_dev *isa_bridge_pcidev;
22 * has legacy ISA devices ?
24 #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special)
27 #include <linux/device.h>
30 #include <linux/compiler.h>
32 #include <asm/byteorder.h>
33 #include <asm/synch.h>
34 #include <asm/delay.h>
37 #include <asm-generic/iomap.h>
43 #define SIO_CONFIG_RA 0x398
44 #define SIO_CONFIG_RD 0x399
48 /* 32 bits uses slightly different variables for the various IO
49 * bases. Most of this file only uses _IO_BASE though which we
50 * define properly based on the platform
54 #define _ISA_MEM_BASE 0
55 #define PCI_DRAM_OFFSET 0
56 #elif defined(CONFIG_PPC32)
57 #define _IO_BASE isa_io_base
58 #define _ISA_MEM_BASE isa_mem_base
59 #define PCI_DRAM_OFFSET pci_dram_offset
61 #define _IO_BASE pci_io_base
62 #define _ISA_MEM_BASE isa_mem_base
63 #define PCI_DRAM_OFFSET 0
66 extern unsigned long isa_io_base;
67 extern unsigned long pci_io_base;
68 extern unsigned long pci_dram_offset;
70 extern resource_size_t isa_mem_base;
72 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE
73 * is not set or addresses cannot be translated to MMIO. This is typically
74 * set when the platform supports "special" PIO accesses via a non memory
75 * mapped mechanism, and allows things like the early udbg UART code to
78 extern bool isa_io_special;
81 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
82 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
88 * Low level MMIO accessors
90 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
91 * specific and thus shouldn't be used in generic code. The accessors
94 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
95 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
96 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
98 * Those operate directly on a kernel virtual address. Note that the prototype
99 * for the out_* accessors has the arguments in opposite order from the usual
100 * linux PCI accessors. Unlike those, they take the address first and the value
103 * Note: I might drop the _ns suffix on the stream operations soon as it is
104 * simply normal for stream operations to not swap in the first place.
109 #define IO_SET_SYNC_FLAG() do { local_paca->io_sync = 1; } while(0)
111 #define IO_SET_SYNC_FLAG()
114 /* gcc 4.0 and older doesn't have 'Z' constraint */
115 #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0)
116 #define DEF_MMIO_IN_X(name, size, insn) \
117 static inline u##size name(const volatile u##size __iomem *addr) \
120 __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \
121 : "=r" (ret) : "r" (addr), "m" (*addr) : "memory"); \
125 #define DEF_MMIO_OUT_X(name, size, insn) \
126 static inline void name(volatile u##size __iomem *addr, u##size val) \
128 __asm__ __volatile__("sync;"#insn" %1,0,%2" \
129 : "=m" (*addr) : "r" (val), "r" (addr) : "memory"); \
130 IO_SET_SYNC_FLAG(); \
132 #else /* newer gcc */
133 #define DEF_MMIO_IN_X(name, size, insn) \
134 static inline u##size name(const volatile u##size __iomem *addr) \
137 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
138 : "=r" (ret) : "Z" (*addr) : "memory"); \
142 #define DEF_MMIO_OUT_X(name, size, insn) \
143 static inline void name(volatile u##size __iomem *addr, u##size val) \
145 __asm__ __volatile__("sync;"#insn" %1,%y0" \
146 : "=Z" (*addr) : "r" (val) : "memory"); \
147 IO_SET_SYNC_FLAG(); \
151 #define DEF_MMIO_IN_D(name, size, insn) \
152 static inline u##size name(const volatile u##size __iomem *addr) \
155 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
156 : "=r" (ret) : "m" (*addr) : "memory"); \
160 #define DEF_MMIO_OUT_D(name, size, insn) \
161 static inline void name(volatile u##size __iomem *addr, u##size val) \
163 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
164 : "=m" (*addr) : "r" (val) : "memory"); \
165 IO_SET_SYNC_FLAG(); \
168 DEF_MMIO_IN_D(in_8, 8, lbz);
169 DEF_MMIO_OUT_D(out_8, 8, stb);
171 #ifdef __BIG_ENDIAN__
172 DEF_MMIO_IN_D(in_be16, 16, lhz);
173 DEF_MMIO_IN_D(in_be32, 32, lwz);
174 DEF_MMIO_IN_X(in_le16, 16, lhbrx);
175 DEF_MMIO_IN_X(in_le32, 32, lwbrx);
177 DEF_MMIO_OUT_D(out_be16, 16, sth);
178 DEF_MMIO_OUT_D(out_be32, 32, stw);
179 DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
180 DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
182 DEF_MMIO_IN_X(in_be16, 16, lhbrx);
183 DEF_MMIO_IN_X(in_be32, 32, lwbrx);
184 DEF_MMIO_IN_D(in_le16, 16, lhz);
185 DEF_MMIO_IN_D(in_le32, 32, lwz);
187 DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
188 DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
189 DEF_MMIO_OUT_D(out_le16, 16, sth);
190 DEF_MMIO_OUT_D(out_le32, 32, stw);
192 #endif /* __BIG_ENDIAN */
195 * Cache inhibitied accessors for use in real mode, you don't want to use these
196 * unless you know what you're doing.
198 * NB. These use the cpu byte ordering.
200 DEF_MMIO_OUT_X(out_rm8, 8, stbcix);
201 DEF_MMIO_OUT_X(out_rm16, 16, sthcix);
202 DEF_MMIO_OUT_X(out_rm32, 32, stwcix);
203 DEF_MMIO_IN_X(in_rm8, 8, lbzcix);
204 DEF_MMIO_IN_X(in_rm16, 16, lhzcix);
205 DEF_MMIO_IN_X(in_rm32, 32, lwzcix);
209 DEF_MMIO_OUT_X(out_rm64, 64, stdcix);
210 DEF_MMIO_IN_X(in_rm64, 64, ldcix);
212 #ifdef __BIG_ENDIAN__
213 DEF_MMIO_OUT_D(out_be64, 64, std);
214 DEF_MMIO_IN_D(in_be64, 64, ld);
216 /* There is no asm instructions for 64 bits reverse loads and stores */
217 static inline u64 in_le64(const volatile u64 __iomem *addr)
219 return swab64(in_be64(addr));
222 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
224 out_be64(addr, swab64(val));
227 DEF_MMIO_OUT_D(out_le64, 64, std);
228 DEF_MMIO_IN_D(in_le64, 64, ld);
230 /* There is no asm instructions for 64 bits reverse loads and stores */
231 static inline u64 in_be64(const volatile u64 __iomem *addr)
233 return swab64(in_le64(addr));
236 static inline void out_be64(volatile u64 __iomem *addr, u64 val)
238 out_le64(addr, swab64(val));
242 #endif /* __powerpc64__ */
246 * Simple Cache inhibited accessors
247 * Unlike the DEF_MMIO_* macros, these don't include any h/w memory
248 * barriers, callers need to manage memory barriers on their own.
249 * These can only be used in hypervisor real mode.
252 static inline u32 _lwzcix(unsigned long addr)
256 __asm__ __volatile__("lwzcix %0,0, %1"
257 : "=r" (ret) : "r" (addr) : "memory");
261 static inline void _stbcix(u64 addr, u8 val)
263 __asm__ __volatile__("stbcix %0,0,%1"
264 : : "r" (val), "r" (addr) : "memory");
267 static inline void _stwcix(u64 addr, u32 val)
269 __asm__ __volatile__("stwcix %0,0,%1"
270 : : "r" (val), "r" (addr) : "memory");
274 * Low level IO stream instructions are defined out of line for now
276 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
277 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
278 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
279 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
280 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
281 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
283 /* The _ns naming is historical and will be removed. For now, just #define
284 * the non _ns equivalent names
286 #define _insw _insw_ns
287 #define _insl _insl_ns
288 #define _outsw _outsw_ns
289 #define _outsl _outsl_ns
293 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
296 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
297 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
299 extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
304 * PCI and standard ISA accessors
306 * Those are globally defined linux accessors for devices on PCI or ISA
307 * busses. They follow the Linux defined semantics. The current implementation
308 * for PowerPC is as close as possible to the x86 version of these, and thus
309 * provides fairly heavy weight barriers for the non-raw versions
311 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
312 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
313 * own implementation of some or all of the accessors.
317 * Include the EEH definitions when EEH is enabled only so they don't get
318 * in the way when building for 32 bits
324 /* Shortcut to the MMIO argument pointer */
325 #define PCI_IO_ADDR volatile void __iomem *
327 /* Indirect IO address tokens:
329 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
330 * on all MMIOs. (Note that this is all 64 bits only for now)
332 * To help platforms who may need to differentiate MMIO addresses in
333 * their hooks, a bitfield is reserved for use by the platform near the
334 * top of MMIO addresses (not PIO, those have to cope the hard way).
336 * The highest address in the kernel virtual space are:
338 * d0003fffffffffff # with Hash MMU
339 * c00fffffffffffff # with Radix MMU
341 * The top 4 bits are reserved as the region ID on hash, leaving us 8 bits
342 * that can be used for the field.
344 * The direct IO mapping operations will then mask off those bits
345 * before doing the actual access, though that only happen when
346 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
349 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
350 * all PIO functions call through a hook.
353 #ifdef CONFIG_PPC_INDIRECT_MMIO
354 #define PCI_IO_IND_TOKEN_SHIFT 52
355 #define PCI_IO_IND_TOKEN_MASK (0xfful << PCI_IO_IND_TOKEN_SHIFT)
356 #define PCI_FIX_ADDR(addr) \
357 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
358 #define PCI_GET_ADDR_TOKEN(addr) \
359 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
360 PCI_IO_IND_TOKEN_SHIFT)
361 #define PCI_SET_ADDR_TOKEN(addr, token) \
363 unsigned long __a = (unsigned long)(addr); \
364 __a &= ~PCI_IO_IND_TOKEN_MASK; \
365 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
366 (addr) = (void __iomem *)__a; \
369 #define PCI_FIX_ADDR(addr) (addr)
374 * Non ordered and non-swapping "raw" accessors
377 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
379 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
381 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
383 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
385 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
387 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
389 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
391 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
393 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
395 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
397 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
399 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
403 static inline unsigned long __raw_readq(const volatile void __iomem *addr)
405 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
407 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
409 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
413 * Real mode version of the above. stdcix is only supposed to be used
414 * in hypervisor real mode as per the architecture spec.
416 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
418 __asm__ __volatile__("stdcix %0,0,%1"
419 : : "r" (val), "r" (paddr) : "memory");
422 #endif /* __powerpc64__ */
426 * PCI PIO and MMIO accessors.
429 * On 32 bits, PIO operations have a recovery mechanism in case they trigger
430 * machine checks (which they occasionally do when probing non existing
431 * IO ports on some platforms, like PowerMac and 8xx).
432 * I always found it to be of dubious reliability and I am tempted to get
433 * rid of it one of these days. So if you think it's important to keep it,
434 * please voice up asap. We never had it for 64 bits and I do not intend
440 #define __do_in_asm(name, op) \
441 static inline unsigned int name(unsigned int port) \
444 __asm__ __volatile__( \
446 "0:" op " %0,0,%1\n" \
451 ".section .fixup,\"ax\"\n" \
455 ".section __ex_table,\"a\"\n" \
463 : "r" (port + _IO_BASE) \
468 #define __do_out_asm(name, op) \
469 static inline void name(unsigned int val, unsigned int port) \
471 __asm__ __volatile__( \
473 "0:" op " %0,0,%1\n" \
476 ".section __ex_table,\"a\"\n" \
481 : : "r" (val), "r" (port + _IO_BASE) \
485 __do_in_asm(_rec_inb, "lbzx")
486 __do_in_asm(_rec_inw, "lhbrx")
487 __do_in_asm(_rec_inl, "lwbrx")
488 __do_out_asm(_rec_outb, "stbx")
489 __do_out_asm(_rec_outw, "sthbrx")
490 __do_out_asm(_rec_outl, "stwbrx")
492 #endif /* CONFIG_PPC32 */
494 /* The "__do_*" operations below provide the actual "base" implementation
495 * for each of the defined accessors. Some of them use the out_* functions
496 * directly, some of them still use EEH, though we might change that in the
497 * future. Those macros below provide the necessary argument swapping and
498 * handling of the IO base for PIO.
500 * They are themselves used by the macros that define the actual accessors
501 * and can be used by the hooks if any.
503 * Note that PIO operations are always defined in terms of their corresonding
504 * MMIO operations. That allows platforms like iSeries who want to modify the
505 * behaviour of both to only hook on the MMIO version and get both. It's also
506 * possible to hook directly at the toplevel PIO operation if they have to
507 * be handled differently
509 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
510 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
511 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
512 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
513 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
514 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
515 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
518 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
519 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
520 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
521 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
522 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
523 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
524 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
525 #else /* CONFIG_EEH */
526 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
527 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
528 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
529 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
530 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
531 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
532 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
533 #endif /* !defined(CONFIG_EEH) */
536 #define __do_outb(val, port) _rec_outb(val, port)
537 #define __do_outw(val, port) _rec_outw(val, port)
538 #define __do_outl(val, port) _rec_outl(val, port)
539 #define __do_inb(port) _rec_inb(port)
540 #define __do_inw(port) _rec_inw(port)
541 #define __do_inl(port) _rec_inl(port)
542 #else /* CONFIG_PPC32 */
543 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
544 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
545 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
546 #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
547 #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
548 #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
549 #endif /* !CONFIG_PPC32 */
552 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
553 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
554 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
555 #else /* CONFIG_EEH */
556 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
557 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
558 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
559 #endif /* !CONFIG_EEH */
560 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
561 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
562 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
564 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
565 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
566 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
567 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
568 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
569 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
571 #define __do_memset_io(addr, c, n) \
572 _memset_io(PCI_FIX_ADDR(addr), c, n)
573 #define __do_memcpy_toio(dst, src, n) \
574 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
577 #define __do_memcpy_fromio(dst, src, n) \
578 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
579 #else /* CONFIG_EEH */
580 #define __do_memcpy_fromio(dst, src, n) \
581 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
582 #endif /* !CONFIG_EEH */
584 #ifdef CONFIG_PPC_INDIRECT_PIO
585 #define DEF_PCI_HOOK_pio(x) x
587 #define DEF_PCI_HOOK_pio(x) NULL
590 #ifdef CONFIG_PPC_INDIRECT_MMIO
591 #define DEF_PCI_HOOK_mem(x) x
593 #define DEF_PCI_HOOK_mem(x) NULL
596 /* Structure containing all the hooks */
597 extern struct ppc_pci_io {
599 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
600 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
602 #include <asm/io-defs.h>
604 #undef DEF_PCI_AC_RET
605 #undef DEF_PCI_AC_NORET
609 /* The inline wrappers */
610 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
611 static inline ret name at \
613 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
614 return ppc_pci_io.name al; \
615 return __do_##name al; \
618 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \
619 static inline void name at \
621 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
622 ppc_pci_io.name al; \
627 #include <asm/io-defs.h>
629 #undef DEF_PCI_AC_RET
630 #undef DEF_PCI_AC_NORET
632 /* Some drivers check for the presence of readq & writeq with
633 * a #ifdef, so we make them happy here.
637 #define writeq writeq
641 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
644 #define xlate_dev_mem_ptr(p) __va(p)
647 * Convert a virtual cached pointer to an uncached pointer
649 #define xlate_dev_kmem_ptr(p) p
652 * We don't do relaxed operations yet, at least not with this semantic
654 #define readb_relaxed(addr) readb(addr)
655 #define readw_relaxed(addr) readw(addr)
656 #define readl_relaxed(addr) readl(addr)
657 #define readq_relaxed(addr) readq(addr)
658 #define writeb_relaxed(v, addr) writeb(v, addr)
659 #define writew_relaxed(v, addr) writew(v, addr)
660 #define writel_relaxed(v, addr) writel(v, addr)
661 #define writeq_relaxed(v, addr) writeq(v, addr)
667 * Enforce synchronisation of stores vs. spin_unlock
668 * (this does it explicitly, though our implementation of spin_unlock
669 * does it implicitely too)
671 static inline void mmiowb(void)
675 __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)"
676 : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
679 #endif /* !CONFIG_PPC32 */
681 static inline void iosync(void)
683 __asm__ __volatile__ ("sync" : : : "memory");
686 /* Enforce in-order execution of data I/O.
687 * No distinction between read/write on PPC; use eieio for all three.
688 * Those are fairly week though. They don't provide a barrier between
689 * MMIO and cacheable storage nor do they provide a barrier vs. locks,
690 * they only provide barriers between 2 __raw MMIO operations and
691 * possibly break write combining.
693 #define iobarrier_rw() eieio()
694 #define iobarrier_r() eieio()
695 #define iobarrier_w() eieio()
699 * output pause versions need a delay at least for the
700 * w83c105 ide controller in a p610.
702 #define inb_p(port) inb(port)
703 #define outb_p(val, port) (udelay(1), outb((val), (port)))
704 #define inw_p(port) inw(port)
705 #define outw_p(val, port) (udelay(1), outw((val), (port)))
706 #define inl_p(port) inl(port)
707 #define outl_p(val, port) (udelay(1), outl((val), (port)))
710 #define IO_SPACE_LIMIT ~(0UL)
714 * ioremap - map bus memory into CPU space
715 * @address: bus address of the memory
716 * @size: size of the resource to map
718 * ioremap performs a platform specific sequence of operations to
719 * make bus memory CPU accessible via the readb/readw/readl/writeb/
720 * writew/writel functions and the other mmio helpers. The returned
721 * address is not guaranteed to be usable directly as a virtual
724 * We provide a few variations of it:
726 * * ioremap is the standard one and provides non-cacheable guarded mappings
727 * and can be hooked by the platform via ppc_md
729 * * ioremap_prot allows to specify the page flags as an argument and can
730 * also be hooked by the platform via ppc_md.
732 * * ioremap_nocache is identical to ioremap
734 * * ioremap_wc enables write combining
736 * * iounmap undoes such a mapping and can be hooked
738 * * __ioremap_at (and the pending __iounmap_at) are low level functions to
739 * create hand-made mappings for use only by the PCI code and cannot
740 * currently be hooked. Must be page aligned.
742 * * __ioremap is the low level implementation used by ioremap and
743 * ioremap_prot and cannot be hooked (but can be used by a hook on one
744 * of the previous ones)
746 * * __ioremap_caller is the same as above but takes an explicit caller
747 * reference rather than using __builtin_return_address(0)
749 * * __iounmap, is the low level implementation used by iounmap and cannot
750 * be hooked (but can be used by a hook on iounmap)
753 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
754 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
755 unsigned long flags);
756 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
757 #define ioremap_nocache(addr, size) ioremap((addr), (size))
758 #define ioremap_uc(addr, size) ioremap((addr), (size))
760 extern void iounmap(volatile void __iomem *addr);
762 extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
763 unsigned long flags);
764 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
765 unsigned long flags, void *caller);
767 extern void __iounmap(volatile void __iomem *addr);
769 extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
770 unsigned long size, unsigned long flags);
771 extern void __iounmap_at(void *ea, unsigned long size);
774 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
775 * which needs some additional definitions here. They basically allow PIO
776 * space overall to be 1GB. This will work as long as we never try to use
777 * iomap to map MMIO below 1GB which should be fine on ppc64
779 #define HAVE_ARCH_PIO_SIZE 1
780 #define PIO_OFFSET 0x00000000UL
781 #define PIO_MASK (FULL_IO_SIZE - 1)
782 #define PIO_RESERVED (FULL_IO_SIZE)
784 #define mmio_read16be(addr) readw_be(addr)
785 #define mmio_read32be(addr) readl_be(addr)
786 #define mmio_write16be(val, addr) writew_be(val, addr)
787 #define mmio_write32be(val, addr) writel_be(val, addr)
788 #define mmio_insb(addr, dst, count) readsb(addr, dst, count)
789 #define mmio_insw(addr, dst, count) readsw(addr, dst, count)
790 #define mmio_insl(addr, dst, count) readsl(addr, dst, count)
791 #define mmio_outsb(addr, src, count) writesb(addr, src, count)
792 #define mmio_outsw(addr, src, count) writesw(addr, src, count)
793 #define mmio_outsl(addr, src, count) writesl(addr, src, count)
796 * virt_to_phys - map virtual addresses to physical
797 * @address: address to remap
799 * The returned physical address is the physical (CPU) mapping for
800 * the memory address given. It is only valid to use this function on
801 * addresses directly mapped or allocated via kmalloc.
803 * This function does not give bus mappings for DMA transfers. In
804 * almost all conceivable cases a device driver should not be using
807 static inline unsigned long virt_to_phys(volatile void * address)
809 return __pa((unsigned long)address);
813 * phys_to_virt - map physical address to virtual
814 * @address: address to remap
816 * The returned virtual address is a current CPU mapping for
817 * the memory address given. It is only valid to use this function on
818 * addresses that have a kernel mapping
820 * This function does not handle bus mappings for DMA transfers. In
821 * almost all conceivable cases a device driver should not be using
824 static inline void * phys_to_virt(unsigned long address)
826 return (void *)__va(address);
830 * Change "struct page" to physical address.
832 #define page_to_phys(page) ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT)
835 * 32 bits still uses virt_to_bus() for it's implementation of DMA
836 * mappings se we have to keep it defined here. We also have some old
837 * drivers (shame shame shame) that use bus_to_virt() and haven't been
838 * fixed yet so I need to define it here.
842 static inline unsigned long virt_to_bus(volatile void * address)
846 return __pa(address) + PCI_DRAM_OFFSET;
849 static inline void * bus_to_virt(unsigned long address)
853 return __va(address - PCI_DRAM_OFFSET);
856 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
858 #endif /* CONFIG_PPC32 */
861 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
862 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
864 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
865 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
867 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
868 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
870 /* Clear and set bits in one shot. These macros can be used to clear and
871 * set multiple bits in a register using a single read-modify-write. These
872 * macros can also be used to set a multiple-bit bit pattern using a mask,
873 * by specifying the mask in the 'clear' parameter and the new bit pattern
874 * in the 'set' parameter.
877 #define clrsetbits(type, addr, clear, set) \
878 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
881 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
882 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
885 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
886 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
888 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
889 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
891 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
893 #endif /* __KERNEL__ */
895 #endif /* _ASM_POWERPC_IO_H */