2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version
5 * 2 of the License, or (at your option) any later version.
7 #ifndef _ASM_POWERPC_CACHEFLUSH_H
8 #define _ASM_POWERPC_CACHEFLUSH_H
13 #include <asm/cputable.h>
16 * No cache flushing is required when address mappings are changed,
17 * because the caches on PowerPCs are physically addressed.
19 #define flush_cache_all() do { } while (0)
20 #define flush_cache_mm(mm) do { } while (0)
21 #define flush_cache_dup_mm(mm) do { } while (0)
22 #define flush_cache_range(vma, start, end) do { } while (0)
23 #define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
24 #define flush_icache_page(vma, page) do { } while (0)
25 #define flush_cache_vunmap(start, end) do { } while (0)
27 #ifdef CONFIG_PPC_BOOK3S_64
29 * Book3s has no ptesync after setting a pte, so without this ptesync it's
30 * possible for a kernel virtual mapping access to return a spurious fault
31 * if it's accessed right after the pte is set. The page fault handler does
32 * not expect this type of fault. flush_cache_vmap is not exactly the right
33 * place to put this, but it seems to work well enough.
35 static inline void flush_cache_vmap(unsigned long start, unsigned long end)
37 asm volatile("ptesync" ::: "memory");
40 static inline void flush_cache_vmap(unsigned long start, unsigned long end) { }
43 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
44 extern void flush_dcache_page(struct page *page);
45 #define flush_dcache_mmap_lock(mapping) do { } while (0)
46 #define flush_dcache_mmap_unlock(mapping) do { } while (0)
48 extern void flush_icache_range(unsigned long, unsigned long);
49 extern void flush_icache_user_range(struct vm_area_struct *vma,
50 struct page *page, unsigned long addr,
52 extern void __flush_dcache_icache(void *page_va);
53 extern void flush_dcache_icache_page(struct page *page);
54 #if defined(CONFIG_PPC32) && !defined(CONFIG_BOOKE)
55 extern void __flush_dcache_icache_phys(unsigned long physaddr);
57 static inline void __flush_dcache_icache_phys(unsigned long physaddr)
65 * Write any modified data cache blocks out to memory and invalidate them.
66 * Does not invalidate the corresponding instruction cache blocks.
68 static inline void flush_dcache_range(unsigned long start, unsigned long stop)
70 void *addr = (void *)(start & ~(L1_CACHE_BYTES - 1));
71 unsigned long size = stop - (unsigned long)addr + (L1_CACHE_BYTES - 1);
74 for (i = 0; i < size >> L1_CACHE_SHIFT; i++, addr += L1_CACHE_BYTES)
80 * Write any modified data cache blocks out to memory.
81 * Does not invalidate the corresponding cache lines (especially for
82 * any corresponding instruction cache).
84 static inline void clean_dcache_range(unsigned long start, unsigned long stop)
86 void *addr = (void *)(start & ~(L1_CACHE_BYTES - 1));
87 unsigned long size = stop - (unsigned long)addr + (L1_CACHE_BYTES - 1);
90 for (i = 0; i < size >> L1_CACHE_SHIFT; i++, addr += L1_CACHE_BYTES)
96 * Like above, but invalidate the D-cache. This is used by the 8xx
97 * to invalidate the cache so the PPC core doesn't get stale data
98 * from the CPM (no cache snooping here :-).
100 static inline void invalidate_dcache_range(unsigned long start,
103 void *addr = (void *)(start & ~(L1_CACHE_BYTES - 1));
104 unsigned long size = stop - (unsigned long)addr + (L1_CACHE_BYTES - 1);
107 for (i = 0; i < size >> L1_CACHE_SHIFT; i++, addr += L1_CACHE_BYTES)
112 #endif /* CONFIG_PPC32 */
114 extern void flush_dcache_range(unsigned long start, unsigned long stop);
115 extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
118 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
120 memcpy(dst, src, len); \
121 flush_icache_user_range(vma, page, vaddr, len); \
123 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
124 memcpy(dst, src, len)
126 #endif /* __KERNEL__ */
128 #endif /* _ASM_POWERPC_CACHEFLUSH_H */