1 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_
2 #define _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_
4 * PowerPC64 memory management structures
6 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
15 #include <asm/asm-compat.h>
20 * This is necessary to get the definition of PGTABLE_RANGE which we
21 * need for various slices related matters. Note that this isn't the
22 * complete pgtable.h but only a portion of it.
24 #include <asm/book3s/64/pgtable.h>
26 #include <asm/processor.h>
27 #include <asm/cpu_has_feature.h>
33 #define SLB_NUM_BOLTED 3
34 #define SLB_CACHE_ENTRIES 8
35 #define SLB_MIN_SIZE 32
37 /* Bits in the SLB ESID word */
38 #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
40 /* Bits in the SLB VSID word */
41 #define SLB_VSID_SHIFT 12
42 #define SLB_VSID_SHIFT_256M SLB_VSID_SHIFT
43 #define SLB_VSID_SHIFT_1T 24
44 #define SLB_VSID_SSIZE_SHIFT 62
45 #define SLB_VSID_B ASM_CONST(0xc000000000000000)
46 #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
47 #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
48 #define SLB_VSID_KS ASM_CONST(0x0000000000000800)
49 #define SLB_VSID_KP ASM_CONST(0x0000000000000400)
50 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
51 #define SLB_VSID_L ASM_CONST(0x0000000000000100)
52 #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
53 #define SLB_VSID_LP ASM_CONST(0x0000000000000030)
54 #define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
55 #define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
56 #define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
57 #define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
58 #define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
60 #define SLB_VSID_KERNEL (SLB_VSID_KP)
61 #define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
63 #define SLBIE_C (0x08000000)
64 #define SLBIE_SSIZE_SHIFT 25
70 #define HPTES_PER_GROUP 8
72 #define HPTE_V_SSIZE_SHIFT 62
73 #define HPTE_V_AVPN_SHIFT 7
74 #define HPTE_V_COMMON_BITS ASM_CONST(0x000fffffffffffff)
75 #define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80)
76 #define HPTE_V_AVPN_3_0 ASM_CONST(0x000fffffffffff80)
77 #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
78 #define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
79 #define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
80 #define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
81 #define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
82 #define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
83 #define HPTE_V_VALID ASM_CONST(0x0000000000000001)
86 * ISA 3.0 has a different HPTE format.
88 #define HPTE_R_3_0_SSIZE_SHIFT 58
89 #define HPTE_R_3_0_SSIZE_MASK (3ull << HPTE_R_3_0_SSIZE_SHIFT)
90 #define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
91 #define HPTE_R_TS ASM_CONST(0x4000000000000000)
92 #define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000)
93 #define HPTE_R_RPN_SHIFT 12
94 #define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000)
95 #define HPTE_R_RPN_3_0 ASM_CONST(0x01fffffffffff000)
96 #define HPTE_R_PP ASM_CONST(0x0000000000000003)
97 #define HPTE_R_PPP ASM_CONST(0x8000000000000003)
98 #define HPTE_R_N ASM_CONST(0x0000000000000004)
99 #define HPTE_R_G ASM_CONST(0x0000000000000008)
100 #define HPTE_R_M ASM_CONST(0x0000000000000010)
101 #define HPTE_R_I ASM_CONST(0x0000000000000020)
102 #define HPTE_R_W ASM_CONST(0x0000000000000040)
103 #define HPTE_R_WIMG ASM_CONST(0x0000000000000078)
104 #define HPTE_R_C ASM_CONST(0x0000000000000080)
105 #define HPTE_R_R ASM_CONST(0x0000000000000100)
106 #define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00)
107 #define HPTE_R_KEY (HPTE_R_KEY_LO | HPTE_R_KEY_HI)
109 #define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
110 #define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000)
112 /* Values for PP (assumes Ks=0, Kp=1) */
113 #define PP_RWXX 0 /* Supervisor read/write, User none */
114 #define PP_RWRX 1 /* Supervisor read/write, User read */
115 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
116 #define PP_RXRX 3 /* Supervisor read, User read */
117 #define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */
119 /* Fields for tlbiel instruction in architecture 2.06 */
120 #define TLBIEL_INVAL_SEL_MASK 0xc00 /* invalidation selector */
121 #define TLBIEL_INVAL_PAGE 0x000 /* invalidate a single page */
122 #define TLBIEL_INVAL_SET_LPID 0x800 /* invalidate a set for current LPID */
123 #define TLBIEL_INVAL_SET 0xc00 /* invalidate a set for all LPIDs */
124 #define TLBIEL_INVAL_SET_MASK 0xfff000 /* set number to inval. */
125 #define TLBIEL_INVAL_SET_SHIFT 12
127 #define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */
128 #define POWER8_TLB_SETS 512 /* # sets in POWER8 TLB */
129 #define POWER9_TLB_SETS_HASH 256 /* # sets in POWER9 TLB Hash mode */
130 #define POWER9_TLB_SETS_RADIX 128 /* # sets in POWER9 TLB Radix mode */
134 struct mmu_hash_ops {
135 void (*hpte_invalidate)(unsigned long slot,
137 int bpsize, int apsize,
138 int ssize, int local);
139 long (*hpte_updatepp)(unsigned long slot,
142 int bpsize, int apsize,
143 int ssize, unsigned long flags);
144 void (*hpte_updateboltedpp)(unsigned long newpp,
146 int psize, int ssize);
147 long (*hpte_insert)(unsigned long hpte_group,
150 unsigned long rflags,
151 unsigned long vflags,
152 int psize, int apsize,
154 long (*hpte_remove)(unsigned long hpte_group);
155 int (*hpte_removebolted)(unsigned long ea,
156 int psize, int ssize);
157 void (*flush_hash_range)(unsigned long number, int local);
158 void (*hugepage_invalidate)(unsigned long vsid,
160 unsigned char *hpte_slot_array,
161 int psize, int ssize, int local);
162 int (*resize_hpt)(unsigned long shift);
165 * To be called in real mode with interrupts disabled. No locks are
166 * taken as such, concurrent access on pre POWER5 hardware could result
168 * The linear mapping is destroyed as well.
170 void (*hpte_clear_all)(void);
172 extern struct mmu_hash_ops mmu_hash_ops;
179 extern struct hash_pte *htab_address;
180 extern unsigned long htab_size_bytes;
181 extern unsigned long htab_hash_mask;
184 static inline int shift_to_mmu_psize(unsigned int shift)
188 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
189 if (mmu_psize_defs[psize].shift == shift)
194 static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
196 if (mmu_psize_defs[mmu_psize].shift)
197 return mmu_psize_defs[mmu_psize].shift;
201 static inline unsigned long get_sllp_encoding(int psize)
205 sllp = ((mmu_psize_defs[psize].sllp & SLB_VSID_L) >> 6) |
206 ((mmu_psize_defs[psize].sllp & SLB_VSID_LP) >> 4);
210 #endif /* __ASSEMBLY__ */
214 * These are the values used by hardware in the B field of
215 * SLB entries and the first dword of MMU hashtable entries.
216 * The B field is 2 bits; the values 2 and 3 are unused and reserved.
218 #define MMU_SEGSIZE_256M 0
219 #define MMU_SEGSIZE_1T 1
222 * encode page number shift.
223 * in order to fit the 78 bit va in a 64 bit variable we shift the va by
224 * 12 bits. This enable us to address upto 76 bit va.
225 * For hpt hash from a va we can ignore the page size bits of va and for
226 * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure
227 * we work in all cases including 4k page size.
232 * HPTE Large Page (LP) details
236 #define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT)
240 static inline int slb_vsid_shift(int ssize)
242 if (ssize == MMU_SEGSIZE_256M)
243 return SLB_VSID_SHIFT;
244 return SLB_VSID_SHIFT_1T;
247 static inline int segment_shift(int ssize)
249 if (ssize == MMU_SEGSIZE_256M)
255 * This array is indexed by the LP field of the HPTE second dword.
256 * Since this field may contain some RPN bits, some entries are
257 * replicated so that we get the same value irrespective of RPN.
258 * The top 4 bits are the page size index (MMU_PAGE_*) for the
259 * actual page size, the bottom 4 bits are the base page size.
261 extern u8 hpte_page_sizes[1 << LP_BITS];
263 static inline unsigned long __hpte_page_size(unsigned long h, unsigned long l,
268 if (!(h & HPTE_V_LARGE))
271 /* Look at the 8 bit LP value */
272 lp = (l >> LP_SHIFT) & ((1 << LP_BITS) - 1);
273 i = hpte_page_sizes[lp];
278 return 1ul << mmu_psize_defs[i & 0xf].shift;
281 static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
283 return __hpte_page_size(h, l, 0);
286 static inline unsigned long hpte_base_page_size(unsigned long h, unsigned long l)
288 return __hpte_page_size(h, l, 1);
292 * The current system page and segment sizes
294 extern int mmu_kernel_ssize;
295 extern int mmu_highuser_ssize;
296 extern u16 mmu_slb_size;
297 extern unsigned long tce_alloc_start, tce_alloc_end;
300 * If the processor supports 64k normal pages but not 64k cache
301 * inhibited pages, we have to be prepared to switch processes
302 * to use 4k pages when they create cache-inhibited mappings.
303 * If this is the case, mmu_ci_restrictions will be set to 1.
305 extern int mmu_ci_restrictions;
308 * This computes the AVPN and B fields of the first dword of a HPTE,
309 * for use when we want to match an existing PTE. The bottom 7 bits
310 * of the returned value are zero.
312 static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
317 * The AVA field omits the low-order 23 bits of the 78 bits VA.
318 * These bits are not needed in the PTE, because the
319 * low-order b of these bits are part of the byte offset
320 * into the virtual page and, if b < 23, the high-order
321 * 23-b of these bits are always used in selecting the
322 * PTEGs to be searched
324 v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
325 v <<= HPTE_V_AVPN_SHIFT;
326 v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
331 * ISA v3.0 defines a new HPTE format, which differs from the old
332 * format in having smaller AVPN and ARPN fields, and the B field
333 * in the second dword instead of the first.
335 static inline unsigned long hpte_old_to_new_v(unsigned long v)
337 /* trim AVPN, drop B */
338 return v & HPTE_V_COMMON_BITS;
341 static inline unsigned long hpte_old_to_new_r(unsigned long v, unsigned long r)
343 /* move B field from 1st to 2nd dword, trim ARPN */
344 return (r & ~HPTE_R_3_0_SSIZE_MASK) |
345 (((v) >> HPTE_V_SSIZE_SHIFT) << HPTE_R_3_0_SSIZE_SHIFT);
348 static inline unsigned long hpte_new_to_old_v(unsigned long v, unsigned long r)
351 return (v & HPTE_V_COMMON_BITS) |
352 ((r & HPTE_R_3_0_SSIZE_MASK) <<
353 (HPTE_V_SSIZE_SHIFT - HPTE_R_3_0_SSIZE_SHIFT));
356 static inline unsigned long hpte_new_to_old_r(unsigned long r)
358 /* clear out B field */
359 return r & ~HPTE_R_3_0_SSIZE_MASK;
363 * This function sets the AVPN and L fields of the HPTE appropriately
364 * using the base page size and actual page size.
366 static inline unsigned long hpte_encode_v(unsigned long vpn, int base_psize,
367 int actual_psize, int ssize)
370 v = hpte_encode_avpn(vpn, base_psize, ssize);
371 if (actual_psize != MMU_PAGE_4K)
377 * This function sets the ARPN, and LP fields of the HPTE appropriately
378 * for the page size. We assume the pa is already "clean" that is properly
379 * aligned for the requested page size
381 static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize,
384 /* A 4K page needs no special encoding */
385 if (actual_psize == MMU_PAGE_4K)
386 return pa & HPTE_R_RPN;
388 unsigned int penc = mmu_psize_defs[base_psize].penc[actual_psize];
389 unsigned int shift = mmu_psize_defs[actual_psize].shift;
390 return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT);
395 * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
397 static inline unsigned long hpt_vpn(unsigned long ea,
398 unsigned long vsid, int ssize)
401 int s_shift = segment_shift(ssize);
403 mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
404 return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask);
408 * This hashes a virtual address
410 static inline unsigned long hpt_hash(unsigned long vpn,
411 unsigned int shift, int ssize)
414 unsigned long hash, vsid;
416 /* VPN_SHIFT can be atmost 12 */
417 if (ssize == MMU_SEGSIZE_256M) {
418 mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
419 hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^
420 ((vpn & mask) >> (shift - VPN_SHIFT));
422 mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
423 vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT);
424 hash = vsid ^ (vsid << 25) ^
425 ((vpn & mask) >> (shift - VPN_SHIFT)) ;
427 return hash & 0x7fffffffffUL;
430 #define HPTE_LOCAL_UPDATE 0x1
431 #define HPTE_NOHPTE_UPDATE 0x2
433 extern int __hash_page_4K(unsigned long ea, unsigned long access,
434 unsigned long vsid, pte_t *ptep, unsigned long trap,
435 unsigned long flags, int ssize, int subpage_prot);
436 extern int __hash_page_64K(unsigned long ea, unsigned long access,
437 unsigned long vsid, pte_t *ptep, unsigned long trap,
438 unsigned long flags, int ssize);
440 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
441 extern int hash_page_mm(struct mm_struct *mm, unsigned long ea,
442 unsigned long access, unsigned long trap,
443 unsigned long flags);
444 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
445 unsigned long dsisr);
446 int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
447 pte_t *ptep, unsigned long trap, unsigned long flags,
448 int ssize, unsigned int shift, unsigned int mmu_psize);
449 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
450 extern int __hash_page_thp(unsigned long ea, unsigned long access,
451 unsigned long vsid, pmd_t *pmdp, unsigned long trap,
452 unsigned long flags, int ssize, unsigned int psize);
454 static inline int __hash_page_thp(unsigned long ea, unsigned long access,
455 unsigned long vsid, pmd_t *pmdp,
456 unsigned long trap, unsigned long flags,
457 int ssize, unsigned int psize)
463 extern void hash_failure_debug(unsigned long ea, unsigned long access,
464 unsigned long vsid, unsigned long trap,
465 int ssize, int psize, int lpsize,
467 extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
468 unsigned long pstart, unsigned long prot,
469 int psize, int ssize);
470 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
471 int psize, int ssize);
472 extern void pseries_add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages);
473 extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
475 #ifdef CONFIG_PPC_PSERIES
476 void hpte_init_pseries(void);
478 static inline void hpte_init_pseries(void) { }
481 extern void hpte_init_native(void);
483 extern void slb_initialize(void);
484 extern void slb_flush_and_rebolt(void);
486 extern void slb_vmalloc_update(void);
487 extern void slb_set_size(u16 size);
488 #endif /* __ASSEMBLY__ */
491 * VSID allocation (256MB segment)
493 * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated
494 * from mmu context id and effective segment id of the address.
496 * For user processes max context id is limited to MAX_USER_CONTEXT.
498 * For kernel space, we use context ids 1-4 to map addresses as below:
499 * NOTE: each context only support 64TB now.
500 * 0x00001 - [ 0xc000000000000000 - 0xc0003fffffffffff ]
501 * 0x00002 - [ 0xd000000000000000 - 0xd0003fffffffffff ]
502 * 0x00003 - [ 0xe000000000000000 - 0xe0003fffffffffff ]
503 * 0x00004 - [ 0xf000000000000000 - 0xf0003fffffffffff ]
505 * The proto-VSIDs are then scrambled into real VSIDs with the
506 * multiplicative hash:
508 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
510 * VSID_MULTIPLIER is prime, so in particular it is
511 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
512 * Because the modulus is 2^n-1 we can compute it efficiently without
513 * a divide or extra multiply (see below). The scramble function gives
514 * robust scattering in the hash table (at least based on some initial
517 * We use VSID 0 to indicate an invalid VSID. The means we can't use context id
518 * 0, because a context id of 0 and an EA of 0 gives a proto-VSID of 0, which
519 * will produce a VSID of 0.
521 * We also need to avoid the last segment of the last context, because that
522 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0
523 * because of the modulo operation in vsid scramble.
527 * Max Va bits we support as of now is 68 bits. We want 19 bit
530 * GPU has restrictions of not able to access beyond 128TB
531 * (47 bit effective address). We also cannot do more than 20bit PID.
532 * For p4 and p5 which can only do 65 bit VA, we restrict our CONTEXT_BITS
533 * to 16 bits (ie, we can only have 2^16 pids at the same time).
536 #define CONTEXT_BITS 19
537 #define ESID_BITS (VA_BITS - (SID_SHIFT + CONTEXT_BITS))
538 #define ESID_BITS_1T (VA_BITS - (SID_SHIFT_1T + CONTEXT_BITS))
540 #define ESID_BITS_MASK ((1 << ESID_BITS) - 1)
541 #define ESID_BITS_1T_MASK ((1 << ESID_BITS_1T) - 1)
545 * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments
546 * available for user + kernel mapping. VSID 0 is reserved as invalid, contexts
547 * 1-4 are used for kernel mapping. Each segment contains 2^28 bytes. Each
548 * context maps 2^49 bytes (512TB).
550 * We also need to avoid the last segment of the last context, because that
551 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0
552 * because of the modulo operation in vsid scramble.
554 #define MAX_USER_CONTEXT ((ASM_CONST(1) << CONTEXT_BITS) - 2)
555 #define MIN_USER_CONTEXT (5)
557 /* Would be nice to use KERNEL_REGION_ID here */
558 #define KERNEL_REGION_CONTEXT_OFFSET (0xc - 1)
561 * For platforms that support on 65bit VA we limit the context bits
563 #define MAX_USER_CONTEXT_65BIT_VA ((ASM_CONST(1) << (65 - (SID_SHIFT + ESID_BITS))) - 2)
566 * This should be computed such that protovosid * vsid_mulitplier
567 * doesn't overflow 64 bits. The vsid_mutliplier should also be
568 * co-prime to vsid_modulus. We also need to make sure that number
569 * of bits in multiplied result (dividend) is less than twice the number of
570 * protovsid bits for our modulus optmization to work.
572 * The below table shows the current values used.
573 * |-------+------------+----------------------+------------+-------------------|
574 * | | Prime Bits | proto VSID_BITS_65VA | Total Bits | 2* prot VSID_BITS |
575 * |-------+------------+----------------------+------------+-------------------|
576 * | 1T | 24 | 25 | 49 | 50 |
577 * |-------+------------+----------------------+------------+-------------------|
578 * | 256MB | 24 | 37 | 61 | 74 |
579 * |-------+------------+----------------------+------------+-------------------|
581 * |-------+------------+----------------------+------------+--------------------|
582 * | | Prime Bits | proto VSID_BITS_68VA | Total Bits | 2* proto VSID_BITS |
583 * |-------+------------+----------------------+------------+--------------------|
584 * | 1T | 24 | 28 | 52 | 56 |
585 * |-------+------------+----------------------+------------+--------------------|
586 * | 256MB | 24 | 40 | 64 | 80 |
587 * |-------+------------+----------------------+------------+--------------------|
590 #define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */
591 #define VSID_BITS_256M (VA_BITS - SID_SHIFT)
592 #define VSID_BITS_65_256M (65 - SID_SHIFT)
594 * Modular multiplicative inverse of VSID_MULTIPLIER under modulo VSID_MODULUS
596 #define VSID_MULINV_256M ASM_CONST(665548017062)
598 #define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
599 #define VSID_BITS_1T (VA_BITS - SID_SHIFT_1T)
600 #define VSID_BITS_65_1T (65 - SID_SHIFT_1T)
601 #define VSID_MULINV_1T ASM_CONST(209034062)
603 /* 1TB VSID reserved for VRMA */
604 #define VRMA_VSID 0x1ffffffUL
605 #define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT))
607 /* 4 bits per slice and we have one slice per 1TB */
608 #define SLICE_ARRAY_SIZE (H_PGTABLE_RANGE >> 41)
609 #define TASK_SLICE_ARRAY_SZ(x) ((x)->context.addr_limit >> 41)
613 #ifdef CONFIG_PPC_SUBPAGE_PROT
615 * For the sub-page protection option, we extend the PGD with one of
616 * these. Basically we have a 3-level tree, with the top level being
617 * the protptrs array. To optimize speed and memory consumption when
618 * only addresses < 4GB are being protected, pointers to the first
619 * four pages of sub-page protection words are stored in the low_prot
621 * Each page of sub-page protection words protects 1GB (4 bytes
622 * protects 64k). For the 3-level tree, each page of pointers then
625 struct subpage_prot_table {
626 unsigned long maxaddr; /* only addresses < this are protected */
627 unsigned int **protptrs[(TASK_SIZE_USER64 >> 43)];
628 unsigned int *low_prot[4];
631 #define SBP_L1_BITS (PAGE_SHIFT - 2)
632 #define SBP_L2_BITS (PAGE_SHIFT - 3)
633 #define SBP_L1_COUNT (1 << SBP_L1_BITS)
634 #define SBP_L2_COUNT (1 << SBP_L2_BITS)
635 #define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
636 #define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
638 extern void subpage_prot_free(struct mm_struct *mm);
639 extern void subpage_prot_init_new_context(struct mm_struct *mm);
641 static inline void subpage_prot_free(struct mm_struct *mm) {}
642 static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
643 #endif /* CONFIG_PPC_SUBPAGE_PROT */
647 * The code below is equivalent to this function for arguments
648 * < 2^VSID_BITS, which is all this should ever be called
649 * with. However gcc is not clever enough to compute the
650 * modulus (2^n-1) without a second multiply.
652 #define vsid_scramble(protovsid, size) \
653 ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
655 /* simplified form avoiding mod operation */
656 #define vsid_scramble(protovsid, size) \
659 x = (protovsid) * VSID_MULTIPLIER_##size; \
660 x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
661 (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
665 static inline unsigned long vsid_scramble(unsigned long protovsid,
666 unsigned long vsid_multiplier, int vsid_bits)
669 unsigned long vsid_modulus = ((1UL << vsid_bits) - 1);
671 * We have same multipler for both 256 and 1T segements now
673 vsid = protovsid * vsid_multiplier;
674 vsid = (vsid >> vsid_bits) + (vsid & vsid_modulus);
675 return (vsid + ((vsid + 1) >> vsid_bits)) & vsid_modulus;
680 /* Returns the segment size indicator for a user address */
681 static inline int user_segment_size(unsigned long addr)
683 /* Use 1T segments if possible for addresses >= 1T */
684 if (addr >= (1UL << SID_SHIFT_1T))
685 return mmu_highuser_ssize;
686 return MMU_SEGSIZE_256M;
689 static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
692 unsigned long va_bits = VA_BITS;
693 unsigned long vsid_bits;
694 unsigned long protovsid;
697 * Bad address. We return VSID 0 for that
699 if ((ea & ~REGION_MASK) >= H_PGTABLE_RANGE)
702 if (!mmu_has_feature(MMU_FTR_68_BIT_VA))
705 if (ssize == MMU_SEGSIZE_256M) {
706 vsid_bits = va_bits - SID_SHIFT;
707 protovsid = (context << ESID_BITS) |
708 ((ea >> SID_SHIFT) & ESID_BITS_MASK);
709 return vsid_scramble(protovsid, VSID_MULTIPLIER_256M, vsid_bits);
712 vsid_bits = va_bits - SID_SHIFT_1T;
713 protovsid = (context << ESID_BITS_1T) |
714 ((ea >> SID_SHIFT_1T) & ESID_BITS_1T_MASK);
715 return vsid_scramble(protovsid, VSID_MULTIPLIER_1T, vsid_bits);
719 * This is only valid for addresses >= PAGE_OFFSET
721 static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
723 unsigned long context;
725 if (!is_kernel_addr(ea))
729 * For kernel space, we use context ids 1-4 to map the address space as
732 * 0x00001 - [ 0xc000000000000000 - 0xc0003fffffffffff ]
733 * 0x00002 - [ 0xd000000000000000 - 0xd0003fffffffffff ]
734 * 0x00003 - [ 0xe000000000000000 - 0xe0003fffffffffff ]
735 * 0x00004 - [ 0xf000000000000000 - 0xf0003fffffffffff ]
737 * So we can compute the context from the region (top nibble) by
738 * subtracting 11, or 0xc - 1.
740 context = (ea >> 60) - KERNEL_REGION_CONTEXT_OFFSET;
742 return get_vsid(context, ea, ssize);
745 unsigned htab_shift_for_mem_size(unsigned long mem_size);
747 #endif /* __ASSEMBLY__ */
749 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ */