1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
5 #ifndef _ASM_POWERPC_BARRIER_H
6 #define _ASM_POWERPC_BARRIER_H
10 * The sync instruction guarantees that all memory accesses initiated
11 * by this processor have been performed (with respect to all other
12 * mechanisms that access memory). The eieio instruction is a barrier
13 * providing an ordering (separately) for (a) cacheable stores and (b)
14 * loads and stores to non-cacheable memory (e.g. I/O devices).
16 * mb() prevents loads and stores being reordered across this point.
17 * rmb() prevents loads being reordered across this point.
18 * wmb() prevents stores being reordered across this point.
19 * read_barrier_depends() prevents data-dependent loads being reordered
20 * across this point (nop on PPC).
22 * *mb() variants without smp_ prefix must order all types of memory
23 * operations with one another. sync is the only instruction sufficient
26 * For the smp_ barriers, ordering is for cacheable memory operations
27 * only. We have to use the sync instruction for smp_mb(), since lwsync
28 * doesn't order loads with respect to previous stores. Lwsync can be
29 * used for smp_rmb() and smp_wmb().
31 * However, on CPUs that don't support lwsync, lwsync actually maps to a
32 * heavy-weight sync, so smp_wmb() can be a lighter-weight eieio.
34 #define mb() __asm__ __volatile__ ("sync" : : : "memory")
35 #define rmb() __asm__ __volatile__ ("sync" : : : "memory")
36 #define wmb() __asm__ __volatile__ ("sync" : : : "memory")
38 /* The sub-arch has lwsync */
39 #if defined(__powerpc64__) || defined(CONFIG_PPC_E500MC)
40 # define SMPWMB LWSYNC
45 /* clang defines this macro for a builtin, which will not work with runtime patching */
47 #define __lwsync() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory")
48 #define dma_rmb() __lwsync()
49 #define dma_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
51 #define __smp_lwsync() __lwsync()
53 #define __smp_mb() mb()
54 #define __smp_rmb() __lwsync()
55 #define __smp_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
58 * This is a barrier which prevents following instructions from being
59 * started until the value of the argument x is known. For example, if
60 * x is a variable loaded from memory, this prevents following
61 * instructions from being executed until the load has been performed.
63 #define data_barrier(x) \
64 asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
66 #define __smp_store_release(p, v) \
68 compiletime_assert_atomic_type(*p); \
73 #define __smp_load_acquire(p) \
75 typeof(*p) ___p1 = READ_ONCE(*p); \
76 compiletime_assert_atomic_type(*p); \
81 #ifdef CONFIG_PPC_BOOK3S_64
82 #define NOSPEC_BARRIER_SLOT nop
83 #elif defined(CONFIG_PPC_FSL_BOOK3E)
84 #define NOSPEC_BARRIER_SLOT nop; nop
87 #ifdef CONFIG_PPC_BARRIER_NOSPEC
89 * Prevent execution of subsequent instructions until preceding branches have
90 * been fully resolved and are no longer executing speculatively.
92 #define barrier_nospec_asm NOSPEC_BARRIER_FIXUP_SECTION; NOSPEC_BARRIER_SLOT
94 // This also acts as a compiler barrier due to the memory clobber.
95 #define barrier_nospec() asm (stringify_in_c(barrier_nospec_asm) ::: "memory")
97 #else /* !CONFIG_PPC_BARRIER_NOSPEC */
98 #define barrier_nospec_asm
99 #define barrier_nospec()
100 #endif /* CONFIG_PPC_BARRIER_NOSPEC */
102 #include <asm-generic/barrier.h>
104 #endif /* _ASM_POWERPC_BARRIER_H */