1 // SPDX-License-Identifier: GPL-2.0-only
3 * MPC8xx support functions
5 * Author: Scott Wood <scottwood@freescale.com>
7 * Copyright (c) 2007 Freescale Semiconductor, Inc.
17 #define MPC8XX_PLPRCR (0x284/4) /* PLL and Reset Control Register */
19 /* Return system clock from crystal frequency */
20 u32 mpc885_get_clock(u32 crystal)
24 int mfi, mfn, mfd, pdf;
27 immr = fsl_get_immr();
29 printf("mpc885_get_clock: Couldn't get IMMR base.\r\n");
33 plprcr = in_be32(&immr[MPC8XX_PLPRCR]);
35 mfi = (plprcr >> 16) & 15;
37 printf("Warning: PLPRCR[MFI] value of %d out-of-bounds\r\n",
42 pdf = (plprcr >> 1) & 0xf;
43 mfd = (plprcr >> 22) & 0x1f;
44 mfn = (plprcr >> 27) & 0x1f;
49 ret += crystal * mfn / (mfd + 1);
51 return ret / (pdf + 1);
54 /* Set common device tree fields based on the given clock frequencies. */
55 void mpc8xx_set_clocks(u32 sysclk)
59 dt_fixup_cpu_clocks(sysclk, sysclk / 16, sysclk);
61 node = finddevice("/soc/cpm");
63 setprop(node, "clock-frequency", &sysclk, 4);
65 node = finddevice("/soc/cpm/brg");
67 setprop(node, "clock-frequency", &sysclk, 4);
70 int mpc885_fixup_clocks(u32 crystal)
72 u32 sysclk = mpc885_get_clock(crystal);
76 mpc8xx_set_clocks(sysclk);