arch/powerpc/boot/dts/sbc8548-post.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * SBC8548 Device Tree Source
   4  *
   5  * Copyright 2007 Wind River Systems Inc.
   6  *
   7  * Paul Gortmaker (see MAINTAINERS for contact information)
   8  */
   9
  10 /{
  11         soc8548@e0000000 {
  12                 #address-cells = <1>;
  13                 #size-cells = <1>;
  14                 device_type = "soc";
  15                 ranges = <0x00000000 0xe0000000 0x00100000>;
  16                 bus-frequency = <0>;
  17                 compatible = "simple-bus";
  18
  19                 ecm-law@0 {
  20                         compatible = "fsl,ecm-law";
  21                         reg = <0x0 0x1000>;
  22                         fsl,num-laws = <10>;
  23                 };
  24
  25                 ecm@1000 {
  26                         compatible = "fsl,mpc8548-ecm", "fsl,ecm";
  27                         reg = <0x1000 0x1000>;
  28                         interrupts = <17 2>;
  29                         interrupt-parent = <&mpic>;
  30                 };
  31
  32                 memory-controller@2000 {
  33                         compatible = "fsl,mpc8548-memory-controller";
  34                         reg = <0x2000 0x1000>;
  35                         interrupt-parent = <&mpic>;
  36                         interrupts = <0x12 0x2>;
  37                 };
  38
  39                 L2: l2-cache-controller@20000 {
  40                         compatible = "fsl,mpc8548-l2-cache-controller";
  41                         reg = <0x20000 0x1000>;
  42                         cache-line-size = <0x20>;       // 32 bytes
  43                         cache-size = <0x80000>; // L2, 512K
  44                         interrupt-parent = <&mpic>;
  45                         interrupts = <0x10 0x2>;
  46                 };
  47
  48                 i2c@3000 {
  49                         #address-cells = <1>;
  50                         #size-cells = <0>;
  51                         cell-index = <0>;
  52                         compatible = "fsl-i2c";
  53                         reg = <0x3000 0x100>;
  54                         interrupts = <0x2b 0x2>;
  55                         interrupt-parent = <&mpic>;
  56                         dfsrr;
  57                 };
  58
  59                 i2c@3100 {
  60                         #address-cells = <1>;
  61                         #size-cells = <0>;
  62                         cell-index = <1>;
  63                         compatible = "fsl-i2c";
  64                         reg = <0x3100 0x100>;
  65                         interrupts = <0x2b 0x2>;
  66                         interrupt-parent = <&mpic>;
  67                         dfsrr;
  68                 };
  69
  70                 dma@21300 {
  71                         #address-cells = <1>;
  72                         #size-cells = <1>;
  73                         compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
  74                         reg = <0x21300 0x4>;
  75                         ranges = <0x0 0x21100 0x200>;
  76                         cell-index = <0>;
  77                         dma-channel@0 {
  78                                 compatible = "fsl,mpc8548-dma-channel",
  79                                                 "fsl,eloplus-dma-channel";
  80                                 reg = <0x0 0x80>;
  81                                 cell-index = <0>;
  82                                 interrupt-parent = <&mpic>;
  83                                 interrupts = <20 2>;
  84                         };
  85                         dma-channel@80 {
  86                                 compatible = "fsl,mpc8548-dma-channel",
  87                                                 "fsl,eloplus-dma-channel";
  88                                 reg = <0x80 0x80>;
  89                                 cell-index = <1>;
  90                                 interrupt-parent = <&mpic>;
  91                                 interrupts = <21 2>;
  92                         };
  93                         dma-channel@100 {
  94                                 compatible = "fsl,mpc8548-dma-channel",
  95                                                 "fsl,eloplus-dma-channel";
  96                                 reg = <0x100 0x80>;
  97                                 cell-index = <2>;
  98                                 interrupt-parent = <&mpic>;
  99                                 interrupts = <22 2>;
 100                         };
 101                         dma-channel@180 {
 102                                 compatible = "fsl,mpc8548-dma-channel",
 103                                                 "fsl,eloplus-dma-channel";
 104                                 reg = <0x180 0x80>;
 105                                 cell-index = <3>;
 106                                 interrupt-parent = <&mpic>;
 107                                 interrupts = <23 2>;
 108                         };
 109                 };
 110
 111                 enet0: ethernet@24000 {
 112                         #address-cells = <1>;
 113                         #size-cells = <1>;
 114                         cell-index = <0>;
 115                         device_type = "network";
 116                         model = "eTSEC";
 117                         compatible = "gianfar";
 118                         reg = <0x24000 0x1000>;
 119                         ranges = <0x0 0x24000 0x1000>;
 120                         local-mac-address = [ 00 00 00 00 00 00 ];
 121                         interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
 122                         interrupt-parent = <&mpic>;
 123                         tbi-handle = <&tbi0>;
 124                         phy-handle = <&phy0>;
 125
 126                         mdio@520 {
 127                                 #address-cells = <1>;
 128                                 #size-cells = <0>;
 129                                 compatible = "fsl,gianfar-mdio";
 130                                 reg = <0x520 0x20>;
 131
 132                                 phy0: ethernet-phy@19 {
 133                                         interrupt-parent = <&mpic>;
 134                                         interrupts = <0x6 0x1>;
 135                                         reg = <0x19>;
 136                                 };
 137                                 phy1: ethernet-phy@1a {
 138                                         interrupt-parent = <&mpic>;
 139                                         interrupts = <0x7 0x1>;
 140                                         reg = <0x1a>;
 141                                 };
 142                                 tbi0: tbi-phy@11 {
 143                                         reg = <0x11>;
 144                                         device_type = "tbi-phy";
 145                                 };
 146                         };
 147                 };
 148
 149                 enet1: ethernet@25000 {
 150                         #address-cells = <1>;
 151                         #size-cells = <1>;
 152                         cell-index = <1>;
 153                         device_type = "network";
 154                         model = "eTSEC";
 155                         compatible = "gianfar";
 156                         reg = <0x25000 0x1000>;
 157                         ranges = <0x0 0x25000 0x1000>;
 158                         local-mac-address = [ 00 00 00 00 00 00 ];
 159                         interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
 160                         interrupt-parent = <&mpic>;
 161                         tbi-handle = <&tbi1>;
 162                         phy-handle = <&phy1>;
 163
 164                         mdio@520 {
 165                                 #address-cells = <1>;
 166                                 #size-cells = <0>;
 167                                 compatible = "fsl,gianfar-tbi";
 168                                 reg = <0x520 0x20>;
 169
 170                                 tbi1: tbi-phy@11 {
 171                                         reg = <0x11>;
 172                                         device_type = "tbi-phy";
 173                                 };
 174                         };
 175                 };
 176
 177                 serial0: serial@4500 {
 178                         cell-index = <0>;
 179                         device_type = "serial";
 180                         compatible = "fsl,ns16550", "ns16550";
 181                         reg = <0x4500 0x100>;   // reg base, size
 182                         clock-frequency = <0>;  // should we fill in in uboot?
 183                         interrupts = <0x2a 0x2>;
 184                         interrupt-parent = <&mpic>;
 185                 };
 186
 187                 serial1: serial@4600 {
 188                         cell-index = <1>;
 189                         device_type = "serial";
 190                         compatible = "fsl,ns16550", "ns16550";
 191                         reg = <0x4600 0x100>;   // reg base, size
 192                         clock-frequency = <0>;  // should we fill in in uboot?
 193                         interrupts = <0x2a 0x2>;
 194                         interrupt-parent = <&mpic>;
 195                 };
 196
 197                 global-utilities@e0000 {        //global utilities reg
 198                         compatible = "fsl,mpc8548-guts";
 199                         reg = <0xe0000 0x1000>;
 200                         fsl,has-rstcr;
 201                 };
 202
 203                 crypto@30000 {
 204                         compatible = "fsl,sec2.1", "fsl,sec2.0";
 205                         reg = <0x30000 0x10000>;
 206                         interrupts = <45 2>;
 207                         interrupt-parent = <&mpic>;
 208                         fsl,num-channels = <4>;
 209                         fsl,channel-fifo-len = <24>;
 210                         fsl,exec-units-mask = <0xfe>;
 211                         fsl,descriptor-types-mask = <0x12b0ebf>;
 212                 };
 213
 214                 mpic: pic@40000 {
 215                         interrupt-controller;
 216                         #address-cells = <0>;
 217                         #interrupt-cells = <2>;
 218                         reg = <0x40000 0x40000>;
 219                         compatible = "chrp,open-pic";
 220                         device_type = "open-pic";
 221                 };
 222         };
 223
 224         pci0: pci@e0008000 {
 225                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 226                 interrupt-map = <
 227                         /* IDSEL 0x01 (PCI-X slot) @66MHz */
 228                         0x0800 0x0 0x0 0x1 &mpic 0x2 0x1
 229                         0x0800 0x0 0x0 0x2 &mpic 0x3 0x1
 230                         0x0800 0x0 0x0 0x3 &mpic 0x4 0x1
 231                         0x0800 0x0 0x0 0x4 &mpic 0x1 0x1
 232
 233                         /* IDSEL 0x11 (PCI, 3.3V 32bit) @33MHz */
 234                         0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
 235                         0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
 236                         0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
 237                         0x8800 0x0 0x0 0x4 &mpic 0x1 0x1>;
 238
 239                 interrupt-parent = <&mpic>;
 240                 interrupts = <0x18 0x2>;
 241                 bus-range = <0 0>;
 242                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 243                           0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;
 244                 clock-frequency = <66000000>;
 245                 #interrupt-cells = <1>;
 246                 #size-cells = <2>;
 247                 #address-cells = <3>;
 248                 reg = <0xe0008000 0x1000>;
 249                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 250                 device_type = "pci";
 251         };
 252
 253         pci1: pcie@e000a000 {
 254                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 255                 interrupt-map = <
 256
 257                         /* IDSEL 0x0 (PEX) */
 258                         0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
 259                         0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
 260                         0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
 261                         0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 262
 263                 interrupt-parent = <&mpic>;
 264                 interrupts = <0x1a 0x2>;
 265                 bus-range = <0x0 0xff>;
 266                 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 267                           0x01000000 0x0 0x00000000 0xe2800000 0x0 0x08000000>;
 268                 clock-frequency = <33000000>;
 269                 #interrupt-cells = <1>;
 270                 #size-cells = <2>;
 271                 #address-cells = <3>;
 272                 reg = <0xe000a000 0x1000>;
 273                 compatible = "fsl,mpc8548-pcie";
 274                 device_type = "pci";
 275                 pcie@0 {
 276                         reg = <0x0 0x0 0x0 0x0 0x0>;
 277                         #size-cells = <2>;
 278                         #address-cells = <3>;
 279                         device_type = "pci";
 280                         ranges = <0x02000000 0x0 0xa0000000
 281                                   0x02000000 0x0 0xa0000000
 282                                   0x0 0x10000000
 283
 284                                   0x01000000 0x0 0x00000000
 285                                   0x01000000 0x0 0x00000000
 286                                   0x0 0x00800000>;
 287                 };
 288         };
 289 };