2 * T4240 Silicon/SoC Device Tree Source (pre include)
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37 /include/ "e6500_power_isa.dtsi"
40 compatible = "fsl,T4240";
43 interrupt-parent = <&mpic>;
90 cpu0: PowerPC,e6500@0 {
93 clocks = <&clockgen 1 0>;
94 next-level-cache = <&L2_1>;
95 fsl,portid-mapping = <0x80000000>;
97 cpu1: PowerPC,e6500@2 {
100 clocks = <&clockgen 1 0>;
101 next-level-cache = <&L2_1>;
102 fsl,portid-mapping = <0x80000000>;
104 cpu2: PowerPC,e6500@4 {
107 clocks = <&clockgen 1 0>;
108 next-level-cache = <&L2_1>;
109 fsl,portid-mapping = <0x80000000>;
111 cpu3: PowerPC,e6500@6 {
114 clocks = <&clockgen 1 0>;
115 next-level-cache = <&L2_1>;
116 fsl,portid-mapping = <0x80000000>;
118 cpu4: PowerPC,e6500@8 {
121 clocks = <&clockgen 1 1>;
122 next-level-cache = <&L2_2>;
123 fsl,portid-mapping = <0x40000000>;
125 cpu5: PowerPC,e6500@10 {
128 clocks = <&clockgen 1 1>;
129 next-level-cache = <&L2_2>;
130 fsl,portid-mapping = <0x40000000>;
132 cpu6: PowerPC,e6500@12 {
135 clocks = <&clockgen 1 1>;
136 next-level-cache = <&L2_2>;
137 fsl,portid-mapping = <0x40000000>;
139 cpu7: PowerPC,e6500@14 {
142 clocks = <&clockgen 1 1>;
143 next-level-cache = <&L2_2>;
144 fsl,portid-mapping = <0x40000000>;
146 cpu8: PowerPC,e6500@16 {
149 clocks = <&clockgen 1 2>;
150 next-level-cache = <&L2_3>;
151 fsl,portid-mapping = <0x20000000>;
153 cpu9: PowerPC,e6500@18 {
156 clocks = <&clockgen 1 2>;
157 next-level-cache = <&L2_3>;
158 fsl,portid-mapping = <0x20000000>;
160 cpu10: PowerPC,e6500@20 {
163 clocks = <&clockgen 1 2>;
164 next-level-cache = <&L2_3>;
165 fsl,portid-mapping = <0x20000000>;
167 cpu11: PowerPC,e6500@22 {
170 clocks = <&clockgen 1 2>;
171 next-level-cache = <&L2_3>;
172 fsl,portid-mapping = <0x20000000>;