2 * T4240QDS Device Tree Source
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
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7 * modification, are permitted provided that the following conditions are met:
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19 * GNU General Public License ("GPL") as published by the Free Software
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35 /include/ "t4240si-pre.dtsi"
38 model = "fsl,T4240QDS";
39 compatible = "fsl,T4240QDS";
42 interrupt-parent = <&mpic>;
45 phy_rgmii1 = &phyrgmii1;
46 phy_rgmii2 = &phyrgmii2;
51 sgmii_phy11 = &sgmiiphy11;
52 sgmii_phy12 = &sgmiiphy12;
53 sgmii_phy13 = &sgmiiphy13;
54 sgmii_phy14 = &sgmiiphy14;
55 sgmii_phy21 = &sgmiiphy21;
56 sgmii_phy22 = &sgmiiphy22;
57 sgmii_phy23 = &sgmiiphy23;
58 sgmii_phy24 = &sgmiiphy24;
59 sgmii_phy31 = &sgmiiphy31;
60 sgmii_phy32 = &sgmiiphy32;
61 sgmii_phy33 = &sgmiiphy33;
62 sgmii_phy34 = &sgmiiphy34;
63 sgmii_phy41 = &sgmiiphy41;
64 sgmii_phy42 = &sgmiiphy42;
65 sgmii_phy43 = &sgmiiphy43;
66 sgmii_phy44 = &sgmiiphy44;
71 xfi_pcs_mdio1 = &xfimdio0;
72 xfi_pcs_mdio2 = &xfimdio1;
73 xfi_pcs_mdio3 = &xfimdio2;
74 xfi_pcs_mdio4 = &xfimdio3;
75 emi1_rgmii = &t4240mdio0;
76 emi1_slot1 = &t4240mdio1;
77 emi1_slot2 = &t4240mdio2;
78 emi1_slot3 = &t4240mdio3;
79 emi1_slot4 = &t4240mdio4;
82 ifc: localbus@ffe124000 {
83 reg = <0xf 0xfe124000 0 0x2000>;
84 ranges = <0 0 0xf 0xe8000000 0x08000000
85 2 0 0xf 0xff800000 0x00010000
86 3 0 0xf 0xffdf0000 0x00008000>;
91 compatible = "cfi-flash";
92 reg = <0x0 0x0 0x8000000>;
101 compatible = "fsl,ifc-nand";
102 reg = <0x2 0x0 0x10000>;
105 /* This location must not be altered */
106 /* 1MB for u-boot Bootloader Image */
107 reg = <0x0 0x00100000>;
108 label = "NAND U-Boot Image";
113 /* 1MB for DTB Image */
114 reg = <0x00100000 0x00100000>;
115 label = "NAND DTB Image";
119 /* 10MB for Linux Kernel Image */
120 reg = <0x00200000 0x00A00000>;
121 label = "NAND Linux Kernel Image";
125 /* 500MB for Root file System Image */
126 reg = <0x00c00000 0x1F400000>;
127 label = "NAND RFS Image";
132 #address-cells = <1>;
134 compatible = "fsl,t4240qds-fpga", "fsl,fpga-qixis";
136 ranges = <0 3 0 0x300>;
139 #address-cells = <1>;
141 compatible = "mdio-mux-mmioreg", "mdio-mux";
142 mdio-parent-bus = <&mdio1>;
147 #address-cells = <1>;
151 phyrgmii1: ethernet-phy@1 {
155 phyrgmii2: ethernet-phy@2 {
160 t4240mdio1: mdio@20 {
161 #address-cells = <1>;
166 phy1: ethernet-phy@0 {
170 phy2: ethernet-phy@1 {
174 phy3: ethernet-phy@2 {
178 phy4: ethernet-phy@3 {
182 sgmiiphy11: ethernet-phy@1c {
186 sgmiiphy12: ethernet-phy@1d {
190 sgmiiphy13: ethernet-phy@1e {
194 sgmiiphy14: ethernet-phy@1f {
199 t4240mdio2: mdio@40 {
200 #address-cells = <1>;
205 phy5: ethernet-phy@4 {
209 phy6: ethernet-phy@5 {
213 phy7: ethernet-phy@6 {
217 phy8: ethernet-phy@7 {
221 sgmiiphy21: ethernet-phy@1c {
225 sgmiiphy22: ethernet-phy@1d {
229 sgmiiphy23: ethernet-phy@1e {
233 sgmiiphy24: ethernet-phy@1f {
238 t4240mdio3: mdio@60 {
239 #address-cells = <1>;
244 phy9: ethernet-phy@8 {
248 phy10: ethernet-phy@9 {
252 phy11: ethernet-phy@a {
256 phy12: ethernet-phy@b {
260 sgmiiphy31: ethernet-phy@1c {
264 sgmiiphy32: ethernet-phy@1d {
268 sgmiiphy33: ethernet-phy@1e {
272 sgmiiphy34: ethernet-phy@1f {
277 t4240mdio4: mdio@80 {
278 #address-cells = <1>;
283 phy13: ethernet-phy@c {
287 phy14: ethernet-phy@d {
291 phy15: ethernet-phy@e {
295 phy16: ethernet-phy@f {
299 sgmiiphy41: ethernet-phy@1c {
303 sgmiiphy42: ethernet-phy@1d {
307 sgmiiphy43: ethernet-phy@1e {
311 sgmiiphy44: ethernet-phy@1f {
320 device_type = "memory";
324 #address-cells = <2>;
328 bman_fbpr: bman-fbpr {
329 size = <0 0x1000000>;
330 alignment = <0 0x1000000>;
334 alignment = <0 0x400000>;
336 qman_pfdr: qman-pfdr {
337 size = <0 0x2000000>;
338 alignment = <0 0x2000000>;
342 dcsr: dcsr@f00000000 {
343 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
346 bportals: bman-portals@ff4000000 {
347 ranges = <0x0 0xf 0xf4000000 0x2000000>;
350 qportals: qman-portals@ff6000000 {
351 ranges = <0x0 0xf 0xf6000000 0x2000000>;
355 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
356 reg = <0xf 0xfe000000 0 0x00001000>;
359 #address-cells = <1>;
361 compatible = "sst,sst25wf040", "jedec,spi-nor";
363 spi-max-frequency = <40000000>; /* input clock */
369 compatible = "nxp,pca9547";
371 #address-cells = <1>;
375 #address-cells = <1>;
380 compatible = "atmel,24c256";
384 compatible = "atmel,24c256";
388 compatible = "atmel,24c256";
392 compatible = "atmel,24c256";
396 compatible = "atmel,24c256";
400 compatible = "atmel,24c256";
404 compatible = "dallas,ds3232";
406 interrupts = <0x1 0x1 0 0>;
411 #address-cells = <1>;
416 compatible = "ti,ina220";
418 shunt-resistor = <1000>;
422 compatible = "ti,ina220";
424 shunt-resistor = <1000>;
428 compatible = "ti,ina220";
430 shunt-resistor = <1000>;
434 compatible = "ti,ina220";
436 shunt-resistor = <1000>;
440 compatible = "ti,ina220";
442 shunt-resistor = <1000>;
446 compatible = "ti,ina220";
448 shunt-resistor = <1000>;
455 voltage-ranges = <1800 1800 3300 3300>;
480 phy-handle = <&phy5>;
481 phy-connection-type = "sgmii";
485 phy-handle = <&phy6>;
486 phy-connection-type = "sgmii";
490 phy-handle = <&phy7>;
491 phy-connection-type = "sgmii";
495 phy-handle = <&phy8>;
496 phy-connection-type = "sgmii";
500 phy-handle = <&phyrgmii2>;
501 phy-connection-type = "rgmii";
505 phy-handle = <&phy2>;
506 phy-connection-type = "sgmii";
510 phy-handle = <&xauiphy1>;
511 phy-connection-type = "xgmii";
515 phy-handle = <&xauiphy2>;
516 phy-connection-type = "xgmii";
519 xfimdio0: mdio@f1000 {
522 xfiphy1: ethernet-phy@0 {
523 compatible = "ethernet-phy-ieee802.3-c45";
528 xfimdio1: mdio@f3000 {
531 xfiphy2: ethernet-phy@0 {
532 compatible = "ethernet-phy-ieee802.3-c45";
556 phy-handle = <&phy13>;
557 phy-connection-type = "sgmii";
561 phy-handle = <&phy14>;
562 phy-connection-type = "sgmii";
566 phy-handle = <&phy15>;
567 phy-connection-type = "sgmii";
571 phy-handle = <&phy16>;
572 phy-connection-type = "sgmii";
576 phy-handle = <&phyrgmii1>;
577 phy-connection-type = "rgmii";
581 phy-handle = <&phy10>;
582 phy-connection-type = "sgmii";
586 phy-handle = <&xauiphy3>;
587 phy-connection-type = "xgmii";
591 phy-handle = <&xauiphy4>;
592 phy-connection-type = "xgmii";
595 xfimdio2: mdio@f1000 {
598 xfiphy3: ethernet-phy@0 {
599 compatible = "ethernet-phy-ieee802.3-c45";
604 xfimdio3: mdio@f3000 {
607 xfiphy4: ethernet-phy@0 {
608 compatible = "ethernet-phy-ieee802.3-c45";
614 xauiphy1: ethernet-phy@0 {
615 compatible = "ethernet-phy-ieee802.3-c45";
619 xauiphy2: ethernet-phy@1 {
620 compatible = "ethernet-phy-ieee802.3-c45";
624 xauiphy3: ethernet-phy@2 {
625 compatible = "ethernet-phy-ieee802.3-c45";
629 xauiphy4: ethernet-phy@3 {
630 compatible = "ethernet-phy-ieee802.3-c45";
637 pci0: pcie@ffe240000 {
638 reg = <0xf 0xfe240000 0 0x10000>;
639 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
640 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
642 ranges = <0x02000000 0 0xe0000000
643 0x02000000 0 0xe0000000
646 0x01000000 0 0x00000000
647 0x01000000 0 0x00000000
652 pci1: pcie@ffe250000 {
653 reg = <0xf 0xfe250000 0 0x10000>;
654 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
655 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
657 ranges = <0x02000000 0 0xe0000000
658 0x02000000 0 0xe0000000
661 0x01000000 0 0x00000000
662 0x01000000 0 0x00000000
667 pci2: pcie@ffe260000 {
668 reg = <0xf 0xfe260000 0 0x1000>;
669 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
670 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
672 ranges = <0x02000000 0 0xe0000000
673 0x02000000 0 0xe0000000
676 0x01000000 0 0x00000000
677 0x01000000 0 0x00000000
682 pci3: pcie@ffe270000 {
683 reg = <0xf 0xfe270000 0 0x10000>;
684 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
685 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
687 ranges = <0x02000000 0 0xe0000000
688 0x02000000 0 0xe0000000
691 0x01000000 0 0x00000000
692 0x01000000 0 0x00000000
696 rio: rapidio@ffe0c0000 {
697 reg = <0xf 0xfe0c0000 0 0x11000>;
700 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
703 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
708 /include/ "t4240si-post.dtsi"