2 * T104xQDS Device Tree Source
4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
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36 model = "fsl,T1040QDS";
39 interrupt-parent = <&mpic>;
42 emi1_rgmii0 = &t1040mdio0;
43 emi1_rgmii1 = &t1040mdio1;
44 emi1_slot3 = &t1040mdio3;
45 emi1_slot5 = &t1040mdio5;
46 emi1_slot6 = &t1040mdio6;
47 emi1_slot7 = &t1040mdio7;
48 rgmii_phy1 = &rgmii_phy1;
49 rgmii_phy2 = &rgmii_phy2;
50 phy_s3_01 = &phy_s3_01;
51 phy_s3_02 = &phy_s3_02;
52 phy_s3_03 = &phy_s3_03;
53 phy_s3_04 = &phy_s3_04;
54 phy_s5_01 = &phy_s5_01;
55 phy_s5_02 = &phy_s5_02;
56 phy_s5_03 = &phy_s5_03;
57 phy_s5_04 = &phy_s5_04;
58 phy_s6_01 = &phy_s6_01;
59 phy_s6_02 = &phy_s6_02;
60 phy_s6_03 = &phy_s6_03;
61 phy_s6_04 = &phy_s6_04;
62 phy_s7_01 = &phy_s7_01;
63 phy_s7_02 = &phy_s7_02;
64 phy_s7_03 = &phy_s7_03;
65 phy_s7_04 = &phy_s7_04;
73 bman_fbpr: bman-fbpr {
75 alignment = <0 0x1000000>;
79 alignment = <0 0x400000>;
81 qman_pfdr: qman-pfdr {
83 alignment = <0 0x2000000>;
87 ifc: localbus@ffe124000 {
88 reg = <0xf 0xfe124000 0 0x2000>;
89 ranges = <0 0 0xf 0xe8000000 0x08000000
90 2 0 0xf 0xff800000 0x00010000
91 3 0 0xf 0xffdf0000 0x00008000>;
96 compatible = "cfi-flash";
97 reg = <0x0 0x0 0x8000000>;
104 #address-cells = <1>;
106 compatible = "fsl,ifc-nand";
107 reg = <0x2 0x0 0x10000>;
111 #address-cells = <1>;
113 compatible = "fsl,fpga-qixis";
115 ranges = <0 3 0 0x300>;
118 #address-cells = <1>;
120 compatible = "mdio-mux-mmioreg", "mdio-mux";
121 mdio-parent-bus = <&mdio0>;
126 #address-cells = <1>;
131 rgmii_phy1: ethernet-phy@1 {
136 t1040mdio1: mdio@20 {
137 #address-cells = <1>;
142 rgmii_phy2: ethernet-phy@2 {
147 t1040mdio3: mdio@60 {
148 #address-cells = <1>;
153 phy_s3_01: ethernet-phy@1c {
157 phy_s3_02: ethernet-phy@1d {
161 phy_s3_03: ethernet-phy@1e {
165 phy_s3_04: ethernet-phy@1f {
170 t1040mdio5: mdio@a0 {
171 #address-cells = <1>;
175 phy_s5_01: ethernet-phy@1c {
179 phy_s5_02: ethernet-phy@1d {
183 phy_s5_03: ethernet-phy@1e {
187 phy_s5_04: ethernet-phy@1f {
192 t1040mdio6: mdio@c0 {
193 #address-cells = <1>;
197 phy_s6_01: ethernet-phy@1c {
201 phy_s6_02: ethernet-phy@1d {
205 phy_s6_03: ethernet-phy@1e {
209 phy_s6_04: ethernet-phy@1f {
214 t1040mdio7: mdio@e0 {
215 #address-cells = <1>;
220 phy_s7_01: ethernet-phy@1c {
224 phy_s7_02: ethernet-phy@1d {
228 phy_s7_03: ethernet-phy@1e {
232 phy_s7_04: ethernet-phy@1f {
241 device_type = "memory";
244 dcsr: dcsr@f00000000 {
245 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
248 bportals: bman-portals@ff4000000 {
249 ranges = <0x0 0xf 0xf4000000 0x2000000>;
252 qportals: qman-portals@ff6000000 {
253 ranges = <0x0 0xf 0xf6000000 0x2000000>;
257 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
258 reg = <0xf 0xfe000000 0 0x00001000>;
262 #address-cells = <1>;
264 compatible = "micron,n25q128a11", "jedec,spi-nor";
266 spi-max-frequency = <10000000>; /* input clock */
272 compatible = "nxp,pca9547";
276 compatible = "dallas,ds3232";
278 interrupts = <0x1 0x1 0 0>;
284 fixed-link = <0 1 1000 0 0>;
285 phy-connection-type = "sgmii";
289 fixed-link = <1 1 1000 0 0>;
290 phy-connection-type = "sgmii";
294 phy-handle = <&phy_s7_03>;
295 phy-connection-type = "sgmii";
299 phy-handle = <&rgmii_phy1>;
300 phy-connection-type = "rgmii";
304 phy-handle = <&rgmii_phy2>;
305 phy-connection-type = "rgmii";
310 pci0: pcie@ffe240000 {
311 reg = <0xf 0xfe240000 0 0x10000>;
312 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000
313 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
315 ranges = <0x02000000 0 0xe0000000
316 0x02000000 0 0xe0000000
319 0x01000000 0 0x00000000
320 0x01000000 0 0x00000000
325 pci1: pcie@ffe250000 {
326 reg = <0xf 0xfe250000 0 0x10000>;
327 ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
328 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
330 ranges = <0x02000000 0 0xe0000000
331 0x02000000 0 0xe0000000
334 0x01000000 0 0x00000000
335 0x01000000 0 0x00000000
340 pci2: pcie@ffe260000 {
341 reg = <0xf 0xfe260000 0 0x10000>;
342 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
343 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
345 ranges = <0x02000000 0 0xe0000000
346 0x02000000 0 0xe0000000
349 0x01000000 0 0x00000000
350 0x01000000 0 0x00000000
355 pci3: pcie@ffe270000 {
356 reg = <0xf 0xfe270000 0 0x10000>;
357 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
358 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
360 ranges = <0x02000000 0 0xe0000000
361 0x02000000 0 0xe0000000
364 0x01000000 0 0x00000000
365 0x01000000 0 0x00000000
371 ranges = <0x0 0xf 0xfe140000 0x40000>;
372 reg = <0xf 0xfe140000 0 0x480>;
377 compatible = "fsl,t1040-qe-si";
382 compatible = "fsl,t1040-qe-siram";
383 reg = <0x1000 0x800>;
387 compatible = "fsl,ucc-hdlc";
388 rx-clock-name = "clk8";
389 tx-clock-name = "clk9";
390 fsl,rx-sync-clock = "rsync_pin";
391 fsl,tx-sync-clock = "tsync_pin";
392 fsl,tx-timeslot-mask = <0xfffffffe>;
393 fsl,rx-timeslot-mask = <0xfffffffe>;
394 fsl,tdm-framer-type = "e1";
396 fsl,siram-entry-id = <0>;
400 ucc_serial: ucc@2200 {
401 compatible = "fsl,t1040-ucc-uart";
403 rx-clock-name = "brg2";
404 tx-clock-name = "brg2";