1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PPA8548 Device Tree Source (36-bit address map)
4 * Copyright 2013 Prodrive B.V.
7 * MPC8548 CDS Device Tree Source (36-bit address map)
8 * Copyright 2012 Freescale Semiconductor Inc.
11 /include/ "mpc8548si-pre.dtsi"
15 compatible = "ppa8548";
18 interrupt-parent = <&mpic>;
21 device_type = "memory";
22 reg = <0 0 0x0 0x40000000>;
25 lbc: localbus@fe0005000 {
26 reg = <0xf 0xe0005000 0 0x1000>;
27 ranges = <0x0 0x0 0xf 0xff800000 0x00800000>;
30 soc: soc8548@fe0000000 {
31 ranges = <0 0xf 0xe0000000 0x100000>;
35 /* ppa8548 board doesn't support PCI */
40 /* ppa8548 board doesn't support PCI */
44 pci2: pcie@fe000a000 {
45 /* ppa8548 board doesn't support PCI */
49 rio: rapidio@fe00c0000 {
50 reg = <0xf 0xe00c0000 0x0 0x11000>;
52 ranges = <0x0 0x0 0x0 0x80000000 0x0 0x40000000>;
61 compatible = "cfi-flash";
62 reg = <0x0 0x0 0x00800000>;
72 reg = <0x7A0000 0x20000>;
78 reg = <0x7C0000 0x40000>;
88 compatible = "intersil,isl1208";
97 * Only ethernet controller @25000 and @26000 are used.
98 * Use alias enet2 and enet3 for the remainig controllers,
99 * to stay compatible with mpc8548si-pre.dtsi.
101 enet2: ethernet@24000 {
106 phy0: ethernet-phy@0 {
107 interrupts = <7 1 0 0>;
110 phy1: ethernet-phy@1 {
111 interrupts = <8 1 0 0>;
116 device_type = "tbi-phy";
120 enet0: ethernet@25000 {
121 tbi-handle = <&tbi1>;
122 phy-handle = <&phy0>;
128 device_type = "tbi-phy";
132 enet1: ethernet@26000 {
133 tbi-handle = <&tbi2>;
134 phy-handle = <&phy1>;
140 device_type = "tbi-phy";
144 enet3: ethernet@27000 {
151 device_type = "tbi-phy";
160 /include/ "mpc8548si-post.dtsi"