2 * P2020/P2010 Silicon/SoC Device Tree Source (post include)
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38 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
42 /* controller at 0xa000 */
44 compatible = "fsl,mpc8548-pcie";
49 clock-frequency = <33333333>;
50 interrupts = <26 2 0 0>;
55 #interrupt-cells = <1>;
59 interrupts = <26 2 0 0>;
60 interrupt-map-mask = <0xf800 0 0 7>;
63 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
64 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
65 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
66 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
71 /* controller at 0x9000 */
73 compatible = "fsl,mpc8548-pcie";
78 clock-frequency = <33333333>;
79 interrupts = <25 2 0 0>;
84 #interrupt-cells = <1>;
88 interrupts = <25 2 0 0>;
89 interrupt-map-mask = <0xf800 0 0 7>;
93 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
94 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
95 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
96 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
101 /* controller at 0x8000 */
103 compatible = "fsl,mpc8548-pcie";
106 #address-cells = <3>;
108 clock-frequency = <33333333>;
109 interrupts = <24 2 0 0>;
114 #interrupt-cells = <1>;
116 #address-cells = <3>;
118 interrupts = <24 2 0 0>;
119 interrupt-map-mask = <0xf800 0 0 7>;
123 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
124 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
125 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
126 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
132 #address-cells = <1>;
135 compatible = "fsl,p2020-immr", "simple-bus";
136 bus-frequency = <0>; // Filled out by uboot.
139 compatible = "fsl,ecm-law";
145 compatible = "fsl,p2020-ecm", "fsl,ecm";
146 reg = <0x1000 0x1000>;
147 interrupts = <17 2 0 0>;
150 memory-controller@2000 {
151 compatible = "fsl,p2020-memory-controller";
152 reg = <0x2000 0x1000>;
153 interrupts = <18 2 0 0>;
156 /include/ "pq3-i2c-0.dtsi"
157 /include/ "pq3-i2c-1.dtsi"
158 /include/ "pq3-duart-0.dtsi"
159 /include/ "pq3-espi-0.dtsi"
161 fsl,espi-num-chipselects = <4>;
164 /include/ "pq3-dma-1.dtsi"
165 /include/ "pq3-gpio-0.dtsi"
167 L2: l2-cache-controller@20000 {
168 compatible = "fsl,p2020-l2-cache-controller";
169 reg = <0x20000 0x1000>;
170 cache-line-size = <32>; // 32 bytes
171 cache-size = <0x80000>; // L2,512K
172 interrupts = <16 2 0 0>;
175 /include/ "pq3-dma-0.dtsi"
176 /include/ "pq3-usb2-dr-0.dtsi"
178 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
180 /include/ "pq3-etsec1-0.dtsi"
181 /include/ "pq3-etsec1-timer-0.dtsi"
184 interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
188 /include/ "pq3-etsec1-1.dtsi"
189 /include/ "pq3-etsec1-2.dtsi"
190 /include/ "pq3-esdhc-0.dtsi"
192 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
195 /include/ "pq3-sec3.1-0.dtsi"
196 /include/ "pq3-mpic.dtsi"
197 /include/ "pq3-mpic-timer-B.dtsi"
199 global-utilities@e0000 {
200 compatible = "fsl,p2020-guts";
201 reg = <0xe0000 0x1000>;
206 compatible = "fsl,mpc8548-pmc";
207 reg = <0xe0070 0x20>;