1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC8568E MDS Device Tree Source
5 * Copyright 2007, 2008 Freescale Semiconductor Inc.
8 /include/ "mpc8568si-pre.dtsi"
11 model = "MPC8568EMDS";
12 compatible = "MPC8568EMDS", "MPC85xxMDS";
21 device_type = "memory";
22 reg = <0x0 0x0 0x0 0x0>;
25 lbc: localbus@e0005000 {
26 reg = <0x0 0xe0005000 0x0 0x1000>;
27 ranges = <0x0 0x0 0xfe000000 0x02000000
28 0x1 0x0 0xf8000000 0x00008000
29 0x2 0x0 0xf0000000 0x04000000
30 0x4 0x0 0xf8008000 0x00008000
31 0x5 0x0 0xf8010000 0x00008000>;
36 compatible = "cfi-flash";
37 reg = <0x0 0x0 0x02000000>;
45 compatible = "fsl,mpc8568mds-bcsr";
47 ranges = <0 1 0 0x8000>;
49 bcsr5: gpio-controller@11 {
51 compatible = "fsl,mpc8568mds-bcsr-gpio";
58 compatible = "fsl,mpc8568mds-pib";
63 compatible = "fsl,mpc8568mds-pib";
68 soc: soc8568@e0000000 {
69 ranges = <0x0 0x0 0xe0000000 0x100000>;
74 compatible = "dallas,ds1374";
76 interrupts = <3 1 0 0>;
81 enet0: ethernet@24000 {
87 phy0: ethernet-phy@7 {
88 interrupts = <1 1 0 0>;
91 phy1: ethernet-phy@1 {
92 interrupts = <2 1 0 0>;
95 phy2: ethernet-phy@2 {
96 interrupts = <1 1 0 0>;
99 phy3: ethernet-phy@3 {
100 interrupts = <2 1 0 0>;
105 device_type = "tbi-phy";
109 enet1: ethernet@25000 {
110 tbi-handle = <&tbi1>;
111 phy-handle = <&phy3>;
112 sleep = <&pmc 0x00000040>;
118 device_type = "tbi-phy";
127 /* port pin dir open_drain assignment has_irq */
128 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
129 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
130 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
131 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
132 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
133 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
134 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
135 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
136 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
137 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
138 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
139 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
140 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
141 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
142 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
143 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
144 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
145 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
146 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
147 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
148 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
149 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
150 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
155 /* port pin dir open_drain assignment has_irq */
156 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
157 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
158 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
159 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
160 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
161 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
162 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
163 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
164 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
165 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
166 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
167 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
168 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
169 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
170 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
171 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
172 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
173 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
174 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
175 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
176 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
177 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
178 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
179 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
180 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
186 ranges = <0x0 0x0 0xe0080000 0x40000>;
187 reg = <0x0 0xe0080000 0x0 0x480>;
198 device_type = "network";
199 compatible = "ucc_geth";
200 local-mac-address = [ 00 00 00 00 00 00 ];
201 rx-clock-name = "none";
202 tx-clock-name = "clk16";
203 pio-handle = <&pio1>;
204 phy-handle = <&phy0>;
205 phy-connection-type = "rgmii-id";
209 device_type = "network";
210 compatible = "ucc_geth";
211 local-mac-address = [ 00 00 00 00 00 00 ];
212 rx-clock-name = "none";
213 tx-clock-name = "clk16";
214 pio-handle = <&pio2>;
215 phy-handle = <&phy1>;
216 phy-connection-type = "rgmii-id";
220 #address-cells = <1>;
223 compatible = "fsl,ucc-mdio";
225 /* These are the same PHYs as on
226 * gianfar's MDIO bus */
227 qe_phy0: ethernet-phy@7 {
228 interrupt-parent = <&mpic>;
229 interrupts = <1 1 0 0>;
232 qe_phy1: ethernet-phy@1 {
233 interrupt-parent = <&mpic>;
234 interrupts = <2 1 0 0>;
237 qe_phy2: ethernet-phy@2 {
238 interrupt-parent = <&mpic>;
239 interrupts = <1 1 0 0>;
242 qe_phy3: ethernet-phy@3 {
243 interrupt-parent = <&mpic>;
244 interrupts = <2 1 0 0>;
251 reg = <0x0 0xe0008000 0x0 0x1000>;
252 ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
253 0x1000000 0x0 0x00000000 0x0 0xe2000000 0x0 0x800000>;
254 clock-frequency = <66666666>;
255 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
257 /* IDSEL 0x12 AD18 */
258 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1 0 0
259 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1 0 0
260 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1 0 0
261 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 0 0
263 /* IDSEL 0x13 AD19 */
264 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1 0 0
265 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1 0 0
266 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
267 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1 0 0>;
271 pci1: pcie@e000a000 {
272 ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000
273 0x1000000 0x0 0x00000000 0x0 0xe2800000 0x0 0x800000>;
274 reg = <0x0 0xe000a000 0x0 0x1000>;
276 ranges = <0x2000000 0x0 0xa0000000
277 0x2000000 0x0 0xa0000000
286 rio: rapidio@e00c00000 {
287 reg = <0x0 0xe00c0000 0x0 0x20000>;
289 ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
294 compatible = "gpio-leds";
297 gpios = <&bcsr5 1 0>;
301 gpios = <&bcsr5 2 0>;
305 gpios = <&bcsr5 3 0>;
310 /include/ "mpc8568si-post.dtsi"