1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * GE SBC310 Device Tree Source
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
7 * Based on: SBS CM6 Device Tree Source
8 * Copyright 2007 SBS Technologies GmbH & Co. KG
9 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
10 * Copyright 2006 Freescale Semiconductor Inc.
14 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
17 /include/ "mpc8641si-pre.dtsi"
21 compatible = "gef,sbc310";
24 device_type = "memory";
25 reg = <0x0 0x40000000>; // set by uboot
28 lbc: localbus@fef05000 {
29 reg = <0xfef05000 0x1000>;
31 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
32 1 0 0xe0000000 0x08000000 // Paged Flash 0
33 2 0 0xe8000000 0x08000000 // Paged Flash 1
34 3 0 0xfc100000 0x00020000 // NVRAM
35 4 0 0xfc000000 0x00010000>; // FPGA
37 /* flash@0,0 is a mirror of part of the memory in flash@1,0
39 compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
40 reg = <0x0 0x0 0x01000000>;
47 reg = <0x0 0x01000000>;
54 compatible = "gef,sbc310-paged-flash", "cfi-flash";
55 reg = <0x1 0x0 0x8000000>;
62 reg = <0x0 0x7800000>;
66 reg = <0x7800000 0x800000>;
72 device_type = "nvram";
73 compatible = "simtek,stk14ca8";
74 reg = <0x3 0x0 0x20000>;
78 compatible = "gef,fpga-regs";
83 compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
85 reg = <0x4 0x2000 0x8>;
86 interrupts = <0x1a 0x4>;
87 interrupt-parent = <&gef_pic>;
91 compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
93 reg = <0x4 0x2010 0x8>;
94 interrupts = <0x1b 0x4>;
95 interrupt-parent = <&gef_pic>;
99 #interrupt-cells = <1>;
100 interrupt-controller;
101 compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic";
102 reg = <0x4 0x4000 0x20>;
103 interrupts = <0x8 0x9 0 0>;
106 gef_gpio: gpio@4,8000 {
108 compatible = "gef,sbc310-gpio";
109 reg = <0x4 0x8000 0x24>;
115 ranges = <0x0 0xfef00000 0x00100000>;
119 compatible = "epson,rx8581";
126 compatible = "national,lm92";
131 compatible = "adi,adt7461";
136 compatible = "dallas,ds1682";
141 enet0: ethernet@24000 {
142 tbi-handle = <&tbi0>;
143 phy-handle = <&phy0>;
144 phy-connection-type = "gmii";
148 phy0: ethernet-phy@0 {
149 interrupt-parent = <&gef_pic>;
150 interrupts = <0x9 0x4>;
153 phy2: ethernet-phy@2 {
154 interrupt-parent = <&gef_pic>;
155 interrupts = <0x8 0x4>;
160 device_type = "tbi-phy";
164 enet1: ethernet@26000 {
165 tbi-handle = <&tbi2>;
166 phy-handle = <&phy2>;
167 phy-connection-type = "gmii";
173 device_type = "tbi-phy";
177 enet2: ethernet@25000 {
185 enet3: ethernet@27000 {
194 pci0: pcie@fef08000 {
195 reg = <0xfef08000 0x1000>;
196 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
197 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
198 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
200 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
201 0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
202 0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
203 0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
207 ranges = <0x02000000 0x0 0x80000000
208 0x02000000 0x0 0x80000000
211 0x01000000 0x0 0x00000000
212 0x01000000 0x0 0x00000000
217 pci1: pcie@fef09000 {
218 reg = <0xfef09000 0x1000>;
219 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
220 0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>;
223 ranges = <0x02000000 0x0 0xc0000000
224 0x02000000 0x0 0xc0000000
227 0x01000000 0x0 0x00000000
228 0x01000000 0x0 0x00000000
234 /include/ "mpc8641si-post.dtsi"