arch/parisc/kernel/unaligned.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *    Unaligned memory access handler
   4  *
   5  *    Copyright (C) 2001 Randolph Chung <tausq@debian.org>
   6  *    Copyright (C) 2022 Helge Deller <deller@gmx.de>
   7  *    Significantly tweaked by LaMont Jones <lamont@debian.org>
   8  */
   9
  10 #include <linux/sched/signal.h>
  11 #include <linux/signal.h>
  12 #include <linux/ratelimit.h>
  13 #include <linux/uaccess.h>
  14 #include <linux/sysctl.h>
  15 #include <asm/unaligned.h>
  16 #include <asm/hardirq.h>
  17 #include <asm/traps.h>
  18
  19 /* #define DEBUG_UNALIGNED 1 */
  20
  21 #ifdef DEBUG_UNALIGNED
  22 #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
  23 #else
  24 #define DPRINTF(fmt, args...)
  25 #endif
  26
  27 #define RFMT "%#08lx"
  28
  29 /* 1111 1100 0000 0000 0001 0011 1100 0000 */
  30 #define OPCODE1(a,b,c)  ((a)<<26|(b)<<12|(c)<<6)
  31 #define OPCODE2(a,b)    ((a)<<26|(b)<<1)
  32 #define OPCODE3(a,b)    ((a)<<26|(b)<<2)
  33 #define OPCODE4(a)      ((a)<<26)
  34 #define OPCODE1_MASK    OPCODE1(0x3f,1,0xf)
  35 #define OPCODE2_MASK    OPCODE2(0x3f,1)
  36 #define OPCODE3_MASK    OPCODE3(0x3f,1)
  37 #define OPCODE4_MASK    OPCODE4(0x3f)
  38
  39 /* skip LDB - never unaligned (index) */
  40 #define OPCODE_LDH_I    OPCODE1(0x03,0,0x1)
  41 #define OPCODE_LDW_I    OPCODE1(0x03,0,0x2)
  42 #define OPCODE_LDD_I    OPCODE1(0x03,0,0x3)
  43 #define OPCODE_LDDA_I   OPCODE1(0x03,0,0x4)
  44 #define OPCODE_LDCD_I   OPCODE1(0x03,0,0x5)
  45 #define OPCODE_LDWA_I   OPCODE1(0x03,0,0x6)
  46 #define OPCODE_LDCW_I   OPCODE1(0x03,0,0x7)
  47 /* skip LDB - never unaligned (short) */
  48 #define OPCODE_LDH_S    OPCODE1(0x03,1,0x1)
  49 #define OPCODE_LDW_S    OPCODE1(0x03,1,0x2)
  50 #define OPCODE_LDD_S    OPCODE1(0x03,1,0x3)
  51 #define OPCODE_LDDA_S   OPCODE1(0x03,1,0x4)
  52 #define OPCODE_LDCD_S   OPCODE1(0x03,1,0x5)
  53 #define OPCODE_LDWA_S   OPCODE1(0x03,1,0x6)
  54 #define OPCODE_LDCW_S   OPCODE1(0x03,1,0x7)
  55 /* skip STB - never unaligned */
  56 #define OPCODE_STH      OPCODE1(0x03,1,0x9)
  57 #define OPCODE_STW      OPCODE1(0x03,1,0xa)
  58 #define OPCODE_STD      OPCODE1(0x03,1,0xb)
  59 /* skip STBY - never unaligned */
  60 /* skip STDBY - never unaligned */
  61 #define OPCODE_STWA     OPCODE1(0x03,1,0xe)
  62 #define OPCODE_STDA     OPCODE1(0x03,1,0xf)
  63
  64 #define OPCODE_FLDWX    OPCODE1(0x09,0,0x0)
  65 #define OPCODE_FLDWXR   OPCODE1(0x09,0,0x1)
  66 #define OPCODE_FSTWX    OPCODE1(0x09,0,0x8)
  67 #define OPCODE_FSTWXR   OPCODE1(0x09,0,0x9)
  68 #define OPCODE_FLDWS    OPCODE1(0x09,1,0x0)
  69 #define OPCODE_FLDWSR   OPCODE1(0x09,1,0x1)
  70 #define OPCODE_FSTWS    OPCODE1(0x09,1,0x8)
  71 #define OPCODE_FSTWSR   OPCODE1(0x09,1,0x9)
  72 #define OPCODE_FLDDX    OPCODE1(0x0b,0,0x0)
  73 #define OPCODE_FSTDX    OPCODE1(0x0b,0,0x8)
  74 #define OPCODE_FLDDS    OPCODE1(0x0b,1,0x0)
  75 #define OPCODE_FSTDS    OPCODE1(0x0b,1,0x8)
  76
  77 #define OPCODE_LDD_L    OPCODE2(0x14,0)
  78 #define OPCODE_FLDD_L   OPCODE2(0x14,1)
  79 #define OPCODE_STD_L    OPCODE2(0x1c,0)
  80 #define OPCODE_FSTD_L   OPCODE2(0x1c,1)
  81
  82 #define OPCODE_LDW_M    OPCODE3(0x17,1)
  83 #define OPCODE_FLDW_L   OPCODE3(0x17,0)
  84 #define OPCODE_FSTW_L   OPCODE3(0x1f,0)
  85 #define OPCODE_STW_M    OPCODE3(0x1f,1)
  86
  87 #define OPCODE_LDH_L    OPCODE4(0x11)
  88 #define OPCODE_LDW_L    OPCODE4(0x12)
  89 #define OPCODE_LDWM     OPCODE4(0x13)
  90 #define OPCODE_STH_L    OPCODE4(0x19)
  91 #define OPCODE_STW_L    OPCODE4(0x1A)
  92 #define OPCODE_STWM     OPCODE4(0x1B)
  93
  94 #define MAJOR_OP(i) (((i)>>26)&0x3f)
  95 #define R1(i) (((i)>>21)&0x1f)
  96 #define R2(i) (((i)>>16)&0x1f)
  97 #define R3(i) ((i)&0x1f)
  98 #define FR3(i) ((((i)&0x1f)<<1)|(((i)>>6)&1))
  99 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
 100 #define IM5_2(i) IM((i)>>16,5)
 101 #define IM5_3(i) IM((i),5)
 102 #define IM14(i) IM((i),14)
 103
 104 #define ERR_NOTHANDLED  -1
 105
 106 int unaligned_enabled __read_mostly = 1;
 107
 108 static int emulate_ldh(struct pt_regs *regs, int toreg)
 109 {
 110         unsigned long saddr = regs->ior;
 111         unsigned long val = 0, temp1;
 112         ASM_EXCEPTIONTABLE_VAR(ret);
 113
 114         DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n",
 115                 regs->isr, regs->ior, toreg);
 116
 117         __asm__ __volatile__  (
 118 "       mtsp    %4, %%sr1\n"
 119 "1:     ldbs    0(%%sr1,%3), %2\n"
 120 "2:     ldbs    1(%%sr1,%3), %0\n"
 121 "       depw    %2, 23, 24, %0\n"
 122 "3:     \n"
 123         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
 124         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
 125         : "+r" (val), "+r" (ret), "=&r" (temp1)
 126         : "r" (saddr), "r" (regs->isr) );
 127
 128         DPRINTF("val = " RFMT "\n", val);
 129
 130         if (toreg)
 131                 regs->gr[toreg] = val;
 132
 133         return ret;
 134 }
 135
 136 static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
 137 {
 138         unsigned long saddr = regs->ior;
 139         unsigned long val = 0, temp1, temp2;
 140         ASM_EXCEPTIONTABLE_VAR(ret);
 141
 142         DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n",
 143                 regs->isr, regs->ior, toreg);
 144
 145         __asm__ __volatile__  (
 146 "       zdep    %4,28,2,%2\n"           /* r19=(ofs&3)*8 */
 147 "       mtsp    %5, %%sr1\n"
 148 "       depw    %%r0,31,2,%4\n"
 149 "1:     ldw     0(%%sr1,%4),%0\n"
 150 "2:     ldw     4(%%sr1,%4),%3\n"
 151 "       subi    32,%2,%2\n"
 152 "       mtctl   %2,11\n"
 153 "       vshd    %0,%3,%0\n"
 154 "3:     \n"
 155         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
 156         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
 157         : "+r" (val), "+r" (ret), "=&r" (temp1), "=&r" (temp2)
 158         : "r" (saddr), "r" (regs->isr) );
 159
 160         DPRINTF("val = " RFMT "\n", val);
 161
 162         if (flop)
 163                 ((__u32*)(regs->fr))[toreg] = val;
 164         else if (toreg)
 165                 regs->gr[toreg] = val;
 166
 167         return ret;
 168 }
 169 static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
 170 {
 171         unsigned long saddr = regs->ior;
 172         unsigned long shift, temp1;
 173         __u64 val = 0;
 174         ASM_EXCEPTIONTABLE_VAR(ret);
 175
 176         DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n",
 177                 regs->isr, regs->ior, toreg);
 178
 179         if (!IS_ENABLED(CONFIG_64BIT) && !flop)
 180                 return ERR_NOTHANDLED;
 181
 182 #ifdef CONFIG_64BIT
 183         __asm__ __volatile__  (
 184 "       depd,z  %2,60,3,%3\n"           /* shift=(ofs&7)*8 */
 185 "       mtsp    %5, %%sr1\n"
 186 "       depd    %%r0,63,3,%2\n"
 187 "1:     ldd     0(%%sr1,%2),%0\n"
 188 "2:     ldd     8(%%sr1,%2),%4\n"
 189 "       subi    64,%3,%3\n"
 190 "       mtsar   %3\n"
 191 "       shrpd   %0,%4,%%sar,%0\n"
 192 "3:     \n"
 193         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
 194         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
 195         : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
 196         : "r" (regs->isr) );
 197 #else
 198         __asm__ __volatile__  (
 199 "       zdep    %2,29,2,%3\n"           /* shift=(ofs&3)*8 */
 200 "       mtsp    %5, %%sr1\n"
 201 "       dep     %%r0,31,2,%2\n"
 202 "1:     ldw     0(%%sr1,%2),%0\n"
 203 "2:     ldw     4(%%sr1,%2),%R0\n"
 204 "3:     ldw     8(%%sr1,%2),%4\n"
 205 "       subi    32,%3,%3\n"
 206 "       mtsar   %3\n"
 207 "       vshd    %0,%R0,%0\n"
 208 "       vshd    %R0,%4,%R0\n"
 209 "4:     \n"
 210         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 4b, "%1")
 211         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 4b, "%1")
 212         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b, "%1")
 213         : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
 214         : "r" (regs->isr) );
 215 #endif
 216
 217         DPRINTF("val = 0x%llx\n", val);
 218
 219         if (flop)
 220                 regs->fr[toreg] = val;
 221         else if (toreg)
 222                 regs->gr[toreg] = val;
 223
 224         return ret;
 225 }
 226
 227 static int emulate_sth(struct pt_regs *regs, int frreg)
 228 {
 229         unsigned long val = regs->gr[frreg], temp1;
 230         ASM_EXCEPTIONTABLE_VAR(ret);
 231
 232         if (!frreg)
 233                 val = 0;
 234
 235         DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg,
 236                 val, regs->isr, regs->ior);
 237
 238         __asm__ __volatile__ (
 239 "       mtsp %4, %%sr1\n"
 240 "       extrw,u %2, 23, 8, %1\n"
 241 "1:     stb %1, 0(%%sr1, %3)\n"
 242 "2:     stb %2, 1(%%sr1, %3)\n"
 243 "3:     \n"
 244         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
 245         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
 246         : "+r" (ret), "=&r" (temp1)
 247         : "r" (val), "r" (regs->ior), "r" (regs->isr) );
 248
 249         return ret;
 250 }
 251
 252 static int emulate_stw(struct pt_regs *regs, int frreg, int flop)
 253 {
 254         unsigned long val;
 255         ASM_EXCEPTIONTABLE_VAR(ret);
 256
 257         if (flop)
 258                 val = ((__u32*)(regs->fr))[frreg];
 259         else if (frreg)
 260                 val = regs->gr[frreg];
 261         else
 262                 val = 0;
 263
 264         DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg,
 265                 val, regs->isr, regs->ior);
 266
 267
 268         __asm__ __volatile__ (
 269 "       mtsp %3, %%sr1\n"
 270 "       zdep    %2, 28, 2, %%r19\n"
 271 "       dep     %%r0, 31, 2, %2\n"
 272 "       mtsar   %%r19\n"
 273 "       depwi,z -2, %%sar, 32, %%r19\n"
 274 "1:     ldw     0(%%sr1,%2),%%r20\n"
 275 "2:     ldw     4(%%sr1,%2),%%r21\n"
 276 "       vshd    %%r0, %1, %%r22\n"
 277 "       vshd    %1, %%r0, %%r1\n"
 278 "       and     %%r20, %%r19, %%r20\n"
 279 "       andcm   %%r21, %%r19, %%r21\n"
 280 "       or      %%r22, %%r20, %%r20\n"
 281 "       or      %%r1, %%r21, %%r21\n"
 282 "       stw     %%r20,0(%%sr1,%2)\n"
 283 "       stw     %%r21,4(%%sr1,%2)\n"
 284 "3:     \n"
 285         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
 286         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
 287         : "+r" (ret)
 288         : "r" (val), "r" (regs->ior), "r" (regs->isr)
 289         : "r19", "r20", "r21", "r22", "r1" );
 290
 291         return ret;
 292 }
 293 static int emulate_std(struct pt_regs *regs, int frreg, int flop)
 294 {
 295         __u64 val;
 296         ASM_EXCEPTIONTABLE_VAR(ret);
 297
 298         if (flop)
 299                 val = regs->fr[frreg];
 300         else if (frreg)
 301                 val = regs->gr[frreg];
 302         else
 303                 val = 0;
 304
 305         DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg,
 306                 val,  regs->isr, regs->ior);
 307
 308         if (!IS_ENABLED(CONFIG_64BIT) && !flop)
 309                 return ERR_NOTHANDLED;
 310
 311 #ifdef CONFIG_64BIT
 312         __asm__ __volatile__ (
 313 "       mtsp %3, %%sr1\n"
 314 "       depd,z  %2, 60, 3, %%r19\n"
 315 "       depd    %%r0, 63, 3, %2\n"
 316 "       mtsar   %%r19\n"
 317 "       depdi,z -2, %%sar, 64, %%r19\n"
 318 "1:     ldd     0(%%sr1,%2),%%r20\n"
 319 "2:     ldd     8(%%sr1,%2),%%r21\n"
 320 "       shrpd   %%r0, %1, %%sar, %%r22\n"
 321 "       shrpd   %1, %%r0, %%sar, %%r1\n"
 322 "       and     %%r20, %%r19, %%r20\n"
 323 "       andcm   %%r21, %%r19, %%r21\n"
 324 "       or      %%r22, %%r20, %%r20\n"
 325 "       or      %%r1, %%r21, %%r21\n"
 326 "3:     std     %%r20,0(%%sr1,%2)\n"
 327 "4:     std     %%r21,8(%%sr1,%2)\n"
 328 "5:     \n"
 329         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 5b, "%0")
 330         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 5b, "%0")
 331         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b, "%0")
 332         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 5b, "%0")
 333         : "+r" (ret)
 334         : "r" (val), "r" (regs->ior), "r" (regs->isr)
 335         : "r19", "r20", "r21", "r22", "r1" );
 336 #else
 337     {
 338         __asm__ __volatile__ (
 339 "       mtsp    %3, %%sr1\n"
 340 "       zdep    %R1, 29, 2, %%r19\n"
 341 "       dep     %%r0, 31, 2, %2\n"
 342 "       mtsar   %%r19\n"
 343 "       zvdepi  -2, 32, %%r19\n"
 344 "1:     ldw     0(%%sr1,%2),%%r20\n"
 345 "2:     ldw     8(%%sr1,%2),%%r21\n"
 346 "       vshd    %1, %R1, %%r1\n"
 347 "       vshd    %%r0, %1, %1\n"
 348 "       vshd    %R1, %%r0, %R1\n"
 349 "       and     %%r20, %%r19, %%r20\n"
 350 "       andcm   %%r21, %%r19, %%r21\n"
 351 "       or      %1, %%r20, %1\n"
 352 "       or      %R1, %%r21, %R1\n"
 353 "3:     stw     %1,0(%%sr1,%2)\n"
 354 "4:     stw     %%r1,4(%%sr1,%2)\n"
 355 "5:     stw     %R1,8(%%sr1,%2)\n"
 356 "6:     \n"
 357         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 6b, "%0")
 358         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 6b, "%0")
 359         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b, "%0")
 360         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 6b, "%0")
 361         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(5b, 6b, "%0")
 362         : "+r" (ret)
 363         : "r" (val), "r" (regs->ior), "r" (regs->isr)
 364         : "r19", "r20", "r21", "r1" );
 365     }
 366 #endif
 367
 368         return ret;
 369 }
 370
 371 void handle_unaligned(struct pt_regs *regs)
 372 {
 373         static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
 374         unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;
 375         int modify = 0;
 376         int ret = ERR_NOTHANDLED;
 377
 378         __inc_irq_stat(irq_unaligned_count);
 379
 380         /* log a message with pacing */
 381         if (user_mode(regs)) {
 382                 if (current->thread.flags & PARISC_UAC_SIGBUS) {
 383                         goto force_sigbus;
 384                 }
 385
 386                 if (!(current->thread.flags & PARISC_UAC_NOPRINT) &&
 387                         __ratelimit(&ratelimit)) {
 388                         printk(KERN_WARNING "%s(%d): unaligned access to " RFMT
 389                                 " at ip " RFMT " (iir " RFMT ")\n",
 390                                 current->comm, task_pid_nr(current), regs->ior,
 391                                 regs->iaoq[0], regs->iir);
 392 #ifdef DEBUG_UNALIGNED
 393                         show_regs(regs);
 394 #endif
 395                 }
 396
 397                 if (!unaligned_enabled)
 398                         goto force_sigbus;
 399         }
 400
 401         /* handle modification - OK, it's ugly, see the instruction manual */
 402         switch (MAJOR_OP(regs->iir))
 403         {
 404         case 0x03:
 405         case 0x09:
 406         case 0x0b:
 407                 if (regs->iir&0x20)
 408                 {
 409                         modify = 1;
 410                         if (regs->iir&0x1000)           /* short loads */
 411                                 if (regs->iir&0x200)
 412                                         newbase += IM5_3(regs->iir);
 413                                 else
 414                                         newbase += IM5_2(regs->iir);
 415                         else if (regs->iir&0x2000)      /* scaled indexed */
 416                         {
 417                                 int shift=0;
 418                                 switch (regs->iir & OPCODE1_MASK)
 419                                 {
 420                                 case OPCODE_LDH_I:
 421                                         shift= 1; break;
 422                                 case OPCODE_LDW_I:
 423                                         shift= 2; break;
 424                                 case OPCODE_LDD_I:
 425                                 case OPCODE_LDDA_I:
 426                                         shift= 3; break;
 427                                 }
 428                                 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;
 429                         } else                          /* simple indexed */
 430                                 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);
 431                 }
 432                 break;
 433         case 0x13:
 434         case 0x1b:
 435                 modify = 1;
 436                 newbase += IM14(regs->iir);
 437                 break;
 438         case 0x14:
 439         case 0x1c:
 440                 if (regs->iir&8)
 441                 {
 442                         modify = 1;
 443                         newbase += IM14(regs->iir&~0xe);
 444                 }
 445                 break;
 446         case 0x16:
 447         case 0x1e:
 448                 modify = 1;
 449                 newbase += IM14(regs->iir&6);
 450                 break;
 451         case 0x17:
 452         case 0x1f:
 453                 if (regs->iir&4)
 454                 {
 455                         modify = 1;
 456                         newbase += IM14(regs->iir&~4);
 457                 }
 458                 break;
 459         }
 460
 461         /* TODO: make this cleaner... */
 462         switch (regs->iir & OPCODE1_MASK)
 463         {
 464         case OPCODE_LDH_I:
 465         case OPCODE_LDH_S:
 466                 ret = emulate_ldh(regs, R3(regs->iir));
 467                 break;
 468
 469         case OPCODE_LDW_I:
 470         case OPCODE_LDWA_I:
 471         case OPCODE_LDW_S:
 472         case OPCODE_LDWA_S:
 473                 ret = emulate_ldw(regs, R3(regs->iir), 0);
 474                 break;
 475
 476         case OPCODE_STH:
 477                 ret = emulate_sth(regs, R2(regs->iir));
 478                 break;
 479
 480         case OPCODE_STW:
 481         case OPCODE_STWA:
 482                 ret = emulate_stw(regs, R2(regs->iir), 0);
 483                 break;
 484
 485 #ifdef CONFIG_64BIT
 486         case OPCODE_LDD_I:
 487         case OPCODE_LDDA_I:
 488         case OPCODE_LDD_S:
 489         case OPCODE_LDDA_S:
 490                 ret = emulate_ldd(regs, R3(regs->iir), 0);
 491                 break;
 492
 493         case OPCODE_STD:
 494         case OPCODE_STDA:
 495                 ret = emulate_std(regs, R2(regs->iir), 0);
 496                 break;
 497 #endif
 498
 499         case OPCODE_FLDWX:
 500         case OPCODE_FLDWS:
 501         case OPCODE_FLDWXR:
 502         case OPCODE_FLDWSR:
 503                 ret = emulate_ldw(regs, FR3(regs->iir), 1);
 504                 break;
 505
 506         case OPCODE_FLDDX:
 507         case OPCODE_FLDDS:
 508                 ret = emulate_ldd(regs, R3(regs->iir), 1);
 509                 break;
 510
 511         case OPCODE_FSTWX:
 512         case OPCODE_FSTWS:
 513         case OPCODE_FSTWXR:
 514         case OPCODE_FSTWSR:
 515                 ret = emulate_stw(regs, FR3(regs->iir), 1);
 516                 break;
 517
 518         case OPCODE_FSTDX:
 519         case OPCODE_FSTDS:
 520                 ret = emulate_std(regs, R3(regs->iir), 1);
 521                 break;
 522
 523         case OPCODE_LDCD_I:
 524         case OPCODE_LDCW_I:
 525         case OPCODE_LDCD_S:
 526         case OPCODE_LDCW_S:
 527                 ret = ERR_NOTHANDLED;   /* "undefined", but lets kill them. */
 528                 break;
 529         }
 530         switch (regs->iir & OPCODE2_MASK)
 531         {
 532         case OPCODE_FLDD_L:
 533                 ret = emulate_ldd(regs,R2(regs->iir),1);
 534                 break;
 535         case OPCODE_FSTD_L:
 536                 ret = emulate_std(regs, R2(regs->iir),1);
 537                 break;
 538 #ifdef CONFIG_64BIT
 539         case OPCODE_LDD_L:
 540                 ret = emulate_ldd(regs, R2(regs->iir),0);
 541                 break;
 542         case OPCODE_STD_L:
 543                 ret = emulate_std(regs, R2(regs->iir),0);
 544                 break;
 545 #endif
 546         }
 547         switch (regs->iir & OPCODE3_MASK)
 548         {
 549         case OPCODE_FLDW_L:
 550                 ret = emulate_ldw(regs, R2(regs->iir), 1);
 551                 break;
 552         case OPCODE_LDW_M:
 553                 ret = emulate_ldw(regs, R2(regs->iir), 0);
 554                 break;
 555
 556         case OPCODE_FSTW_L:
 557                 ret = emulate_stw(regs, R2(regs->iir),1);
 558                 break;
 559         case OPCODE_STW_M:
 560                 ret = emulate_stw(regs, R2(regs->iir),0);
 561                 break;
 562         }
 563         switch (regs->iir & OPCODE4_MASK)
 564         {
 565         case OPCODE_LDH_L:
 566                 ret = emulate_ldh(regs, R2(regs->iir));
 567                 break;
 568         case OPCODE_LDW_L:
 569         case OPCODE_LDWM:
 570                 ret = emulate_ldw(regs, R2(regs->iir),0);
 571                 break;
 572         case OPCODE_STH_L:
 573                 ret = emulate_sth(regs, R2(regs->iir));
 574                 break;
 575         case OPCODE_STW_L:
 576         case OPCODE_STWM:
 577                 ret = emulate_stw(regs, R2(regs->iir),0);
 578                 break;
 579         }
 580
 581         if (ret == 0 && modify && R1(regs->iir))
 582                 regs->gr[R1(regs->iir)] = newbase;
 583
 584
 585         if (ret == ERR_NOTHANDLED)
 586                 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);
 587
 588         DPRINTF("ret = %d\n", ret);
 589
 590         if (ret)
 591         {
 592                 /*
 593                  * The unaligned handler failed.
 594                  * If we were called by __get_user() or __put_user() jump
 595                  * to it's exception fixup handler instead of crashing.
 596                  */
 597                 if (!user_mode(regs) && fixup_exception(regs))
 598                         return;
 599
 600                 printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);
 601                 die_if_kernel("Unaligned data reference", regs, 28);
 602
 603                 if (ret == -EFAULT)
 604                 {
 605                         force_sig_fault(SIGSEGV, SEGV_MAPERR,
 606                                         (void __user *)regs->ior);
 607                 }
 608                 else
 609                 {
 610 force_sigbus:
 611                         /* couldn't handle it ... */
 612                         force_sig_fault(SIGBUS, BUS_ADRALN,
 613                                         (void __user *)regs->ior);
 614                 }
 615
 616                 return;
 617         }
 618
 619         /* else we handled it, let life go on. */
 620         regs->gr[0]|=PSW_N;
 621 }
 622
 623 /*
 624  * NB: check_unaligned() is only used for PCXS processors right
 625  * now, so we only check for PA1.1 encodings at this point.
 626  */
 627
 628 int
 629 check_unaligned(struct pt_regs *regs)
 630 {
 631         unsigned long align_mask;
 632
 633         /* Get alignment mask */
 634
 635         align_mask = 0UL;
 636         switch (regs->iir & OPCODE1_MASK) {
 637
 638         case OPCODE_LDH_I:
 639         case OPCODE_LDH_S:
 640         case OPCODE_STH:
 641                 align_mask = 1UL;
 642                 break;
 643
 644         case OPCODE_LDW_I:
 645         case OPCODE_LDWA_I:
 646         case OPCODE_LDW_S:
 647         case OPCODE_LDWA_S:
 648         case OPCODE_STW:
 649         case OPCODE_STWA:
 650                 align_mask = 3UL;
 651                 break;
 652
 653         default:
 654                 switch (regs->iir & OPCODE4_MASK) {
 655                 case OPCODE_LDH_L:
 656                 case OPCODE_STH_L:
 657                         align_mask = 1UL;
 658                         break;
 659                 case OPCODE_LDW_L:
 660                 case OPCODE_LDWM:
 661                 case OPCODE_STW_L:
 662                 case OPCODE_STWM:
 663                         align_mask = 3UL;
 664                         break;
 665                 }
 666                 break;
 667         }
 668
 669         return (int)(regs->ior & align_mask);
 670 }
 671