arch/parisc/kernel/unaligned.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *    Unaligned memory access handler
   4  *
   5  *    Copyright (C) 2001 Randolph Chung <tausq@debian.org>
   6  *    Copyright (C) 2022 Helge Deller <deller@gmx.de>
   7  *    Significantly tweaked by LaMont Jones <lamont@debian.org>
   8  */
   9
  10 #include <linux/sched/signal.h>
  11 #include <linux/signal.h>
  12 #include <linux/ratelimit.h>
  13 #include <linux/uaccess.h>
  14 #include <asm/hardirq.h>
  15 #include <asm/traps.h>
  16
  17 /* #define DEBUG_UNALIGNED 1 */
  18
  19 #ifdef DEBUG_UNALIGNED
  20 #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
  21 #else
  22 #define DPRINTF(fmt, args...)
  23 #endif
  24
  25 #define RFMT "%#08lx"
  26
  27 /* 1111 1100 0000 0000 0001 0011 1100 0000 */
  28 #define OPCODE1(a,b,c)  ((a)<<26|(b)<<12|(c)<<6)
  29 #define OPCODE2(a,b)    ((a)<<26|(b)<<1)
  30 #define OPCODE3(a,b)    ((a)<<26|(b)<<2)
  31 #define OPCODE4(a)      ((a)<<26)
  32 #define OPCODE1_MASK    OPCODE1(0x3f,1,0xf)
  33 #define OPCODE2_MASK    OPCODE2(0x3f,1)
  34 #define OPCODE3_MASK    OPCODE3(0x3f,1)
  35 #define OPCODE4_MASK    OPCODE4(0x3f)
  36
  37 /* skip LDB - never unaligned (index) */
  38 #define OPCODE_LDH_I    OPCODE1(0x03,0,0x1)
  39 #define OPCODE_LDW_I    OPCODE1(0x03,0,0x2)
  40 #define OPCODE_LDD_I    OPCODE1(0x03,0,0x3)
  41 #define OPCODE_LDDA_I   OPCODE1(0x03,0,0x4)
  42 #define OPCODE_LDCD_I   OPCODE1(0x03,0,0x5)
  43 #define OPCODE_LDWA_I   OPCODE1(0x03,0,0x6)
  44 #define OPCODE_LDCW_I   OPCODE1(0x03,0,0x7)
  45 /* skip LDB - never unaligned (short) */
  46 #define OPCODE_LDH_S    OPCODE1(0x03,1,0x1)
  47 #define OPCODE_LDW_S    OPCODE1(0x03,1,0x2)
  48 #define OPCODE_LDD_S    OPCODE1(0x03,1,0x3)
  49 #define OPCODE_LDDA_S   OPCODE1(0x03,1,0x4)
  50 #define OPCODE_LDCD_S   OPCODE1(0x03,1,0x5)
  51 #define OPCODE_LDWA_S   OPCODE1(0x03,1,0x6)
  52 #define OPCODE_LDCW_S   OPCODE1(0x03,1,0x7)
  53 /* skip STB - never unaligned */
  54 #define OPCODE_STH      OPCODE1(0x03,1,0x9)
  55 #define OPCODE_STW      OPCODE1(0x03,1,0xa)
  56 #define OPCODE_STD      OPCODE1(0x03,1,0xb)
  57 /* skip STBY - never unaligned */
  58 /* skip STDBY - never unaligned */
  59 #define OPCODE_STWA     OPCODE1(0x03,1,0xe)
  60 #define OPCODE_STDA     OPCODE1(0x03,1,0xf)
  61
  62 #define OPCODE_FLDWX    OPCODE1(0x09,0,0x0)
  63 #define OPCODE_FLDWXR   OPCODE1(0x09,0,0x1)
  64 #define OPCODE_FSTWX    OPCODE1(0x09,0,0x8)
  65 #define OPCODE_FSTWXR   OPCODE1(0x09,0,0x9)
  66 #define OPCODE_FLDWS    OPCODE1(0x09,1,0x0)
  67 #define OPCODE_FLDWSR   OPCODE1(0x09,1,0x1)
  68 #define OPCODE_FSTWS    OPCODE1(0x09,1,0x8)
  69 #define OPCODE_FSTWSR   OPCODE1(0x09,1,0x9)
  70 #define OPCODE_FLDDX    OPCODE1(0x0b,0,0x0)
  71 #define OPCODE_FSTDX    OPCODE1(0x0b,0,0x8)
  72 #define OPCODE_FLDDS    OPCODE1(0x0b,1,0x0)
  73 #define OPCODE_FSTDS    OPCODE1(0x0b,1,0x8)
  74
  75 #define OPCODE_LDD_L    OPCODE2(0x14,0)
  76 #define OPCODE_FLDD_L   OPCODE2(0x14,1)
  77 #define OPCODE_STD_L    OPCODE2(0x1c,0)
  78 #define OPCODE_FSTD_L   OPCODE2(0x1c,1)
  79
  80 #define OPCODE_LDW_M    OPCODE3(0x17,1)
  81 #define OPCODE_FLDW_L   OPCODE3(0x17,0)
  82 #define OPCODE_FSTW_L   OPCODE3(0x1f,0)
  83 #define OPCODE_STW_M    OPCODE3(0x1f,1)
  84
  85 #define OPCODE_LDH_L    OPCODE4(0x11)
  86 #define OPCODE_LDW_L    OPCODE4(0x12)
  87 #define OPCODE_LDWM     OPCODE4(0x13)
  88 #define OPCODE_STH_L    OPCODE4(0x19)
  89 #define OPCODE_STW_L    OPCODE4(0x1A)
  90 #define OPCODE_STWM     OPCODE4(0x1B)
  91
  92 #define MAJOR_OP(i) (((i)>>26)&0x3f)
  93 #define R1(i) (((i)>>21)&0x1f)
  94 #define R2(i) (((i)>>16)&0x1f)
  95 #define R3(i) ((i)&0x1f)
  96 #define FR3(i) ((((i)&0x1f)<<1)|(((i)>>6)&1))
  97 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
  98 #define IM5_2(i) IM((i)>>16,5)
  99 #define IM5_3(i) IM((i),5)
 100 #define IM14(i) IM((i),14)
 101
 102 #define ERR_NOTHANDLED  -1
 103
 104 int unaligned_enabled __read_mostly = 1;
 105
 106 static int emulate_ldh(struct pt_regs *regs, int toreg)
 107 {
 108         unsigned long saddr = regs->ior;
 109         unsigned long val = 0, temp1;
 110         ASM_EXCEPTIONTABLE_VAR(ret);
 111
 112         DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n",
 113                 regs->isr, regs->ior, toreg);
 114
 115         __asm__ __volatile__  (
 116 "       mtsp    %4, %%sr1\n"
 117 "1:     ldbs    0(%%sr1,%3), %2\n"
 118 "2:     ldbs    1(%%sr1,%3), %0\n"
 119 "       depw    %2, 23, 24, %0\n"
 120 "3:     \n"
 121         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
 122         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
 123         : "+r" (val), "+r" (ret), "=&r" (temp1)
 124         : "r" (saddr), "r" (regs->isr) );
 125
 126         DPRINTF("val = " RFMT "\n", val);
 127
 128         if (toreg)
 129                 regs->gr[toreg] = val;
 130
 131         return ret;
 132 }
 133
 134 static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
 135 {
 136         unsigned long saddr = regs->ior;
 137         unsigned long val = 0, temp1, temp2;
 138         ASM_EXCEPTIONTABLE_VAR(ret);
 139
 140         DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n",
 141                 regs->isr, regs->ior, toreg);
 142
 143         __asm__ __volatile__  (
 144 "       zdep    %4,28,2,%2\n"           /* r19=(ofs&3)*8 */
 145 "       mtsp    %5, %%sr1\n"
 146 "       depw    %%r0,31,2,%4\n"
 147 "1:     ldw     0(%%sr1,%4),%0\n"
 148 "2:     ldw     4(%%sr1,%4),%3\n"
 149 "       subi    32,%2,%2\n"
 150 "       mtctl   %2,11\n"
 151 "       vshd    %0,%3,%0\n"
 152 "3:     \n"
 153         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
 154         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
 155         : "+r" (val), "+r" (ret), "=&r" (temp1), "=&r" (temp2)
 156         : "r" (saddr), "r" (regs->isr) );
 157
 158         DPRINTF("val = " RFMT "\n", val);
 159
 160         if (flop)
 161                 ((__u32*)(regs->fr))[toreg] = val;
 162         else if (toreg)
 163                 regs->gr[toreg] = val;
 164
 165         return ret;
 166 }
 167 static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
 168 {
 169         unsigned long saddr = regs->ior;
 170         unsigned long shift, temp1;
 171         __u64 val = 0;
 172         ASM_EXCEPTIONTABLE_VAR(ret);
 173
 174         DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n",
 175                 regs->isr, regs->ior, toreg);
 176
 177         if (!IS_ENABLED(CONFIG_64BIT) && !flop)
 178                 return ERR_NOTHANDLED;
 179
 180 #ifdef CONFIG_64BIT
 181         __asm__ __volatile__  (
 182 "       depd,z  %2,60,3,%3\n"           /* shift=(ofs&7)*8 */
 183 "       mtsp    %5, %%sr1\n"
 184 "       depd    %%r0,63,3,%2\n"
 185 "1:     ldd     0(%%sr1,%2),%0\n"
 186 "2:     ldd     8(%%sr1,%2),%4\n"
 187 "       subi    64,%3,%3\n"
 188 "       mtsar   %3\n"
 189 "       shrpd   %0,%4,%%sar,%0\n"
 190 "3:     \n"
 191         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
 192         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
 193         : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
 194         : "r" (regs->isr) );
 195 #else
 196         __asm__ __volatile__  (
 197 "       zdep    %2,29,2,%3\n"           /* shift=(ofs&3)*8 */
 198 "       mtsp    %5, %%sr1\n"
 199 "       dep     %%r0,31,2,%2\n"
 200 "1:     ldw     0(%%sr1,%2),%0\n"
 201 "2:     ldw     4(%%sr1,%2),%R0\n"
 202 "3:     ldw     8(%%sr1,%2),%4\n"
 203 "       subi    32,%3,%3\n"
 204 "       mtsar   %3\n"
 205 "       vshd    %0,%R0,%0\n"
 206 "       vshd    %R0,%4,%R0\n"
 207 "4:     \n"
 208         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 4b, "%1")
 209         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 4b, "%1")
 210         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b, "%1")
 211         : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
 212         : "r" (regs->isr) );
 213 #endif
 214
 215         DPRINTF("val = 0x%llx\n", val);
 216
 217         if (flop)
 218                 regs->fr[toreg] = val;
 219         else if (toreg)
 220                 regs->gr[toreg] = val;
 221
 222         return ret;
 223 }
 224
 225 static int emulate_sth(struct pt_regs *regs, int frreg)
 226 {
 227         unsigned long val = regs->gr[frreg], temp1;
 228         ASM_EXCEPTIONTABLE_VAR(ret);
 229
 230         if (!frreg)
 231                 val = 0;
 232
 233         DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg,
 234                 val, regs->isr, regs->ior);
 235
 236         __asm__ __volatile__ (
 237 "       mtsp %4, %%sr1\n"
 238 "       extrw,u %2, 23, 8, %1\n"
 239 "1:     stb %1, 0(%%sr1, %3)\n"
 240 "2:     stb %2, 1(%%sr1, %3)\n"
 241 "3:     \n"
 242         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
 243         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
 244         : "+r" (ret), "=&r" (temp1)
 245         : "r" (val), "r" (regs->ior), "r" (regs->isr) );
 246
 247         return ret;
 248 }
 249
 250 static int emulate_stw(struct pt_regs *regs, int frreg, int flop)
 251 {
 252         unsigned long val;
 253         ASM_EXCEPTIONTABLE_VAR(ret);
 254
 255         if (flop)
 256                 val = ((__u32*)(regs->fr))[frreg];
 257         else if (frreg)
 258                 val = regs->gr[frreg];
 259         else
 260                 val = 0;
 261
 262         DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg,
 263                 val, regs->isr, regs->ior);
 264
 265
 266         __asm__ __volatile__ (
 267 "       mtsp %3, %%sr1\n"
 268 "       zdep    %2, 28, 2, %%r19\n"
 269 "       dep     %%r0, 31, 2, %2\n"
 270 "       mtsar   %%r19\n"
 271 "       depwi,z -2, %%sar, 32, %%r19\n"
 272 "1:     ldw     0(%%sr1,%2),%%r20\n"
 273 "2:     ldw     4(%%sr1,%2),%%r21\n"
 274 "       vshd    %%r0, %1, %%r22\n"
 275 "       vshd    %1, %%r0, %%r1\n"
 276 "       and     %%r20, %%r19, %%r20\n"
 277 "       andcm   %%r21, %%r19, %%r21\n"
 278 "       or      %%r22, %%r20, %%r20\n"
 279 "       or      %%r1, %%r21, %%r21\n"
 280 "       stw     %%r20,0(%%sr1,%2)\n"
 281 "       stw     %%r21,4(%%sr1,%2)\n"
 282 "3:     \n"
 283         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
 284         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
 285         : "+r" (ret)
 286         : "r" (val), "r" (regs->ior), "r" (regs->isr)
 287         : "r19", "r20", "r21", "r22", "r1" );
 288
 289         return ret;
 290 }
 291 static int emulate_std(struct pt_regs *regs, int frreg, int flop)
 292 {
 293         __u64 val;
 294         ASM_EXCEPTIONTABLE_VAR(ret);
 295
 296         if (flop)
 297                 val = regs->fr[frreg];
 298         else if (frreg)
 299                 val = regs->gr[frreg];
 300         else
 301                 val = 0;
 302
 303         DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg,
 304                 val,  regs->isr, regs->ior);
 305
 306         if (!IS_ENABLED(CONFIG_64BIT) && !flop)
 307                 return ERR_NOTHANDLED;
 308
 309 #ifdef CONFIG_64BIT
 310         __asm__ __volatile__ (
 311 "       mtsp %3, %%sr1\n"
 312 "       depd,z  %2, 60, 3, %%r19\n"
 313 "       depd    %%r0, 63, 3, %2\n"
 314 "       mtsar   %%r19\n"
 315 "       depdi,z -2, %%sar, 64, %%r19\n"
 316 "1:     ldd     0(%%sr1,%2),%%r20\n"
 317 "2:     ldd     8(%%sr1,%2),%%r21\n"
 318 "       shrpd   %%r0, %1, %%sar, %%r22\n"
 319 "       shrpd   %1, %%r0, %%sar, %%r1\n"
 320 "       and     %%r20, %%r19, %%r20\n"
 321 "       andcm   %%r21, %%r19, %%r21\n"
 322 "       or      %%r22, %%r20, %%r20\n"
 323 "       or      %%r1, %%r21, %%r21\n"
 324 "3:     std     %%r20,0(%%sr1,%2)\n"
 325 "4:     std     %%r21,8(%%sr1,%2)\n"
 326 "5:     \n"
 327         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 5b, "%0")
 328         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 5b, "%0")
 329         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b, "%0")
 330         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 5b, "%0")
 331         : "+r" (ret)
 332         : "r" (val), "r" (regs->ior), "r" (regs->isr)
 333         : "r19", "r20", "r21", "r22", "r1" );
 334 #else
 335     {
 336         unsigned long valh=(val>>32),vall=(val&0xffffffffl);
 337         __asm__ __volatile__ (
 338 "       mtsp    %4, %%sr1\n"
 339 "       zdep    %2, 29, 2, %%r19\n"
 340 "       dep     %%r0, 31, 2, %3\n"
 341 "       mtsar   %%r19\n"
 342 "       zvdepi  -2, 32, %%r19\n"
 343 "1:     ldw     0(%%sr1,%3),%%r20\n"
 344 "2:     ldw     8(%%sr1,%3),%%r21\n"
 345 "       vshd    %1, %2, %%r1\n"
 346 "       vshd    %%r0, %1, %1\n"
 347 "       vshd    %2, %%r0, %2\n"
 348 "       and     %%r20, %%r19, %%r20\n"
 349 "       andcm   %%r21, %%r19, %%r21\n"
 350 "       or      %1, %%r20, %1\n"
 351 "       or      %2, %%r21, %2\n"
 352 "3:     stw     %1,0(%%sr1,%3)\n"
 353 "4:     stw     %%r1,4(%%sr1,%3)\n"
 354 "5:     stw     %2,8(%%sr1,%3)\n"
 355 "6:     \n"
 356         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 6b, "%0")
 357         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 6b, "%0")
 358         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b, "%0")
 359         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 6b, "%0")
 360         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(5b, 6b, "%0")
 361         : "+r" (ret)
 362         : "r" (valh), "r" (vall), "r" (regs->ior), "r" (regs->isr)
 363         : "r19", "r20", "r21", "r1" );
 364     }
 365 #endif
 366
 367         return ret;
 368 }
 369
 370 void handle_unaligned(struct pt_regs *regs)
 371 {
 372         static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
 373         unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;
 374         int modify = 0;
 375         int ret = ERR_NOTHANDLED;
 376
 377         __inc_irq_stat(irq_unaligned_count);
 378
 379         /* log a message with pacing */
 380         if (user_mode(regs)) {
 381                 if (current->thread.flags & PARISC_UAC_SIGBUS) {
 382                         goto force_sigbus;
 383                 }
 384
 385                 if (!(current->thread.flags & PARISC_UAC_NOPRINT) &&
 386                         __ratelimit(&ratelimit)) {
 387                         printk(KERN_WARNING "%s(%d): unaligned access to " RFMT
 388                                 " at ip " RFMT " (iir " RFMT ")\n",
 389                                 current->comm, task_pid_nr(current), regs->ior,
 390                                 regs->iaoq[0], regs->iir);
 391 #ifdef DEBUG_UNALIGNED
 392                         show_regs(regs);
 393 #endif
 394                 }
 395
 396                 if (!unaligned_enabled)
 397                         goto force_sigbus;
 398         }
 399
 400         /* handle modification - OK, it's ugly, see the instruction manual */
 401         switch (MAJOR_OP(regs->iir))
 402         {
 403         case 0x03:
 404         case 0x09:
 405         case 0x0b:
 406                 if (regs->iir&0x20)
 407                 {
 408                         modify = 1;
 409                         if (regs->iir&0x1000)           /* short loads */
 410                                 if (regs->iir&0x200)
 411                                         newbase += IM5_3(regs->iir);
 412                                 else
 413                                         newbase += IM5_2(regs->iir);
 414                         else if (regs->iir&0x2000)      /* scaled indexed */
 415                         {
 416                                 int shift=0;
 417                                 switch (regs->iir & OPCODE1_MASK)
 418                                 {
 419                                 case OPCODE_LDH_I:
 420                                         shift= 1; break;
 421                                 case OPCODE_LDW_I:
 422                                         shift= 2; break;
 423                                 case OPCODE_LDD_I:
 424                                 case OPCODE_LDDA_I:
 425                                         shift= 3; break;
 426                                 }
 427                                 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;
 428                         } else                          /* simple indexed */
 429                                 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);
 430                 }
 431                 break;
 432         case 0x13:
 433         case 0x1b:
 434                 modify = 1;
 435                 newbase += IM14(regs->iir);
 436                 break;
 437         case 0x14:
 438         case 0x1c:
 439                 if (regs->iir&8)
 440                 {
 441                         modify = 1;
 442                         newbase += IM14(regs->iir&~0xe);
 443                 }
 444                 break;
 445         case 0x16:
 446         case 0x1e:
 447                 modify = 1;
 448                 newbase += IM14(regs->iir&6);
 449                 break;
 450         case 0x17:
 451         case 0x1f:
 452                 if (regs->iir&4)
 453                 {
 454                         modify = 1;
 455                         newbase += IM14(regs->iir&~4);
 456                 }
 457                 break;
 458         }
 459
 460         /* TODO: make this cleaner... */
 461         switch (regs->iir & OPCODE1_MASK)
 462         {
 463         case OPCODE_LDH_I:
 464         case OPCODE_LDH_S:
 465                 ret = emulate_ldh(regs, R3(regs->iir));
 466                 break;
 467
 468         case OPCODE_LDW_I:
 469         case OPCODE_LDWA_I:
 470         case OPCODE_LDW_S:
 471         case OPCODE_LDWA_S:
 472                 ret = emulate_ldw(regs, R3(regs->iir),0);
 473                 break;
 474
 475         case OPCODE_STH:
 476                 ret = emulate_sth(regs, R2(regs->iir));
 477                 break;
 478
 479         case OPCODE_STW:
 480         case OPCODE_STWA:
 481                 ret = emulate_stw(regs, R2(regs->iir),0);
 482                 break;
 483
 484 #ifdef CONFIG_64BIT
 485         case OPCODE_LDD_I:
 486         case OPCODE_LDDA_I:
 487         case OPCODE_LDD_S:
 488         case OPCODE_LDDA_S:
 489                 ret = emulate_ldd(regs, R3(regs->iir),0);
 490                 break;
 491
 492         case OPCODE_STD:
 493         case OPCODE_STDA:
 494                 ret = emulate_std(regs, R2(regs->iir),0);
 495                 break;
 496 #endif
 497
 498         case OPCODE_FLDWX:
 499         case OPCODE_FLDWS:
 500         case OPCODE_FLDWXR:
 501         case OPCODE_FLDWSR:
 502                 ret = emulate_ldw(regs,FR3(regs->iir),1);
 503                 break;
 504
 505         case OPCODE_FLDDX:
 506         case OPCODE_FLDDS:
 507                 ret = emulate_ldd(regs,R3(regs->iir),1);
 508                 break;
 509
 510         case OPCODE_FSTWX:
 511         case OPCODE_FSTWS:
 512         case OPCODE_FSTWXR:
 513         case OPCODE_FSTWSR:
 514                 ret = emulate_stw(regs,FR3(regs->iir),1);
 515                 break;
 516
 517         case OPCODE_FSTDX:
 518         case OPCODE_FSTDS:
 519                 ret = emulate_std(regs,R3(regs->iir),1);
 520                 break;
 521
 522         case OPCODE_LDCD_I:
 523         case OPCODE_LDCW_I:
 524         case OPCODE_LDCD_S:
 525         case OPCODE_LDCW_S:
 526                 ret = ERR_NOTHANDLED;   /* "undefined", but lets kill them. */
 527                 break;
 528         }
 529         switch (regs->iir & OPCODE2_MASK)
 530         {
 531         case OPCODE_FLDD_L:
 532                 ret = emulate_ldd(regs,R2(regs->iir),1);
 533                 break;
 534         case OPCODE_FSTD_L:
 535                 ret = emulate_std(regs, R2(regs->iir),1);
 536                 break;
 537 #ifdef CONFIG_64BIT
 538         case OPCODE_LDD_L:
 539                 ret = emulate_ldd(regs, R2(regs->iir),0);
 540                 break;
 541         case OPCODE_STD_L:
 542                 ret = emulate_std(regs, R2(regs->iir),0);
 543                 break;
 544 #endif
 545         }
 546         switch (regs->iir & OPCODE3_MASK)
 547         {
 548         case OPCODE_FLDW_L:
 549                 ret = emulate_ldw(regs, R2(regs->iir), 1);
 550                 break;
 551         case OPCODE_LDW_M:
 552                 ret = emulate_ldw(regs, R2(regs->iir), 0);
 553                 break;
 554
 555         case OPCODE_FSTW_L:
 556                 ret = emulate_stw(regs, R2(regs->iir),1);
 557                 break;
 558         case OPCODE_STW_M:
 559                 ret = emulate_stw(regs, R2(regs->iir),0);
 560                 break;
 561         }
 562         switch (regs->iir & OPCODE4_MASK)
 563         {
 564         case OPCODE_LDH_L:
 565                 ret = emulate_ldh(regs, R2(regs->iir));
 566                 break;
 567         case OPCODE_LDW_L:
 568         case OPCODE_LDWM:
 569                 ret = emulate_ldw(regs, R2(regs->iir),0);
 570                 break;
 571         case OPCODE_STH_L:
 572                 ret = emulate_sth(regs, R2(regs->iir));
 573                 break;
 574         case OPCODE_STW_L:
 575         case OPCODE_STWM:
 576                 ret = emulate_stw(regs, R2(regs->iir),0);
 577                 break;
 578         }
 579
 580         if (ret == 0 && modify && R1(regs->iir))
 581                 regs->gr[R1(regs->iir)] = newbase;
 582
 583
 584         if (ret == ERR_NOTHANDLED)
 585                 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);
 586
 587         DPRINTF("ret = %d\n", ret);
 588
 589         if (ret)
 590         {
 591                 /*
 592                  * The unaligned handler failed.
 593                  * If we were called by __get_user() or __put_user() jump
 594                  * to it's exception fixup handler instead of crashing.
 595                  */
 596                 if (!user_mode(regs) && fixup_exception(regs))
 597                         return;
 598
 599                 printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);
 600                 die_if_kernel("Unaligned data reference", regs, 28);
 601
 602                 if (ret == -EFAULT)
 603                 {
 604                         force_sig_fault(SIGSEGV, SEGV_MAPERR,
 605                                         (void __user *)regs->ior);
 606                 }
 607                 else
 608                 {
 609 force_sigbus:
 610                         /* couldn't handle it ... */
 611                         force_sig_fault(SIGBUS, BUS_ADRALN,
 612                                         (void __user *)regs->ior);
 613                 }
 614
 615                 return;
 616         }
 617
 618         /* else we handled it, let life go on. */
 619         regs->gr[0]|=PSW_N;
 620 }
 621
 622 /*
 623  * NB: check_unaligned() is only used for PCXS processors right
 624  * now, so we only check for PA1.1 encodings at this point.
 625  */
 626
 627 int
 628 check_unaligned(struct pt_regs *regs)
 629 {
 630         unsigned long align_mask;
 631
 632         /* Get alignment mask */
 633
 634         align_mask = 0UL;
 635         switch (regs->iir & OPCODE1_MASK) {
 636
 637         case OPCODE_LDH_I:
 638         case OPCODE_LDH_S:
 639         case OPCODE_STH:
 640                 align_mask = 1UL;
 641                 break;
 642
 643         case OPCODE_LDW_I:
 644         case OPCODE_LDWA_I:
 645         case OPCODE_LDW_S:
 646         case OPCODE_LDWA_S:
 647         case OPCODE_STW:
 648         case OPCODE_STWA:
 649                 align_mask = 3UL;
 650                 break;
 651
 652         default:
 653                 switch (regs->iir & OPCODE4_MASK) {
 654                 case OPCODE_LDH_L:
 655                 case OPCODE_STH_L:
 656                         align_mask = 1UL;
 657                         break;
 658                 case OPCODE_LDW_L:
 659                 case OPCODE_LDWM:
 660                 case OPCODE_STW_L:
 661                 case OPCODE_STWM:
 662                         align_mask = 3UL;
 663                         break;
 664                 }
 665                 break;
 666         }
 667
 668         return (int)(regs->ior & align_mask);
 669 }
 670