1 /* This file is subject to the terms and conditions of the GNU General Public
2 * License. See the file "COPYING" in the main directory of this archive
5 * Copyright (C) 1999-2007 by Helge Deller <deller@gmx.de>
6 * Copyright 1999 SuSE GmbH (Philipp Rumpf)
7 * Copyright 1999 Philipp Rumpf (prumpf@tux.org)
8 * Copyright 2000 Hewlett Packard (Paul Bame, bame@puffin.external.hp.com)
9 * Copyright (C) 2001 Grant Grundler (Hewlett Packard)
10 * Copyright (C) 2004 Kyle McMartin <kyle@debian.org>
12 * Initial Version 04-23-1999 by Helge Deller <deller@gmx.de>
15 #include <asm/asm-offsets.h>
19 #include <asm/assembly.h>
21 #include <linux/linkage.h>
22 #include <linux/init.h>
23 #include <linux/pgtable.h>
38 .import init_thread_union,data
39 .import fault_vector_20,code /* IVA parisc 2.0 32 bit */
41 .import fault_vector_11,code /* IVA parisc 1.1 32 bit */
42 .import $global$ /* forward declaration */
43 #endif /*!CONFIG_64BIT*/
44 ENTRY(parisc_kernel_start)
48 /* Make sure sr4-sr7 are set to zero for the kernel address space */
54 /* Clear BSS (shouldn't the boot loader do this?) */
56 .import __bss_start,data
57 .import __bss_stop,data
59 load32 PA(__bss_start),%r3
60 load32 PA(__bss_stop),%r4
62 cmpb,<<,n %r3,%r4,$bss_loop
65 /* Save away the arguments the boot loader passed in (32 bit args) */
66 load32 PA(boot_args),%r1
72 #if defined(CONFIG_PA20)
73 /* check for 64-bit capable CPU as required by current kernel */
79 comib,<>,n 0,%r10,$cpu_ok
82 ldi msg1_end-msg1,%arg1
86 load32 PA(init_stack),%sp
87 #define MEM_CONS 0x3A0
88 ldw MEM_CONS+32(%r0),%arg0 // HPA
89 ldi ENTRY_IO_COUT,%arg1
90 ldw MEM_CONS+36(%r0),%arg2 // SPA
91 ldw MEM_CONS+8(%r0),%arg3 // layers
92 load32 PA(__bss_start),%r1
93 stw %r1,-52(%sp) // arg4
94 stw %r0,-56(%sp) // arg5
95 stw %r10,-60(%sp) // arg6 = ptr to text
96 stw %r11,-64(%sp) // arg7 = len
97 stw %r0,-68(%sp) // arg8
98 load32 PA(.iodc_panic_ret), %rp
99 ldw MEM_CONS+40(%r0),%r1 // ENTRY_IODC
102 b . /* wait endless with ... */
103 or %r10,%r10,%r10 /* qemu idle sleep */
104 msg1: .ascii "Can't boot kernel which was built for PA8x00 CPUs on this machine.\r\n"
112 /* Initialize startup VM. Just map first 16/32 MB of memory */
113 load32 PA(swapper_pg_dir),%r4
114 mtctl %r4,%cr24 /* Initialize kernel root pointer */
115 mtctl %r4,%cr25 /* Initialize user root pointer */
117 #if CONFIG_PGTABLE_LEVELS == 3
120 shrd %r5,PxD_VALUE_SHIFT,%r3
121 ldo (PxD_FLAG_PRESENT+PxD_FLAG_VALID)(%r3),%r3
122 stw %r3,ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4)
123 ldo ASM_PMD_ENTRY*ASM_PMD_ENTRY_SIZE(%r5),%r4
125 /* 2-level page table, so pmd == pgd */
126 ldo ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4),%r4
129 /* Fill in pmd with enough pte directories */
131 SHRREG %r1,PxD_VALUE_SHIFT,%r3
132 ldo (PxD_FLAG_PRESENT+PxD_FLAG_VALID)(%r3),%r3
134 ldi ASM_PT_INITIAL,%r1
138 ldo (PAGE_SIZE >> PxD_VALUE_SHIFT)(%r3),%r3
140 #if CONFIG_PGTABLE_LEVELS == 3
141 ldo ASM_PMD_ENTRY_SIZE(%r4),%r4
143 ldo ASM_PGD_ENTRY_SIZE(%r4),%r4
147 /* Now initialize the PTEs themselves. We use RWX for
148 * everything ... it will get remapped correctly later */
149 ldo 0+_PAGE_KERNEL_RWX(%r0),%r3 /* Hardwired 0 phys addr start */
150 load32 (1<<(KERNEL_INITIAL_ORDER-PAGE_SHIFT)),%r11 /* PFN count */
154 STREGM %r3,ASM_PTE_ENTRY_SIZE(%r1)
155 ldo (1<<PFN_PTE_SHIFT)(%r3),%r3 /* add one PFN */
156 addib,> -1,%r11,$pgt_fill_loop
159 /* Load the return address...er...crash 'n burn */
162 /* And the RFI Target address too */
163 load32 start_parisc,%r11
165 /* And the initial task pointer */
166 load32 init_thread_union,%r6
169 /* And the stack pointer too */
170 ldo THREAD_SZ_ALGN(%r6),%sp
172 #if defined(CONFIG_64BIT) && defined(CONFIG_FUNCTION_TRACER)
174 /* initialize mcount FPTR */
175 /* Get the global data pointer */
177 load32 PA(_mcount), %r10
182 /* Get PDCE_PROC for monarch CPU. */
183 #define MEM_PDC_LO 0x388
184 #define MEM_PDC_HI 0x35C
185 ldw MEM_PDC_LO(%r0),%r3
186 ldw MEM_PDC_HI(%r0),%r10
187 depd %r10, 31, 32, %r3 /* move to upper word */
192 /* Set the smp rendezvous address into page zero.
193 ** It would be safer to do this in init_smp_config() but
194 ** it's just way easier to deal with here because
195 ** of 64-bit function ptrs and the address is local to this file.
197 load32 PA(smp_slave_stext),%r10
198 stw %r10,0x10(%r0) /* MEM_RENDEZ */
199 stw %r0,0x28(%r0) /* MEM_RENDEZ_HI - assume addr < 4GB */
205 ** Code Common to both Monarch and Slave processors.
209 ** %r11 must contain RFI target address.
210 ** %r25/%r26 args to pass to target function
211 ** %r2 in case rfi target decides it didn't like something
214 ** %r3 PDCE_PROC address
215 ** %r11 RFI target address
217 ** Caller must init: SR4-7, %sp, %r10, %cr24/25,
223 /* Clear PDC entry point - we won't use it */
224 stw %r0,0x10(%r0) /* MEM_RENDEZ */
225 stw %r0,0x28(%r0) /* MEM_RENDEZ_HI */
226 #endif /*CONFIG_SMP*/
231 /* Save the rfi target address */
232 ldd TI_TASK-THREAD_SZ_ALGN(%sp), %r10
234 std %r11, TASK_PT_GR11(%r10)
235 /* Switch to wide mode Superdome doesn't support narrow PDC
238 1: mfia %rp /* clear upper part of pcoq */
244 /* Set Wide mode as the "Default" (eg for traps)
245 ** First trap occurs *right* after (or part of) rfi for slave CPUs.
246 ** Someday, palo might not do this for the Monarch either.
249 mfctl %cr30,%r6 /* PCX-W2 firmware bug */
251 ldo PDC_PSW(%r0),%arg0 /* 21 */
252 ldo PDC_PSW_SET_DEFAULTS(%r0),%arg1 /* 2 */
253 ldo PDC_PSW_WIDE_BIT(%r0),%arg2 /* 2 */
254 load32 PA(stext_pdc_ret), %rp
259 mtctl %r6,%cr30 /* restore task thread info */
261 /* restore rfi target address*/
262 ldd TI_TASK-THREAD_SZ_ALGN(%sp), %r10
264 ldd TASK_PT_GR11(%r10), %r11
268 /* PARANOID: clear user scratch/user space SR's */
274 /* Initialize Protection Registers */
280 /* Initialize the global data pointer */
283 /* Set up our interrupt table. HPMCs might not work after this!
285 * We need to install the correct iva for PA1.1 or PA2.0. The
286 * following short sequence of instructions can determine this
287 * (without being illegal on a PA1.1 machine).
295 comib,<>,n 0,%r10,$is_pa20
296 ldil L%PA(fault_vector_11),%r10
298 ldo R%PA(fault_vector_11)(%r10),%r10
301 .level PA_ASM_LEVEL /* restore 1.1 || 2.0w */
302 #endif /*!CONFIG_64BIT*/
303 load32 PA(fault_vector_20),%r10
308 b aligned_rfi /* Prepare to RFI! Man all the cannons! */
315 copy %r3, %arg0 /* PDCE_PROC for smp_callin() */
317 rsm PSW_SM_QUIET,%r0 /* off troublesome PSW bits */
318 /* Don't need NOPs, have 8 compliant insn before rfi */
320 mtctl %r0,%cr17 /* Clear IIASQ tail */
321 mtctl %r0,%cr17 /* Clear IIASQ head */
323 /* Load RFI target into PC queue */
324 mtctl %r11,%cr18 /* IIAOQ head */
326 mtctl %r11,%cr18 /* IIAOQ tail */
328 load32 KERNEL_PSW,%r10
331 /* Jump through hyperspace to Virt Mode */
339 .import smp_init_current_idle_task,data
340 .import smp_callin,code
346 break 1,1 /* Break if returned from start_secondary */
350 #endif /*!CONFIG_64BIT*/
352 /***************************************************************************
353 * smp_slave_stext is executed by all non-monarch Processors when the Monarch
354 * pokes the slave CPUs in smp.c:smp_boot_cpus().
356 * Once here, registers values are initialized in order to branch to virtual
357 * mode. Once all available/eligible CPUs are in virtual mode, all are
358 * released and start out by executing their own idle task.
359 *****************************************************************************/
365 ** Initialize Space registers
374 * Enable Wide mode early, in case the task_struct for the idle
375 * task in smp_init_current_idle_task was allocated above 4GB.
377 1: mfia %rp /* clear upper part of pcoq */
385 /* Initialize the SP - monarch sets up smp_init_current_idle_task */
386 load32 PA(smp_init_current_idle_task),%sp
387 LDREG 0(%sp),%sp /* load task address */
389 LDREG TASK_THREAD_INFO(%sp),%sp
390 mtctl %sp,%cr30 /* store in cr30 */
391 ldo THREAD_SZ_ALGN(%sp),%sp
393 /* point CPU to kernel page tables */
394 load32 PA(swapper_pg_dir),%r4
395 mtctl %r4,%cr24 /* Initialize kernel root pointer */
396 mtctl %r4,%cr25 /* Initialize user root pointer */
399 /* Setup PDCE_PROC entry */
402 /* Load RFI *return* address in case smp_callin bails */
403 load32 smp_callin_rtn,%r2
406 /* Load RFI target address. */
407 load32 smp_callin,%r11
409 /* ok...common code can handle the rest */
414 #endif /* CONFIG_SMP */
416 ENDPROC(parisc_kernel_start)
419 .section .data..ro_after_init
422 .export $global$,data
424 .type $global$,@object
428 #endif /*!CONFIG_64BIT*/