1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
5 * kernel entry points (interruptions, system call wrappers)
6 * Copyright (C) 1999,2000 Philipp Rumpf
7 * Copyright (C) 1999 SuSE GmbH Nuernberg
8 * Copyright (C) 2000 Hewlett-Packard (John Marvin)
9 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
12 #include <asm/asm-offsets.h>
14 /* we have the following possibilities to act on an interruption:
15 * - handle in assembly and use shadowed registers only
16 * - save registers to kernel stack and handle in assembly or C */
20 #include <asm/cache.h> /* for L1_CACHE_SHIFT */
21 #include <asm/assembly.h> /* for LDREG/STREG defines */
22 #include <asm/pgtable.h>
23 #include <asm/signal.h>
24 #include <asm/unistd.h>
26 #include <asm/traps.h>
27 #include <asm/thread_info.h>
28 #include <asm/alternative.h>
30 #include <linux/linkage.h>
38 .import pa_tlb_lock,data
39 .macro load_pa_tlb_lock reg
41 addil L%(PAGE_SIZE << (PGD_ALLOC_ORDER - 1)),\reg
44 /* space_to_prot macro creates a prot id from a space id */
46 #if (SPACEID_SHIFT) == 0
47 .macro space_to_prot spc prot
48 depd,z \spc,62,31,\prot
51 .macro space_to_prot spc prot
52 extrd,u \spc,(64 - (SPACEID_SHIFT)),32,\prot
56 /* Switch to virtual mapping, trashing only %r1 */
59 rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */
64 load32 KERNEL_PSW, %r1
66 rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */
67 mtctl %r0, %cr17 /* Clear IIASQ tail */
68 mtctl %r0, %cr17 /* Clear IIASQ head */
71 mtctl %r1, %cr18 /* Set IIAOQ tail */
73 mtctl %r1, %cr18 /* Set IIAOQ head */
80 * The "get_stack" macros are responsible for determining the
84 * Already using a kernel stack, so call the
85 * get_stack_use_r30 macro to push a pt_regs structure
86 * on the stack, and store registers there.
88 * Need to set up a kernel stack, so call the
89 * get_stack_use_cr30 macro to set up a pointer
90 * to the pt_regs structure contained within the
91 * task pointer pointed to by cr30. Set the stack
92 * pointer to point to the end of the task structure.
94 * Note that we use shadowed registers for temps until
95 * we can save %r26 and %r29. %r26 is used to preserve
96 * %r8 (a shadowed register) which temporarily contained
97 * either the fault type ("code") or the eirr. We need
98 * to use a non-shadowed register to carry the value over
99 * the rfir in virt_map. We use %r26 since this value winds
100 * up being passed as the argument to either do_cpu_irq_mask
101 * or handle_interruption. %r29 is used to hold a pointer
102 * the register save area, and once again, it needs to
103 * be a non-shadowed register so that it survives the rfir.
105 * N.B. TASK_SZ_ALGN and PT_SZ_ALGN include space for a stack frame.
108 .macro get_stack_use_cr30
110 /* we save the registers in the task struct */
114 ldo THREAD_SZ_ALGN(%r1), %r30
118 LDREG TI_TASK(%r9), %r1 /* thread_info -> task_struct */
120 ldo TASK_REGS(%r9),%r9
121 STREG %r17,PT_GR30(%r9)
122 STREG %r29,PT_GR29(%r9)
123 STREG %r26,PT_GR26(%r9)
124 STREG %r16,PT_SR7(%r9)
128 .macro get_stack_use_r30
130 /* we put a struct pt_regs on the stack and save the registers there */
134 ldo PT_SZ_ALGN(%r30),%r30
135 STREG %r1,PT_GR30(%r9)
136 STREG %r29,PT_GR29(%r9)
137 STREG %r26,PT_GR26(%r9)
138 STREG %r16,PT_SR7(%r9)
143 LDREG PT_GR1(%r29), %r1
144 LDREG PT_GR30(%r29),%r30
145 LDREG PT_GR29(%r29),%r29
148 /* default interruption handler
149 * (calls traps.c:handle_interruption) */
156 /* Interrupt interruption handler
157 * (calls irq.c:do_cpu_irq_mask) */
164 .import os_hpmc, code
168 nop /* must be a NOP, will be patched later */
169 load32 PA(os_hpmc), %r3
172 .word 0 /* checksum (will be patched) */
173 .word 0 /* address of handler */
174 .word 0 /* length of handler */
178 * Performance Note: Instructions will be moved up into
179 * this part of the code later on, once we are sure
180 * that the tlb miss handlers are close to final form.
183 /* Register definitions for tlb miss handler macros */
185 va = r8 /* virtual address for which the trap occurred */
186 spc = r24 /* space for which the trap occurred */
191 * itlb miss interruption handler (parisc 1.1 - 32 bit)
205 * itlb miss interruption handler (parisc 2.0)
222 * naitlb miss interruption handler (parisc 1.1 - 32 bit)
225 .macro naitlb_11 code
236 * naitlb miss interruption handler (parisc 2.0)
239 .macro naitlb_20 code
254 * dtlb miss interruption handler (parisc 1.1 - 32 bit)
268 * dtlb miss interruption handler (parisc 2.0)
285 /* nadtlb miss interruption handler (parisc 1.1 - 32 bit) */
287 .macro nadtlb_11 code
297 /* nadtlb miss interruption handler (parisc 2.0) */
299 .macro nadtlb_20 code
314 * dirty bit trap interruption handler (parisc 1.1 - 32 bit)
328 * dirty bit trap interruption handler (parisc 2.0)
344 /* In LP64, the space contains part of the upper 32 bits of the
345 * fault. We have to extract this and place it in the va,
346 * zeroing the corresponding bits in the space register */
347 .macro space_adjust spc,va,tmp
349 extrd,u \spc,63,SPACEID_SHIFT,\tmp
350 depd %r0,63,SPACEID_SHIFT,\spc
351 depd \tmp,31,SPACEID_SHIFT,\va
355 .import swapper_pg_dir,code
357 /* Get the pgd. For faults on space zero (kernel space), this
358 * is simply swapper_pg_dir. For user space faults, the
359 * pgd is stored in %cr25 */
360 .macro get_pgd spc,reg
361 ldil L%PA(swapper_pg_dir),\reg
362 ldo R%PA(swapper_pg_dir)(\reg),\reg
363 or,COND(=) %r0,\spc,%r0
368 space_check(spc,tmp,fault)
370 spc - The space we saw the fault with.
371 tmp - The place to store the current space.
372 fault - Function to call on failure.
374 Only allow faults on different spaces from the
375 currently active one if we're the kernel
378 .macro space_check spc,tmp,fault
380 /* check against %r0 which is same value as LINUX_GATEWAY_SPACE */
381 or,COND(<>) %r0,\spc,%r0 /* user may execute gateway page
382 * as kernel, so defeat the space
385 or,COND(=) %r0,\tmp,%r0 /* nullify if executing as kernel */
386 cmpb,COND(<>),n \tmp,\spc,\fault
389 /* Look up a PTE in a 2-Level scheme (faulting at each
390 * level if the entry isn't present
392 * NOTE: we use ldw even for LP64, since the short pointers
393 * can address up to 1TB
395 .macro L2_ptep pmd,pte,index,va,fault
396 #if CONFIG_PGTABLE_LEVELS == 3
397 extru \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index
399 # if defined(CONFIG_64BIT)
400 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
402 # if PAGE_SIZE > 4096
403 extru \va,31-ASM_PGDIR_SHIFT,32-ASM_PGDIR_SHIFT,\index
405 extru \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
409 dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
411 ldw,s \index(\pmd),\pmd
412 bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault
413 dep %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
414 SHLREG \pmd,PxD_VALUE_SHIFT,\pmd
415 extru \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
416 dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
417 shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd /* pmd is now pte */
420 /* Look up PTE in a 3-Level scheme.
422 * Here we implement a Hybrid L2/L3 scheme: we allocate the
423 * first pmd adjacent to the pgd. This means that we can
424 * subtract a constant offset to get to it. The pmd and pgd
425 * sizes are arranged so that a single pmd covers 4GB (giving
426 * a full LP64 process access to 8TB) so our lookups are
427 * effectively L2 for the first 4GB of the kernel (i.e. for
428 * all ILP32 processes and all the kernel for machines with
429 * under 4GB of memory) */
430 .macro L3_ptep pgd,pte,index,va,fault
431 #if CONFIG_PGTABLE_LEVELS == 3 /* we might have a 2-Level scheme, e.g. with 16kb page size */
432 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
433 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
434 ldw,s \index(\pgd),\pgd
435 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
436 bb,>=,n \pgd,_PxD_PRESENT_BIT,\fault
437 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
438 shld \pgd,PxD_VALUE_SHIFT,\index
439 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
441 extrd,u,*<> \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
442 ldo ASM_PGD_PMD_OFFSET(\pgd),\pgd
444 L2_ptep \pgd,\pte,\index,\va,\fault
447 /* Acquire pa_tlb_lock lock and check page is present. */
448 .macro tlb_lock spc,ptp,pte,tmp,tmp1,fault
450 98: cmpib,COND(=),n 0,\spc,2f
451 load_pa_tlb_lock \tmp
452 1: LDCW 0(\tmp),\tmp1
453 cmpib,COND(=) 0,\tmp1,1b
456 bb,<,n \pte,_PAGE_PRESENT_BIT,3f
459 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
461 2: LDREG 0(\ptp),\pte
462 bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault
466 /* Release pa_tlb_lock lock without reloading lock address.
467 Note that the values in the register spc are limited to
468 NR_SPACE_IDS (262144). Thus, the stw instruction always
469 stores a nonzero value even when register spc is 64 bits.
470 We use an ordered store to ensure all prior accesses are
471 performed prior to releasing the lock. */
472 .macro tlb_unlock0 spc,tmp
474 98: or,COND(=) %r0,\spc,%r0
476 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
480 /* Release pa_tlb_lock lock. */
481 .macro tlb_unlock1 spc,tmp
483 98: load_pa_tlb_lock \tmp
484 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
485 tlb_unlock0 \spc,\tmp
489 /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and
490 * don't needlessly dirty the cache line if it was already set */
491 .macro update_accessed ptp,pte,tmp,tmp1
492 ldi _PAGE_ACCESSED,\tmp1
494 and,COND(<>) \tmp1,\pte,%r0
498 /* Set the dirty bit (and accessed bit). No need to be
499 * clever, this is only used from the dirty fault */
500 .macro update_dirty ptp,pte,tmp
501 ldi _PAGE_ACCESSED|_PAGE_DIRTY,\tmp
506 /* We have (depending on the page size):
507 * - 38 to 52-bit Physical Page Number
508 * - 12 to 26-bit page offset
510 /* bitshift difference between a PFN (based on kernel's PAGE_SIZE)
511 * to a CPU TLB 4k PFN (4k => 12 bits to shift) */
512 #define PAGE_ADD_SHIFT (PAGE_SHIFT-12)
513 #define PAGE_ADD_HUGE_SHIFT (REAL_HPAGE_SHIFT-12)
514 #define PFN_START_BIT (63-ASM_PFN_PTE_SHIFT+(63-58)-PAGE_ADD_SHIFT)
516 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
517 .macro convert_for_tlb_insert20 pte,tmp
518 #ifdef CONFIG_HUGETLB_PAGE
520 extrd,u \tmp,PFN_START_BIT,PFN_START_BIT+1,\pte
522 depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\
523 (63-58)+PAGE_ADD_SHIFT,\pte
524 extrd,u,*= \tmp,_PAGE_HPAGE_BIT+32,1,%r0
525 depdi _HUGE_PAGE_SIZE_ENCODING_DEFAULT,63,\
526 (63-58)+PAGE_ADD_HUGE_SHIFT,\pte
527 #else /* Huge pages disabled */
528 extrd,u \pte,PFN_START_BIT,PFN_START_BIT+1,\pte
529 depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\
530 (63-58)+PAGE_ADD_SHIFT,\pte
534 /* Convert the pte and prot to tlb insertion values. How
535 * this happens is quite subtle, read below */
536 .macro make_insert_tlb spc,pte,prot,tmp
537 space_to_prot \spc \prot /* create prot id from space */
538 /* The following is the real subtlety. This is depositing
539 * T <-> _PAGE_REFTRAP
541 * B <-> _PAGE_DMB (memory break)
543 * Then incredible subtlety: The access rights are
544 * _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE
545 * See 3-14 of the parisc 2.0 manual
547 * Finally, _PAGE_READ goes in the top bit of PL1 (so we
548 * trigger an access rights trap in user space if the user
549 * tries to read an unreadable page */
552 /* PAGE_USER indicates the page can be read with user privileges,
553 * so deposit X1|11 to PL1|PL2 (remember the upper bit of PL1
554 * contains _PAGE_READ) */
555 extrd,u,*= \pte,_PAGE_USER_BIT+32,1,%r0
557 /* If we're a gateway page, drop PL2 back to zero for promotion
558 * to kernel privilege (so we can execute the page as kernel).
559 * Any privilege promotion page always denys read and write */
560 extrd,u,*= \pte,_PAGE_GATEWAY_BIT+32,1,%r0
561 depd %r0,11,2,\prot /* If Gateway, Set PL2 to 0 */
563 /* Enforce uncacheable pages.
564 * This should ONLY be use for MMIO on PA 2.0 machines.
565 * Memory/DMA is cache coherent on all PA2.0 machines we support
566 * (that means T-class is NOT supported) and the memory controllers
567 * on most of those machines only handles cache transactions.
569 extrd,u,*= \pte,_PAGE_NO_CACHE_BIT+32,1,%r0
572 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
573 convert_for_tlb_insert20 \pte \tmp
576 /* Identical macro to make_insert_tlb above, except it
577 * makes the tlb entry for the differently formatted pa11
578 * insertion instructions */
579 .macro make_insert_tlb_11 spc,pte,prot
580 zdep \spc,30,15,\prot
582 extru,= \pte,_PAGE_NO_CACHE_BIT,1,%r0
584 extru,= \pte,_PAGE_USER_BIT,1,%r0
585 depi 7,11,3,\prot /* Set for user space (1 rsvd for read) */
586 extru,= \pte,_PAGE_GATEWAY_BIT,1,%r0
587 depi 0,11,2,\prot /* If Gateway, Set PL2 to 0 */
589 /* Get rid of prot bits and convert to page addr for iitlba */
591 depi 0,31,ASM_PFN_PTE_SHIFT,\pte
592 SHRREG \pte,(ASM_PFN_PTE_SHIFT-(31-26)),\pte
595 /* This is for ILP32 PA2.0 only. The TLB insertion needs
596 * to extend into I/O space if the address is 0xfXXXXXXX
597 * so we extend the f's into the top word of the pte in
599 .macro f_extend pte,tmp
600 extrd,s \pte,42,4,\tmp
602 extrd,s \pte,63,25,\pte
605 /* The alias region is an 8MB aligned 16MB to do clear and
606 * copy user pages at addresses congruent with the user
609 * To use the alias page, you set %r26 up with the to TLB
610 * entry (identifying the physical page) and %r23 up with
611 * the from tlb entry (or nothing if only a to entry---for
612 * clear_user_page_asm) */
613 .macro do_alias spc,tmp,tmp1,va,pte,prot,fault,patype
614 cmpib,COND(<>),n 0,\spc,\fault
615 ldil L%(TMPALIAS_MAP_START),\tmp
616 #if defined(CONFIG_64BIT) && (TMPALIAS_MAP_START >= 0x80000000)
617 /* on LP64, ldi will sign extend into the upper 32 bits,
618 * which is behaviour we don't want */
623 cmpb,COND(<>),n \tmp,\tmp1,\fault
624 mfctl %cr19,\tmp /* iir */
625 /* get the opcode (first six bits) into \tmp */
626 extrw,u \tmp,5,6,\tmp
628 * Only setting the T bit prevents data cache movein
629 * Setting access rights to zero prevents instruction cache movein
631 * Note subtlety here: _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE go
632 * to type field and _PAGE_READ goes to top bit of PL1
634 ldi (_PAGE_REFTRAP|_PAGE_READ|_PAGE_WRITE),\prot
636 * so if the opcode is one (i.e. this is a memory management
637 * instruction) nullify the next load so \prot is only T.
638 * Otherwise this is a normal data operation
640 cmpiclr,= 0x01,\tmp,%r0
641 ldi (_PAGE_DIRTY|_PAGE_READ|_PAGE_WRITE),\prot
643 depd,z \prot,8,7,\prot
646 depw,z \prot,8,7,\prot
648 .error "undefined PA type to do_alias"
652 * OK, it is in the temp alias region, check whether "from" or "to".
653 * Check "subtle" note in pacache.S re: r23/r26.
656 extrd,u,*= \va,41,1,%r0
658 extrw,u,= \va,9,1,%r0
660 or,COND(tr) %r23,%r0,\pte
666 * Fault_vectors are architecturally required to be aligned on a 2K
673 ENTRY(fault_vector_20)
674 /* First vector is invalid (0) */
675 .ascii "cows can fly"
684 itlb_20 PARISC_ITLB_TRAP
716 ENTRY(fault_vector_11)
717 /* First vector is invalid (0) */
718 .ascii "cows can fly"
727 itlb_11 PARISC_ITLB_TRAP
756 /* Fault vector is separately protected and *must* be on its own page */
759 .import handle_interruption,code
760 .import do_cpu_irq_mask,code
765 * copy_thread moved args into task save area.
768 ENTRY(ret_from_kernel_thread)
769 /* Call schedule_tail first though */
770 BL schedule_tail, %r2
773 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
774 LDREG TASK_PT_GR25(%r1), %r26
776 LDREG TASK_PT_GR27(%r1), %r27
778 LDREG TASK_PT_GR26(%r1), %r1
781 b finish_child_return
783 END(ret_from_kernel_thread)
787 * struct task_struct *_switch_to(struct task_struct *prev,
788 * struct task_struct *next)
790 * switch kernel stacks and return prev */
791 ENTRY_CFI(_switch_to)
792 STREG %r2, -RP_OFFSET(%r30)
797 load32 _switch_to_ret, %r2
799 STREG %r2, TASK_PT_KPC(%r26)
800 LDREG TASK_PT_KPC(%r25), %r2
802 STREG %r30, TASK_PT_KSP(%r26)
803 LDREG TASK_PT_KSP(%r25), %r30
804 LDREG TASK_THREAD_INFO(%r25), %r25
808 ENTRY(_switch_to_ret)
809 mtctl %r0, %cr0 /* Needed for single stepping */
813 LDREG -RP_OFFSET(%r30), %r2
816 ENDPROC_CFI(_switch_to)
819 * Common rfi return path for interruptions, kernel execve, and
820 * sys_rt_sigreturn (sometimes). The sys_rt_sigreturn syscall will
821 * return via this path if the signal was received when the process
822 * was running; if the process was blocked on a syscall then the
823 * normal syscall_exit path is used. All syscalls for traced
824 * proceses exit via intr_restore.
826 * XXX If any syscalls that change a processes space id ever exit
827 * this way, then we will need to copy %sr3 in to PT_SR[3..7], and
834 ENTRY_CFI(syscall_exit_rfi)
836 LDREG TI_TASK(%r16), %r16 /* thread_info -> task_struct */
837 ldo TASK_REGS(%r16),%r16
838 /* Force iaoq to userspace, as the user has had access to our current
839 * context via sigcontext. Also Filter the PSW for the same reason.
841 LDREG PT_IAOQ0(%r16),%r19
843 STREG %r19,PT_IAOQ0(%r16)
844 LDREG PT_IAOQ1(%r16),%r19
846 STREG %r19,PT_IAOQ1(%r16)
847 LDREG PT_PSW(%r16),%r19
848 load32 USER_PSW_MASK,%r1
850 load32 USER_PSW_HI_MASK,%r20
853 and %r19,%r1,%r19 /* Mask out bits that user shouldn't play with */
855 or %r19,%r1,%r19 /* Make sure default USER_PSW bits are set */
856 STREG %r19,PT_PSW(%r16)
859 * If we aren't being traced, we never saved space registers
860 * (we don't store them in the sigcontext), so set them
861 * to "proper" values now (otherwise we'll wind up restoring
862 * whatever was last stored in the task structure, which might
863 * be inconsistent if an interrupt occurred while on the gateway
864 * page). Note that we may be "trashing" values the user put in
865 * them, but we don't support the user changing them.
868 STREG %r0,PT_SR2(%r16)
870 STREG %r19,PT_SR0(%r16)
871 STREG %r19,PT_SR1(%r16)
872 STREG %r19,PT_SR3(%r16)
873 STREG %r19,PT_SR4(%r16)
874 STREG %r19,PT_SR5(%r16)
875 STREG %r19,PT_SR6(%r16)
876 STREG %r19,PT_SR7(%r16)
879 /* check for reschedule */
881 LDREG TI_FLAGS(%r1),%r19 /* sched.h: TIF_NEED_RESCHED */
882 bb,<,n %r19,31-TIF_NEED_RESCHED,intr_do_resched /* forward */
884 .import do_notify_resume,code
888 LDREG TI_FLAGS(%r1),%r19
889 ldi (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME), %r20
890 and,COND(<>) %r19, %r20, %r0
891 b,n intr_restore /* skip past if we've nothing to do */
893 /* This check is critical to having LWS
894 * working. The IASQ is zero on the gateway
895 * page and we cannot deliver any signals until
896 * we get off the gateway page.
898 * Only do signals if we are returning to user space
900 LDREG PT_IASQ0(%r16), %r20
901 cmpib,COND(=),n LINUX_GATEWAY_SPACE, %r20, intr_restore /* backward */
902 LDREG PT_IASQ1(%r16), %r20
903 cmpib,COND(=),n LINUX_GATEWAY_SPACE, %r20, intr_restore /* backward */
905 /* NOTE: We need to enable interrupts if we have to deliver
906 * signals. We used to do this earlier but it caused kernel
907 * stack overflows. */
910 copy %r0, %r25 /* long in_syscall = 0 */
912 ldo -16(%r30),%r29 /* Reference param save area */
915 BL do_notify_resume,%r2
916 copy %r16, %r26 /* struct pt_regs *regs */
922 ldo PT_FR31(%r29),%r1
926 /* inverse of virt_map */
928 rsm PSW_SM_QUIET,%r0 /* prepare for rfi */
931 /* Restore space id's and special cr's from PT_REGS
932 * structure pointed to by r29
936 /* IMPORTANT: rest_stack restores r29 last (we are using it)!
937 * It also restores r1 and r30.
944 #ifndef CONFIG_PREEMPT
945 # define intr_do_preempt intr_restore
946 #endif /* !CONFIG_PREEMPT */
948 .import schedule,code
950 /* Only call schedule on return to userspace. If we're returning
951 * to kernel space, we may schedule if CONFIG_PREEMPT, otherwise
952 * we jump back to intr_restore.
954 LDREG PT_IASQ0(%r16), %r20
955 cmpib,COND(=) 0, %r20, intr_do_preempt
957 LDREG PT_IASQ1(%r16), %r20
958 cmpib,COND(=) 0, %r20, intr_do_preempt
961 /* NOTE: We need to enable interrupts if we schedule. We used
962 * to do this earlier but it caused kernel stack overflows. */
966 ldo -16(%r30),%r29 /* Reference param save area */
969 ldil L%intr_check_sig, %r2
973 load32 schedule, %r20
976 ldo R%intr_check_sig(%r2), %r2
978 /* preempt the current task on returning to kernel
979 * mode from an interrupt, iff need_resched is set,
980 * and preempt_count is 0. otherwise, we continue on
981 * our merry way back to the current running task.
983 #ifdef CONFIG_PREEMPT
984 .import preempt_schedule_irq,code
986 rsm PSW_SM_I, %r0 /* disable interrupts */
988 /* current_thread_info()->preempt_count */
990 LDREG TI_PRE_COUNT(%r1), %r19
991 cmpib,COND(<>) 0, %r19, intr_restore /* if preempt_count > 0 */
992 nop /* prev insn branched backwards */
994 /* check if we interrupted a critical path */
995 LDREG PT_PSW(%r16), %r20
996 bb,<,n %r20, 31 - PSW_SM_I, intr_restore
999 BL preempt_schedule_irq, %r2
1002 b,n intr_restore /* ssm PSW_SM_I done by intr_restore */
1003 #endif /* CONFIG_PREEMPT */
1006 * External interrupts.
1010 cmpib,COND(=),n 0,%r16,1f
1022 ldo PT_FR0(%r29), %r24
1027 copy %r29, %r26 /* arg0 is pt_regs */
1028 copy %r29, %r16 /* save pt_regs */
1030 ldil L%intr_return, %r2
1033 ldo -16(%r30),%r29 /* Reference param save area */
1037 ldo R%intr_return(%r2), %r2 /* return to intr_return, not here */
1038 ENDPROC_CFI(syscall_exit_rfi)
1041 /* Generic interruptions (illegal insn, unaligned, page fault, etc) */
1043 ENTRY_CFI(intr_save) /* for os_hpmc */
1045 cmpib,COND(=),n 0,%r16,1f
1057 /* If this trap is a itlb miss, skip saving/adjusting isr/ior */
1058 cmpib,COND(=),n PARISC_ITLB_TRAP,%r26,skip_save_ior
1062 nop /* serialize mfctl on PA 2.0 to avoid 4 cycle penalty */
1068 * If the interrupted code was running with W bit off (32 bit),
1069 * clear the b bits (bits 0 & 1) in the ior.
1070 * save_specials left ipsw value in r8 for us to test.
1072 extrd,u,*<> %r8,PSW_W_BIT,1,%r0
1075 /* adjust isr/ior: get high bits from isr and deposit in ior */
1076 space_adjust %r16,%r17,%r1
1078 STREG %r16, PT_ISR(%r29)
1079 STREG %r17, PT_IOR(%r29)
1081 #if 0 && defined(CONFIG_64BIT)
1082 /* Revisit when we have 64-bit code above 4Gb */
1086 /* We have a itlb miss, and when executing code above 4 Gb on ILP64, we
1087 * need to adjust iasq/iaoq here in the same way we adjusted isr/ior
1090 extrd,u,* %r8,PSW_W_BIT,1,%r1
1091 cmpib,COND(=),n 1,%r1,intr_save2
1092 LDREG PT_IASQ0(%r29), %r16
1093 LDREG PT_IAOQ0(%r29), %r17
1094 /* adjust iasq/iaoq */
1095 space_adjust %r16,%r17,%r1
1096 STREG %r16, PT_IASQ0(%r29)
1097 STREG %r17, PT_IAOQ0(%r29)
1106 ldo PT_FR0(%r29), %r25
1111 copy %r29, %r25 /* arg1 is pt_regs */
1113 ldo -16(%r30),%r29 /* Reference param save area */
1116 ldil L%intr_check_sig, %r2
1117 copy %r25, %r16 /* save pt_regs */
1119 b handle_interruption
1120 ldo R%intr_check_sig(%r2), %r2
1121 ENDPROC_CFI(intr_save)
1125 * Note for all tlb miss handlers:
1127 * cr24 contains a pointer to the kernel address space
1130 * cr25 contains a pointer to the current user address
1131 * space page directory.
1133 * sr3 will contain the space id of the user address space
1134 * of the current running thread while that thread is
1135 * running in the kernel.
1139 * register number allocations. Note that these are all
1140 * in the shadowed registers
1143 t0 = r1 /* temporary register 0 */
1144 va = r8 /* virtual address for which the trap occurred */
1145 t1 = r9 /* temporary register 1 */
1146 pte = r16 /* pte/phys page # */
1147 prot = r17 /* prot bits */
1148 spc = r24 /* space for which the trap occurred */
1149 ptp = r25 /* page directory/page table pointer */
1154 space_adjust spc,va,t0
1156 space_check spc,t0,dtlb_fault
1158 L3_ptep ptp,pte,t0,va,dtlb_check_alias_20w
1160 tlb_lock spc,ptp,pte,t0,t1,dtlb_check_alias_20w
1161 update_accessed ptp,pte,t0,t1
1163 make_insert_tlb spc,pte,prot,t1
1171 dtlb_check_alias_20w:
1172 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,20
1180 space_adjust spc,va,t0
1182 space_check spc,t0,nadtlb_fault
1184 L3_ptep ptp,pte,t0,va,nadtlb_check_alias_20w
1186 tlb_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_20w
1187 update_accessed ptp,pte,t0,t1
1189 make_insert_tlb spc,pte,prot,t1
1197 nadtlb_check_alias_20w:
1198 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,20
1210 space_check spc,t0,dtlb_fault
1212 L2_ptep ptp,pte,t0,va,dtlb_check_alias_11
1214 tlb_lock spc,ptp,pte,t0,t1,dtlb_check_alias_11
1215 update_accessed ptp,pte,t0,t1
1217 make_insert_tlb_11 spc,pte,prot
1219 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1222 idtlba pte,(%sr1,va)
1223 idtlbp prot,(%sr1,va)
1225 mtsp t1, %sr1 /* Restore sr1 */
1231 dtlb_check_alias_11:
1232 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,11
1243 space_check spc,t0,nadtlb_fault
1245 L2_ptep ptp,pte,t0,va,nadtlb_check_alias_11
1247 tlb_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_11
1248 update_accessed ptp,pte,t0,t1
1250 make_insert_tlb_11 spc,pte,prot
1252 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1255 idtlba pte,(%sr1,va)
1256 idtlbp prot,(%sr1,va)
1258 mtsp t1, %sr1 /* Restore sr1 */
1264 nadtlb_check_alias_11:
1265 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,11
1274 space_adjust spc,va,t0
1276 space_check spc,t0,dtlb_fault
1278 L2_ptep ptp,pte,t0,va,dtlb_check_alias_20
1280 tlb_lock spc,ptp,pte,t0,t1,dtlb_check_alias_20
1281 update_accessed ptp,pte,t0,t1
1283 make_insert_tlb spc,pte,prot,t1
1293 dtlb_check_alias_20:
1294 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,20
1304 space_check spc,t0,nadtlb_fault
1306 L2_ptep ptp,pte,t0,va,nadtlb_check_alias_20
1308 tlb_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_20
1309 update_accessed ptp,pte,t0,t1
1311 make_insert_tlb spc,pte,prot,t1
1321 nadtlb_check_alias_20:
1322 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,20
1334 * Non access misses can be caused by fdc,fic,pdc,lpa,probe and
1335 * probei instructions. We don't want to fault for these
1336 * instructions (not only does it not make sense, it can cause
1337 * deadlocks, since some flushes are done with the mmap
1338 * semaphore held). If the translation doesn't exist, we can't
1339 * insert a translation, so have to emulate the side effects
1340 * of the instruction. Since we don't insert a translation
1341 * we can get a lot of faults during a flush loop, so it makes
1342 * sense to try to do it here with minimum overhead. We only
1343 * emulate fdc,fic,pdc,probew,prober instructions whose base
1344 * and index registers are not shadowed. We defer everything
1345 * else to the "slow" path.
1348 mfctl %cr19,%r9 /* Get iir */
1350 /* PA 2.0 Arch Ref. Book pg 382 has a good description of the insn bits.
1351 Checks for fdc,fdce,pdc,"fic,4f",prober,probeir,probew, probeiw */
1353 /* Checks for fdc,fdce,pdc,"fic,4f" only */
1356 cmpb,<>,n %r16,%r17,nadtlb_probe_check
1357 bb,>=,n %r9,26,nadtlb_nullify /* m bit not set, just nullify */
1358 BL get_register,%r25
1359 extrw,u %r9,15,5,%r8 /* Get index register # */
1360 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1362 BL get_register,%r25
1363 extrw,u %r9,10,5,%r8 /* Get base register # */
1364 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1365 BL set_register,%r25
1366 add,l %r1,%r24,%r1 /* doesn't affect c/b bits */
1371 or %r8,%r9,%r8 /* Set PSW_N */
1378 When there is no translation for the probe address then we
1379 must nullify the insn and return zero in the target register.
1380 This will indicate to the calling code that it does not have
1381 write/read privileges to this address.
1383 This should technically work for prober and probew in PA 1.1,
1384 and also probe,r and probe,w in PA 2.0
1386 WARNING: USE ONLY NON-SHADOW REGISTERS WITH PROBE INSN!
1387 THE SLOW-PATH EMULATION HAS NOT BEEN WRITTEN YET.
1393 cmpb,<>,n %r16,%r17,nadtlb_fault /* Must be probe,[rw]*/
1394 BL get_register,%r25 /* Find the target register */
1395 extrw,u %r9,31,5,%r8 /* Get target register */
1396 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1397 BL set_register,%r25
1398 copy %r0,%r1 /* Write zero to target register */
1399 b nadtlb_nullify /* Nullify return insn */
1407 * I miss is a little different, since we allow users to fault
1408 * on the gateway page which is in the kernel address space.
1411 space_adjust spc,va,t0
1413 space_check spc,t0,itlb_fault
1415 L3_ptep ptp,pte,t0,va,itlb_fault
1417 tlb_lock spc,ptp,pte,t0,t1,itlb_fault
1418 update_accessed ptp,pte,t0,t1
1420 make_insert_tlb spc,pte,prot,t1
1431 * I miss is a little different, since we allow users to fault
1432 * on the gateway page which is in the kernel address space.
1435 space_adjust spc,va,t0
1437 space_check spc,t0,naitlb_fault
1439 L3_ptep ptp,pte,t0,va,naitlb_check_alias_20w
1441 tlb_lock spc,ptp,pte,t0,t1,naitlb_check_alias_20w
1442 update_accessed ptp,pte,t0,t1
1444 make_insert_tlb spc,pte,prot,t1
1452 naitlb_check_alias_20w:
1453 do_alias spc,t0,t1,va,pte,prot,naitlb_fault,20
1465 space_check spc,t0,itlb_fault
1467 L2_ptep ptp,pte,t0,va,itlb_fault
1469 tlb_lock spc,ptp,pte,t0,t1,itlb_fault
1470 update_accessed ptp,pte,t0,t1
1472 make_insert_tlb_11 spc,pte,prot
1474 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1477 iitlba pte,(%sr1,va)
1478 iitlbp prot,(%sr1,va)
1480 mtsp t1, %sr1 /* Restore sr1 */
1489 space_check spc,t0,naitlb_fault
1491 L2_ptep ptp,pte,t0,va,naitlb_check_alias_11
1493 tlb_lock spc,ptp,pte,t0,t1,naitlb_check_alias_11
1494 update_accessed ptp,pte,t0,t1
1496 make_insert_tlb_11 spc,pte,prot
1498 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1501 iitlba pte,(%sr1,va)
1502 iitlbp prot,(%sr1,va)
1504 mtsp t1, %sr1 /* Restore sr1 */
1510 naitlb_check_alias_11:
1511 do_alias spc,t0,t1,va,pte,prot,itlb_fault,11
1513 iitlba pte,(%sr0, va)
1514 iitlbp prot,(%sr0, va)
1523 space_check spc,t0,itlb_fault
1525 L2_ptep ptp,pte,t0,va,itlb_fault
1527 tlb_lock spc,ptp,pte,t0,t1,itlb_fault
1528 update_accessed ptp,pte,t0,t1
1530 make_insert_tlb spc,pte,prot,t1
1543 space_check spc,t0,naitlb_fault
1545 L2_ptep ptp,pte,t0,va,naitlb_check_alias_20
1547 tlb_lock spc,ptp,pte,t0,t1,naitlb_check_alias_20
1548 update_accessed ptp,pte,t0,t1
1550 make_insert_tlb spc,pte,prot,t1
1560 naitlb_check_alias_20:
1561 do_alias spc,t0,t1,va,pte,prot,naitlb_fault,20
1573 space_adjust spc,va,t0
1575 space_check spc,t0,dbit_fault
1577 L3_ptep ptp,pte,t0,va,dbit_fault
1579 tlb_lock spc,ptp,pte,t0,t1,dbit_fault
1580 update_dirty ptp,pte,t1
1582 make_insert_tlb spc,pte,prot,t1
1595 space_check spc,t0,dbit_fault
1597 L2_ptep ptp,pte,t0,va,dbit_fault
1599 tlb_lock spc,ptp,pte,t0,t1,dbit_fault
1600 update_dirty ptp,pte,t1
1602 make_insert_tlb_11 spc,pte,prot
1604 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1607 idtlba pte,(%sr1,va)
1608 idtlbp prot,(%sr1,va)
1610 mtsp t1, %sr1 /* Restore sr1 */
1619 space_check spc,t0,dbit_fault
1621 L2_ptep ptp,pte,t0,va,dbit_fault
1623 tlb_lock spc,ptp,pte,t0,t1,dbit_fault
1624 update_dirty ptp,pte,t1
1626 make_insert_tlb spc,pte,prot,t1
1637 .import handle_interruption,code
1641 ldi 31,%r8 /* Use an unused code */
1649 ldi PARISC_ITLB_TRAP,%r8
1663 /* Register saving semantics for system calls:
1665 %r1 clobbered by system call macro in userspace
1666 %r2 saved in PT_REGS by gateway page
1667 %r3 - %r18 preserved by C code (saved by signal code)
1668 %r19 - %r20 saved in PT_REGS by gateway page
1669 %r21 - %r22 non-standard syscall args
1670 stored in kernel stack by gateway page
1671 %r23 - %r26 arg3-arg0, saved in PT_REGS by gateway page
1672 %r27 - %r30 saved in PT_REGS by gateway page
1673 %r31 syscall return pointer
1676 /* Floating point registers (FIXME: what do we do with these?)
1678 %fr0 - %fr3 status/exception, not preserved
1679 %fr4 - %fr7 arguments
1680 %fr8 - %fr11 not preserved by C code
1681 %fr12 - %fr21 preserved by C code
1682 %fr22 - %fr31 not preserved by C code
1685 .macro reg_save regs
1686 STREG %r3, PT_GR3(\regs)
1687 STREG %r4, PT_GR4(\regs)
1688 STREG %r5, PT_GR5(\regs)
1689 STREG %r6, PT_GR6(\regs)
1690 STREG %r7, PT_GR7(\regs)
1691 STREG %r8, PT_GR8(\regs)
1692 STREG %r9, PT_GR9(\regs)
1693 STREG %r10,PT_GR10(\regs)
1694 STREG %r11,PT_GR11(\regs)
1695 STREG %r12,PT_GR12(\regs)
1696 STREG %r13,PT_GR13(\regs)
1697 STREG %r14,PT_GR14(\regs)
1698 STREG %r15,PT_GR15(\regs)
1699 STREG %r16,PT_GR16(\regs)
1700 STREG %r17,PT_GR17(\regs)
1701 STREG %r18,PT_GR18(\regs)
1704 .macro reg_restore regs
1705 LDREG PT_GR3(\regs), %r3
1706 LDREG PT_GR4(\regs), %r4
1707 LDREG PT_GR5(\regs), %r5
1708 LDREG PT_GR6(\regs), %r6
1709 LDREG PT_GR7(\regs), %r7
1710 LDREG PT_GR8(\regs), %r8
1711 LDREG PT_GR9(\regs), %r9
1712 LDREG PT_GR10(\regs),%r10
1713 LDREG PT_GR11(\regs),%r11
1714 LDREG PT_GR12(\regs),%r12
1715 LDREG PT_GR13(\regs),%r13
1716 LDREG PT_GR14(\regs),%r14
1717 LDREG PT_GR15(\regs),%r15
1718 LDREG PT_GR16(\regs),%r16
1719 LDREG PT_GR17(\regs),%r17
1720 LDREG PT_GR18(\regs),%r18
1723 .macro fork_like name
1724 ENTRY_CFI(sys_\name\()_wrapper)
1725 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1726 ldo TASK_REGS(%r1),%r1
1729 ldil L%sys_\name, %r31
1730 be R%sys_\name(%sr4,%r31)
1731 STREG %r28, PT_CR27(%r1)
1732 ENDPROC_CFI(sys_\name\()_wrapper)
1740 /* Set the return value for the child */
1742 BL schedule_tail, %r2
1744 finish_child_return:
1745 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1746 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1748 LDREG PT_CR27(%r1), %r3
1755 ENTRY_CFI(sys_rt_sigreturn_wrapper)
1756 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26
1757 ldo TASK_REGS(%r26),%r26 /* get pt regs */
1758 /* Don't save regs, we are going to restore them from sigcontext. */
1759 STREG %r2, -RP_OFFSET(%r30)
1761 ldo FRAME_SIZE(%r30), %r30
1762 BL sys_rt_sigreturn,%r2
1763 ldo -16(%r30),%r29 /* Reference param save area */
1765 BL sys_rt_sigreturn,%r2
1766 ldo FRAME_SIZE(%r30), %r30
1769 ldo -FRAME_SIZE(%r30), %r30
1770 LDREG -RP_OFFSET(%r30), %r2
1772 /* FIXME: I think we need to restore a few more things here. */
1773 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1774 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1777 /* If the signal was received while the process was blocked on a
1778 * syscall, then r2 will take us to syscall_exit; otherwise r2 will
1779 * take us to syscall_exit_rfi and on to intr_return.
1782 LDREG PT_GR28(%r1),%r28 /* reload original r28 for syscall_exit */
1783 ENDPROC_CFI(sys_rt_sigreturn_wrapper)
1786 /* NOTE: Not all syscalls exit this way. rt_sigreturn will exit
1787 * via syscall_exit_rfi if the signal was received while the process
1791 /* save return value now */
1794 LDREG TI_TASK(%r1),%r1
1795 STREG %r28,TASK_PT_GR28(%r1)
1797 /* Seems to me that dp could be wrong here, if the syscall involved
1798 * calling a module, and nothing got round to restoring dp on return.
1802 syscall_check_resched:
1804 /* check for reschedule */
1806 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19 /* long */
1807 bb,<,n %r19, 31-TIF_NEED_RESCHED, syscall_do_resched /* forward */
1809 .import do_signal,code
1811 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19
1812 ldi (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME), %r26
1813 and,COND(<>) %r19, %r26, %r0
1814 b,n syscall_restore /* skip past if we've nothing to do */
1817 /* Save callee-save registers (for sigcontext).
1818 * FIXME: After this point the process structure should be
1819 * consistent with all the relevant state of the process
1820 * before the syscall. We need to verify this.
1822 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1823 ldo TASK_REGS(%r1), %r26 /* struct pt_regs *regs */
1827 ldo -16(%r30),%r29 /* Reference param save area */
1830 BL do_notify_resume,%r2
1831 ldi 1, %r25 /* long in_syscall = 1 */
1833 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1834 ldo TASK_REGS(%r1), %r20 /* reload pt_regs */
1837 b,n syscall_check_sig
1840 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1842 /* Are we being ptraced? */
1843 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19
1844 ldi _TIF_SINGLESTEP|_TIF_BLOCKSTEP,%r2
1845 and,COND(=) %r19,%r2,%r0
1846 b,n syscall_restore_rfi
1848 ldo TASK_PT_FR31(%r1),%r19 /* reload fpregs */
1851 LDREG TASK_PT_SAR(%r1),%r19 /* restore SAR */
1854 LDREG TASK_PT_GR2(%r1),%r2 /* restore user rp */
1855 LDREG TASK_PT_GR19(%r1),%r19
1856 LDREG TASK_PT_GR20(%r1),%r20
1857 LDREG TASK_PT_GR21(%r1),%r21
1858 LDREG TASK_PT_GR22(%r1),%r22
1859 LDREG TASK_PT_GR23(%r1),%r23
1860 LDREG TASK_PT_GR24(%r1),%r24
1861 LDREG TASK_PT_GR25(%r1),%r25
1862 LDREG TASK_PT_GR26(%r1),%r26
1863 LDREG TASK_PT_GR27(%r1),%r27 /* restore user dp */
1864 LDREG TASK_PT_GR28(%r1),%r28 /* syscall return value */
1865 LDREG TASK_PT_GR29(%r1),%r29
1866 LDREG TASK_PT_GR31(%r1),%r31 /* restore syscall rp */
1868 /* NOTE: We use rsm/ssm pair to make this operation atomic */
1869 LDREG TASK_PT_GR30(%r1),%r1 /* Get user sp */
1871 copy %r1,%r30 /* Restore user sp */
1872 mfsp %sr3,%r1 /* Get user space id */
1873 mtsp %r1,%sr7 /* Restore sr7 */
1876 /* Set sr2 to zero for userspace syscalls to work. */
1878 mtsp %r1,%sr4 /* Restore sr4 */
1879 mtsp %r1,%sr5 /* Restore sr5 */
1880 mtsp %r1,%sr6 /* Restore sr6 */
1882 depi 3,31,2,%r31 /* ensure return to user mode. */
1885 /* decide whether to reset the wide mode bit
1887 * For a syscall, the W bit is stored in the lowest bit
1888 * of sp. Extract it and reset W if it is zero */
1889 extrd,u,*<> %r30,63,1,%r1
1891 /* now reset the lowest bit of sp if it was set */
1894 be,n 0(%sr3,%r31) /* return to user space */
1896 /* We have to return via an RFI, so that PSW T and R bits can be set
1898 * This sets up pt_regs so we can return via intr_restore, which is not
1899 * the most efficient way of doing things, but it works.
1901 syscall_restore_rfi:
1902 ldo -1(%r0),%r2 /* Set recovery cntr to -1 */
1903 mtctl %r2,%cr0 /* for immediate trap */
1904 LDREG TASK_PT_PSW(%r1),%r2 /* Get old PSW */
1905 ldi 0x0b,%r20 /* Create new PSW */
1906 depi -1,13,1,%r20 /* C, Q, D, and I bits */
1908 /* The values of SINGLESTEP_BIT and BLOCKSTEP_BIT are
1909 * set in thread_info.h and converted to PA bitmap
1910 * numbers in asm-offsets.c */
1912 /* if ((%r19.SINGLESTEP_BIT)) { %r20.27=1} */
1913 extru,= %r19,TIF_SINGLESTEP_PA_BIT,1,%r0
1914 depi -1,27,1,%r20 /* R bit */
1916 /* if ((%r19.BLOCKSTEP_BIT)) { %r20.7=1} */
1917 extru,= %r19,TIF_BLOCKSTEP_PA_BIT,1,%r0
1918 depi -1,7,1,%r20 /* T bit */
1920 STREG %r20,TASK_PT_PSW(%r1)
1922 /* Always store space registers, since sr3 can be changed (e.g. fork) */
1925 STREG %r25,TASK_PT_SR3(%r1)
1926 STREG %r25,TASK_PT_SR4(%r1)
1927 STREG %r25,TASK_PT_SR5(%r1)
1928 STREG %r25,TASK_PT_SR6(%r1)
1929 STREG %r25,TASK_PT_SR7(%r1)
1930 STREG %r25,TASK_PT_IASQ0(%r1)
1931 STREG %r25,TASK_PT_IASQ1(%r1)
1934 /* Now if old D bit is clear, it means we didn't save all registers
1935 * on syscall entry, so do that now. This only happens on TRACEME
1936 * calls, or if someone attached to us while we were on a syscall.
1937 * We could make this more efficient by not saving r3-r18, but
1938 * then we wouldn't be able to use the common intr_restore path.
1939 * It is only for traced processes anyway, so performance is not
1942 bb,< %r2,30,pt_regs_ok /* Branch if D set */
1943 ldo TASK_REGS(%r1),%r25
1944 reg_save %r25 /* Save r3 to r18 */
1946 /* Save the current sr */
1948 STREG %r2,TASK_PT_SR0(%r1)
1950 /* Save the scratch sr */
1952 STREG %r2,TASK_PT_SR1(%r1)
1954 /* sr2 should be set to zero for userspace syscalls */
1955 STREG %r0,TASK_PT_SR2(%r1)
1957 LDREG TASK_PT_GR31(%r1),%r2
1958 depi 3,31,2,%r2 /* ensure return to user mode. */
1959 STREG %r2,TASK_PT_IAOQ0(%r1)
1961 STREG %r2,TASK_PT_IAOQ1(%r1)
1966 LDREG TASK_PT_IAOQ0(%r1),%r2
1967 depi 3,31,2,%r2 /* ensure return to user mode. */
1968 STREG %r2,TASK_PT_IAOQ0(%r1)
1969 LDREG TASK_PT_IAOQ1(%r1),%r2
1971 STREG %r2,TASK_PT_IAOQ1(%r1)
1976 load32 syscall_check_resched,%r2 /* if resched, we start over again */
1977 load32 schedule,%r19
1978 bv %r0(%r19) /* jumps to schedule() */
1980 ldo -16(%r30),%r29 /* Reference param save area */
1987 #ifdef CONFIG_FUNCTION_TRACER
1989 .import ftrace_function_trampoline,code
1990 .align L1_CACHE_BYTES
1991 ENTRY_CFI(mcount, caller)
1993 .export _mcount,data
1995 * The 64bit mcount() function pointer needs 4 dwords, of which the
1996 * first two are free. We optimize it here and put 2 instructions for
1997 * calling mcount(), and 2 instructions for ftrace_stub(). That way we
1998 * have all on one L1 cacheline.
2001 b ftrace_function_trampoline
2002 copy %r3, %arg2 /* caller original %sp */
2005 .type ftrace_stub, @function
2014 .dword 0 /* code in head.S puts value of global gp here */
2018 #ifdef CONFIG_DYNAMIC_FTRACE
2021 #define FTRACE_FRAME_SIZE (2*FRAME_SIZE)
2023 #define FTRACE_FRAME_SIZE FRAME_SIZE
2025 ENTRY_CFI(ftrace_caller, caller,frame=FTRACE_FRAME_SIZE,CALLS,SAVE_RP,SAVE_SP)
2027 .global ftrace_caller
2029 STREG %r3, -FTRACE_FRAME_SIZE+1*REG_SZ(%sp)
2030 ldo -FTRACE_FRAME_SIZE(%sp), %r3
2031 STREG %rp, -RP_OFFSET(%r3)
2033 /* Offset 0 is already allocated for %r1 */
2034 STREG %r23, 2*REG_SZ(%r3)
2035 STREG %r24, 3*REG_SZ(%r3)
2036 STREG %r25, 4*REG_SZ(%r3)
2037 STREG %r26, 5*REG_SZ(%r3)
2038 STREG %r28, 6*REG_SZ(%r3)
2039 STREG %r29, 7*REG_SZ(%r3)
2041 STREG %r19, 8*REG_SZ(%r3)
2042 STREG %r20, 9*REG_SZ(%r3)
2043 STREG %r21, 10*REG_SZ(%r3)
2044 STREG %r22, 11*REG_SZ(%r3)
2045 STREG %r27, 12*REG_SZ(%r3)
2046 STREG %r31, 13*REG_SZ(%r3)
2053 ldi 0, %r23 /* no pt_regs */
2054 b,l ftrace_function_trampoline, %rp
2057 LDREG -RP_OFFSET(%r3), %rp
2058 LDREG 2*REG_SZ(%r3), %r23
2059 LDREG 3*REG_SZ(%r3), %r24
2060 LDREG 4*REG_SZ(%r3), %r25
2061 LDREG 5*REG_SZ(%r3), %r26
2062 LDREG 6*REG_SZ(%r3), %r28
2063 LDREG 7*REG_SZ(%r3), %r29
2065 LDREG 8*REG_SZ(%r3), %r19
2066 LDREG 9*REG_SZ(%r3), %r20
2067 LDREG 10*REG_SZ(%r3), %r21
2068 LDREG 11*REG_SZ(%r3), %r22
2069 LDREG 12*REG_SZ(%r3), %r27
2070 LDREG 13*REG_SZ(%r3), %r31
2072 LDREG 1*REG_SZ(%r3), %r3
2074 LDREGM -FTRACE_FRAME_SIZE(%sp), %r1
2075 /* Adjust return point to jump back to beginning of traced function */
2079 ENDPROC_CFI(ftrace_caller)
2081 #ifdef CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS
2082 ENTRY_CFI(ftrace_regs_caller,caller,frame=FTRACE_FRAME_SIZE+PT_SZ_ALGN,
2083 CALLS,SAVE_RP,SAVE_SP)
2085 .global ftrace_regs_caller
2087 ldo -FTRACE_FRAME_SIZE(%sp), %r1
2088 STREG %rp, -RP_OFFSET(%r1)
2091 ldo PT_SZ_ALGN(%sp), %sp
2093 STREG %rp, PT_GR2(%r1)
2094 STREG %r3, PT_GR3(%r1)
2095 STREG %r4, PT_GR4(%r1)
2096 STREG %r5, PT_GR5(%r1)
2097 STREG %r6, PT_GR6(%r1)
2098 STREG %r7, PT_GR7(%r1)
2099 STREG %r8, PT_GR8(%r1)
2100 STREG %r9, PT_GR9(%r1)
2101 STREG %r10, PT_GR10(%r1)
2102 STREG %r11, PT_GR11(%r1)
2103 STREG %r12, PT_GR12(%r1)
2104 STREG %r13, PT_GR13(%r1)
2105 STREG %r14, PT_GR14(%r1)
2106 STREG %r15, PT_GR15(%r1)
2107 STREG %r16, PT_GR16(%r1)
2108 STREG %r17, PT_GR17(%r1)
2109 STREG %r18, PT_GR18(%r1)
2110 STREG %r19, PT_GR19(%r1)
2111 STREG %r20, PT_GR20(%r1)
2112 STREG %r21, PT_GR21(%r1)
2113 STREG %r22, PT_GR22(%r1)
2114 STREG %r23, PT_GR23(%r1)
2115 STREG %r24, PT_GR24(%r1)
2116 STREG %r25, PT_GR25(%r1)
2117 STREG %r26, PT_GR26(%r1)
2118 STREG %r27, PT_GR27(%r1)
2119 STREG %r28, PT_GR28(%r1)
2120 STREG %r29, PT_GR29(%r1)
2121 STREG %r30, PT_GR30(%r1)
2122 STREG %r31, PT_GR31(%r1)
2124 STREG %r26, PT_SAR(%r1)
2127 LDREG -FTRACE_FRAME_SIZE-PT_SZ_ALGN(%sp), %r25
2129 ldo -FTRACE_FRAME_SIZE(%r1), %arg2
2130 b,l ftrace_function_trampoline, %rp
2131 copy %r1, %arg3 /* struct pt_regs */
2133 ldo -PT_SZ_ALGN(%sp), %r1
2135 LDREG PT_SAR(%r1), %rp
2138 LDREG PT_GR2(%r1), %rp
2139 LDREG PT_GR3(%r1), %r3
2140 LDREG PT_GR4(%r1), %r4
2141 LDREG PT_GR5(%r1), %r5
2142 LDREG PT_GR6(%r1), %r6
2143 LDREG PT_GR7(%r1), %r7
2144 LDREG PT_GR8(%r1), %r8
2145 LDREG PT_GR9(%r1), %r9
2146 LDREG PT_GR10(%r1),%r10
2147 LDREG PT_GR11(%r1),%r11
2148 LDREG PT_GR12(%r1),%r12
2149 LDREG PT_GR13(%r1),%r13
2150 LDREG PT_GR14(%r1),%r14
2151 LDREG PT_GR15(%r1),%r15
2152 LDREG PT_GR16(%r1),%r16
2153 LDREG PT_GR17(%r1),%r17
2154 LDREG PT_GR18(%r1),%r18
2155 LDREG PT_GR19(%r1),%r19
2156 LDREG PT_GR20(%r1),%r20
2157 LDREG PT_GR21(%r1),%r21
2158 LDREG PT_GR22(%r1),%r22
2159 LDREG PT_GR23(%r1),%r23
2160 LDREG PT_GR24(%r1),%r24
2161 LDREG PT_GR25(%r1),%r25
2162 LDREG PT_GR26(%r1),%r26
2163 LDREG PT_GR27(%r1),%r27
2164 LDREG PT_GR28(%r1),%r28
2165 LDREG PT_GR29(%r1),%r29
2166 LDREG PT_GR30(%r1),%r30
2167 LDREG PT_GR31(%r1),%r31
2169 ldo -PT_SZ_ALGN(%sp), %sp
2170 LDREGM -FTRACE_FRAME_SIZE(%sp), %r1
2171 /* Adjust return point to jump back to beginning of traced function */
2175 ENDPROC_CFI(ftrace_regs_caller)
2180 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2182 ENTRY_CFI(return_to_handler, caller,frame=FRAME_SIZE)
2183 .export parisc_return_to_handler,data
2184 parisc_return_to_handler:
2186 STREG %r0,-RP_OFFSET(%sp) /* store 0 as %rp */
2188 STREGM %r1,FRAME_SIZE(%sp)
2196 /* call ftrace_return_to_handler(0) */
2197 .import ftrace_return_to_handler,code
2198 load32 ftrace_return_to_handler,%ret0
2199 load32 .Lftrace_ret,%r2
2201 ldo -16(%sp),%ret1 /* Reference param save area */
2210 /* restore original return values */
2214 /* return from function */
2220 LDREGM -FRAME_SIZE(%sp),%r3
2221 ENDPROC_CFI(return_to_handler)
2223 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
2225 #endif /* CONFIG_FUNCTION_TRACER */
2227 #ifdef CONFIG_IRQSTACKS
2228 /* void call_on_stack(unsigned long param1, void *func,
2229 unsigned long new_stack) */
2230 ENTRY_CFI(call_on_stack, FRAME=2*FRAME_SIZE,CALLS,SAVE_RP,SAVE_SP)
2231 ENTRY(_call_on_stack)
2234 /* Regarding the HPPA calling conventions for function pointers,
2235 we assume the PIC register is not changed across call. For
2236 CONFIG_64BIT, the argument pointer is left to point at the
2237 argument region allocated for the call to call_on_stack. */
2239 /* Switch to new stack. We allocate two frames. */
2240 ldo 2*FRAME_SIZE(%arg2), %sp
2241 # ifdef CONFIG_64BIT
2242 /* Save previous stack pointer and return pointer in frame marker */
2243 STREG %rp, -FRAME_SIZE-RP_OFFSET(%sp)
2244 /* Calls always use function descriptor */
2245 LDREG 16(%arg1), %arg1
2247 STREG %r1, -FRAME_SIZE-REG_SZ(%sp)
2248 LDREG -FRAME_SIZE-RP_OFFSET(%sp), %rp
2250 LDREG -FRAME_SIZE-REG_SZ(%sp), %sp
2252 /* Save previous stack pointer and return pointer in frame marker */
2253 STREG %r1, -FRAME_SIZE-REG_SZ(%sp)
2254 STREG %rp, -FRAME_SIZE-RP_OFFSET(%sp)
2255 /* Calls use function descriptor if PLABEL bit is set */
2256 bb,>=,n %arg1, 30, 1f
2258 LDREG 0(%arg1), %arg1
2260 be,l 0(%sr4,%arg1), %sr0, %r31
2262 LDREG -FRAME_SIZE-RP_OFFSET(%sp), %rp
2264 LDREG -FRAME_SIZE-REG_SZ(%sp), %sp
2265 # endif /* CONFIG_64BIT */
2266 ENDPROC_CFI(call_on_stack)
2267 #endif /* CONFIG_IRQSTACKS */
2269 ENTRY_CFI(get_register)
2271 * get_register is used by the non access tlb miss handlers to
2272 * copy the value of the general register specified in r8 into
2273 * r1. This routine can't be used for shadowed registers, since
2274 * the rfir will restore the original value. So, for the shadowed
2275 * registers we put a -1 into r1 to indicate that the register
2276 * should not be used (the register being copied could also have
2277 * a -1 in it, but that is OK, it just means that we will have
2278 * to use the slow path instead).
2282 bv %r0(%r25) /* r0 */
2284 bv %r0(%r25) /* r1 - shadowed */
2286 bv %r0(%r25) /* r2 */
2288 bv %r0(%r25) /* r3 */
2290 bv %r0(%r25) /* r4 */
2292 bv %r0(%r25) /* r5 */
2294 bv %r0(%r25) /* r6 */
2296 bv %r0(%r25) /* r7 */
2298 bv %r0(%r25) /* r8 - shadowed */
2300 bv %r0(%r25) /* r9 - shadowed */
2302 bv %r0(%r25) /* r10 */
2304 bv %r0(%r25) /* r11 */
2306 bv %r0(%r25) /* r12 */
2308 bv %r0(%r25) /* r13 */
2310 bv %r0(%r25) /* r14 */
2312 bv %r0(%r25) /* r15 */
2314 bv %r0(%r25) /* r16 - shadowed */
2316 bv %r0(%r25) /* r17 - shadowed */
2318 bv %r0(%r25) /* r18 */
2320 bv %r0(%r25) /* r19 */
2322 bv %r0(%r25) /* r20 */
2324 bv %r0(%r25) /* r21 */
2326 bv %r0(%r25) /* r22 */
2328 bv %r0(%r25) /* r23 */
2330 bv %r0(%r25) /* r24 - shadowed */
2332 bv %r0(%r25) /* r25 - shadowed */
2334 bv %r0(%r25) /* r26 */
2336 bv %r0(%r25) /* r27 */
2338 bv %r0(%r25) /* r28 */
2340 bv %r0(%r25) /* r29 */
2342 bv %r0(%r25) /* r30 */
2344 bv %r0(%r25) /* r31 */
2346 ENDPROC_CFI(get_register)
2349 ENTRY_CFI(set_register)
2351 * set_register is used by the non access tlb miss handlers to
2352 * copy the value of r1 into the general register specified in
2357 bv %r0(%r25) /* r0 (silly, but it is a place holder) */
2359 bv %r0(%r25) /* r1 */
2361 bv %r0(%r25) /* r2 */
2363 bv %r0(%r25) /* r3 */
2365 bv %r0(%r25) /* r4 */
2367 bv %r0(%r25) /* r5 */
2369 bv %r0(%r25) /* r6 */
2371 bv %r0(%r25) /* r7 */
2373 bv %r0(%r25) /* r8 */
2375 bv %r0(%r25) /* r9 */
2377 bv %r0(%r25) /* r10 */
2379 bv %r0(%r25) /* r11 */
2381 bv %r0(%r25) /* r12 */
2383 bv %r0(%r25) /* r13 */
2385 bv %r0(%r25) /* r14 */
2387 bv %r0(%r25) /* r15 */
2389 bv %r0(%r25) /* r16 */
2391 bv %r0(%r25) /* r17 */
2393 bv %r0(%r25) /* r18 */
2395 bv %r0(%r25) /* r19 */
2397 bv %r0(%r25) /* r20 */
2399 bv %r0(%r25) /* r21 */
2401 bv %r0(%r25) /* r22 */
2403 bv %r0(%r25) /* r23 */
2405 bv %r0(%r25) /* r24 */
2407 bv %r0(%r25) /* r25 */
2409 bv %r0(%r25) /* r26 */
2411 bv %r0(%r25) /* r27 */
2413 bv %r0(%r25) /* r28 */
2415 bv %r0(%r25) /* r29 */
2417 bv %r0(%r25) /* r30 */
2419 bv %r0(%r25) /* r31 */
2421 ENDPROC_CFI(set_register)