arch/parisc/kernel/cache.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
   7  * Copyright (C) 1999 SuSE GmbH Nuernberg
   8  * Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
   9  *
  10  * Cache and TLB management
  11  *
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mm.h>
  17 #include <linux/module.h>
  18 #include <linux/seq_file.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/sched.h>
  21 #include <linux/sched/mm.h>
  22 #include <asm/pdc.h>
  23 #include <asm/cache.h>
  24 #include <asm/cacheflush.h>
  25 #include <asm/tlbflush.h>
  26 #include <asm/page.h>
  27 #include <asm/pgalloc.h>
  28 #include <asm/processor.h>
  29 #include <asm/sections.h>
  30 #include <asm/shmparam.h>
  31
  32 int split_tlb __read_mostly;
  33 int dcache_stride __read_mostly;
  34 int icache_stride __read_mostly;
  35 EXPORT_SYMBOL(dcache_stride);
  36
  37 void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
  38 EXPORT_SYMBOL(flush_dcache_page_asm);
  39 void flush_icache_page_asm(unsigned long phys_addr, unsigned long vaddr);
  40
  41
  42 /* On some machines (e.g. ones with the Merced bus), there can be
  43  * only a single PxTLB broadcast at a time; this must be guaranteed
  44  * by software.  We put a spinlock around all TLB flushes  to
  45  * ensure this.
  46  */
  47 DEFINE_SPINLOCK(pa_tlb_lock);
  48
  49 struct pdc_cache_info cache_info __read_mostly;
  50 #ifndef CONFIG_PA20
  51 static struct pdc_btlb_info btlb_info __read_mostly;
  52 #endif
  53
  54 #ifdef CONFIG_SMP
  55 void
  56 flush_data_cache(void)
  57 {
  58         on_each_cpu(flush_data_cache_local, NULL, 1);
  59 }
  60 void
  61 flush_instruction_cache(void)
  62 {
  63         on_each_cpu(flush_instruction_cache_local, NULL, 1);
  64 }
  65 #endif
  66
  67 void
  68 flush_cache_all_local(void)
  69 {
  70         flush_instruction_cache_local(NULL);
  71         flush_data_cache_local(NULL);
  72 }
  73 EXPORT_SYMBOL(flush_cache_all_local);
  74
  75 /* Virtual address of pfn.  */
  76 #define pfn_va(pfn)     __va(PFN_PHYS(pfn))
  77
  78 void
  79 update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
  80 {
  81         unsigned long pfn = pte_pfn(*ptep);
  82         struct page *page;
  83
  84         /* We don't have pte special.  As a result, we can be called with
  85            an invalid pfn and we don't need to flush the kernel dcache page.
  86            This occurs with FireGL card in C8000.  */
  87         if (!pfn_valid(pfn))
  88                 return;
  89
  90         page = pfn_to_page(pfn);
  91         if (page_mapping_file(page) &&
  92             test_bit(PG_dcache_dirty, &page->flags)) {
  93                 flush_kernel_dcache_page_addr(pfn_va(pfn));
  94                 clear_bit(PG_dcache_dirty, &page->flags);
  95         } else if (parisc_requires_coherency())
  96                 flush_kernel_dcache_page_addr(pfn_va(pfn));
  97 }
  98
  99 void
 100 show_cache_info(struct seq_file *m)
 101 {
 102         char buf[32];
 103
 104         seq_printf(m, "I-cache\t\t: %ld KB\n",
 105                 cache_info.ic_size/1024 );
 106         if (cache_info.dc_loop != 1)
 107                 snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
 108         seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n",
 109                 cache_info.dc_size/1024,
 110                 (cache_info.dc_conf.cc_wt ? "WT":"WB"),
 111                 (cache_info.dc_conf.cc_sh ? ", shared I/D":""),
 112                 ((cache_info.dc_loop == 1) ? "direct mapped" : buf));
 113         seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
 114                 cache_info.it_size,
 115                 cache_info.dt_size,
 116                 cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
 117         );
 118
 119 #ifndef CONFIG_PA20
 120         /* BTLB - Block TLB */
 121         if (btlb_info.max_size==0) {
 122                 seq_printf(m, "BTLB\t\t: not supported\n" );
 123         } else {
 124                 seq_printf(m,
 125                 "BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
 126                 "BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
 127                 "BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
 128                 btlb_info.max_size, (int)4096,
 129                 btlb_info.max_size>>8,
 130                 btlb_info.fixed_range_info.num_i,
 131                 btlb_info.fixed_range_info.num_d,
 132                 btlb_info.fixed_range_info.num_comb,
 133                 btlb_info.variable_range_info.num_i,
 134                 btlb_info.variable_range_info.num_d,
 135                 btlb_info.variable_range_info.num_comb
 136                 );
 137         }
 138 #endif
 139 }
 140
 141 void __init
 142 parisc_cache_init(void)
 143 {
 144         if (pdc_cache_info(&cache_info) < 0)
 145                 panic("parisc_cache_init: pdc_cache_info failed");
 146
 147 #if 0
 148         printk("ic_size %lx dc_size %lx it_size %lx\n",
 149                 cache_info.ic_size,
 150                 cache_info.dc_size,
 151                 cache_info.it_size);
 152
 153         printk("DC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
 154                 cache_info.dc_base,
 155                 cache_info.dc_stride,
 156                 cache_info.dc_count,
 157                 cache_info.dc_loop);
 158
 159         printk("dc_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
 160                 *(unsigned long *) (&cache_info.dc_conf),
 161                 cache_info.dc_conf.cc_alias,
 162                 cache_info.dc_conf.cc_block,
 163                 cache_info.dc_conf.cc_line,
 164                 cache_info.dc_conf.cc_shift);
 165         printk("        wt %d sh %d cst %d hv %d\n",
 166                 cache_info.dc_conf.cc_wt,
 167                 cache_info.dc_conf.cc_sh,
 168                 cache_info.dc_conf.cc_cst,
 169                 cache_info.dc_conf.cc_hv);
 170
 171         printk("IC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
 172                 cache_info.ic_base,
 173                 cache_info.ic_stride,
 174                 cache_info.ic_count,
 175                 cache_info.ic_loop);
 176
 177         printk("IT  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
 178                 cache_info.it_sp_base,
 179                 cache_info.it_sp_stride,
 180                 cache_info.it_sp_count,
 181                 cache_info.it_loop,
 182                 cache_info.it_off_base,
 183                 cache_info.it_off_stride,
 184                 cache_info.it_off_count);
 185
 186         printk("DT  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
 187                 cache_info.dt_sp_base,
 188                 cache_info.dt_sp_stride,
 189                 cache_info.dt_sp_count,
 190                 cache_info.dt_loop,
 191                 cache_info.dt_off_base,
 192                 cache_info.dt_off_stride,
 193                 cache_info.dt_off_count);
 194
 195         printk("ic_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
 196                 *(unsigned long *) (&cache_info.ic_conf),
 197                 cache_info.ic_conf.cc_alias,
 198                 cache_info.ic_conf.cc_block,
 199                 cache_info.ic_conf.cc_line,
 200                 cache_info.ic_conf.cc_shift);
 201         printk("        wt %d sh %d cst %d hv %d\n",
 202                 cache_info.ic_conf.cc_wt,
 203                 cache_info.ic_conf.cc_sh,
 204                 cache_info.ic_conf.cc_cst,
 205                 cache_info.ic_conf.cc_hv);
 206
 207         printk("D-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
 208                 cache_info.dt_conf.tc_sh,
 209                 cache_info.dt_conf.tc_page,
 210                 cache_info.dt_conf.tc_cst,
 211                 cache_info.dt_conf.tc_aid,
 212                 cache_info.dt_conf.tc_sr);
 213
 214         printk("I-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
 215                 cache_info.it_conf.tc_sh,
 216                 cache_info.it_conf.tc_page,
 217                 cache_info.it_conf.tc_cst,
 218                 cache_info.it_conf.tc_aid,
 219                 cache_info.it_conf.tc_sr);
 220 #endif
 221
 222         split_tlb = 0;
 223         if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
 224                 if (cache_info.dt_conf.tc_sh == 2)
 225                         printk(KERN_WARNING "Unexpected TLB configuration. "
 226                         "Will flush I/D separately (could be optimized).\n");
 227
 228                 split_tlb = 1;
 229         }
 230
 231         /* "New and Improved" version from Jim Hull
 232          *      (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
 233          * The following CAFL_STRIDE is an optimized version, see
 234          * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
 235          * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
 236          */
 237 #define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
 238         dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
 239         icache_stride = CAFL_STRIDE(cache_info.ic_conf);
 240 #undef CAFL_STRIDE
 241
 242 #ifndef CONFIG_PA20
 243         if (pdc_btlb_info(&btlb_info) < 0) {
 244                 memset(&btlb_info, 0, sizeof btlb_info);
 245         }
 246 #endif
 247
 248         if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
 249                                                 PDC_MODEL_NVA_UNSUPPORTED) {
 250                 printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
 251 #if 0
 252                 panic("SMP kernel required to avoid non-equivalent aliasing");
 253 #endif
 254         }
 255 }
 256
 257 void __init disable_sr_hashing(void)
 258 {
 259         int srhash_type, retval;
 260         unsigned long space_bits;
 261
 262         switch (boot_cpu_data.cpu_type) {
 263         case pcx: /* We shouldn't get this far.  setup.c should prevent it. */
 264                 BUG();
 265                 return;
 266
 267         case pcxs:
 268         case pcxt:
 269         case pcxt_:
 270                 srhash_type = SRHASH_PCXST;
 271                 break;
 272
 273         case pcxl:
 274                 srhash_type = SRHASH_PCXL;
 275                 break;
 276
 277         case pcxl2: /* pcxl2 doesn't support space register hashing */
 278                 return;
 279
 280         default: /* Currently all PA2.0 machines use the same ins. sequence */
 281                 srhash_type = SRHASH_PA20;
 282                 break;
 283         }
 284
 285         disable_sr_hashing_asm(srhash_type);
 286
 287         retval = pdc_spaceid_bits(&space_bits);
 288         /* If this procedure isn't implemented, don't panic. */
 289         if (retval < 0 && retval != PDC_BAD_OPTION)
 290                 panic("pdc_spaceid_bits call failed.\n");
 291         if (space_bits != 0)
 292                 panic("SpaceID hashing is still on!\n");
 293 }
 294
 295 static inline void
 296 __flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
 297                    unsigned long physaddr)
 298 {
 299         preempt_disable();
 300         flush_dcache_page_asm(physaddr, vmaddr);
 301         if (vma->vm_flags & VM_EXEC)
 302                 flush_icache_page_asm(physaddr, vmaddr);
 303         preempt_enable();
 304 }
 305
 306 void flush_dcache_page(struct page *page)
 307 {
 308         struct address_space *mapping = page_mapping_file(page);
 309         struct vm_area_struct *mpnt;
 310         unsigned long offset;
 311         unsigned long addr, old_addr = 0;
 312         unsigned long flags;
 313         pgoff_t pgoff;
 314
 315         if (mapping && !mapping_mapped(mapping)) {
 316                 set_bit(PG_dcache_dirty, &page->flags);
 317                 return;
 318         }
 319
 320         flush_kernel_dcache_page(page);
 321
 322         if (!mapping)
 323                 return;
 324
 325         pgoff = page->index;
 326
 327         /* We have carefully arranged in arch_get_unmapped_area() that
 328          * *any* mappings of a file are always congruently mapped (whether
 329          * declared as MAP_PRIVATE or MAP_SHARED), so we only need
 330          * to flush one address here for them all to become coherent */
 331
 332         flush_dcache_mmap_lock_irqsave(mapping, flags);
 333         vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
 334                 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
 335                 addr = mpnt->vm_start + offset;
 336
 337                 /* The TLB is the engine of coherence on parisc: The
 338                  * CPU is entitled to speculate any page with a TLB
 339                  * mapping, so here we kill the mapping then flush the
 340                  * page along a special flush only alias mapping.
 341                  * This guarantees that the page is no-longer in the
 342                  * cache for any process and nor may it be
 343                  * speculatively read in (until the user or kernel
 344                  * specifically accesses it, of course) */
 345
 346                 flush_tlb_page(mpnt, addr);
 347                 if (old_addr == 0 || (old_addr & (SHM_COLOUR - 1))
 348                                       != (addr & (SHM_COLOUR - 1))) {
 349                         __flush_cache_page(mpnt, addr, page_to_phys(page));
 350                         if (old_addr)
 351                                 printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %pD\n", old_addr, addr, mpnt->vm_file);
 352                         old_addr = addr;
 353                 }
 354         }
 355         flush_dcache_mmap_unlock_irqrestore(mapping, flags);
 356 }
 357 EXPORT_SYMBOL(flush_dcache_page);
 358
 359 /* Defined in arch/parisc/kernel/pacache.S */
 360 EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
 361 EXPORT_SYMBOL(flush_kernel_dcache_page_asm);
 362 EXPORT_SYMBOL(flush_data_cache_local);
 363 EXPORT_SYMBOL(flush_kernel_icache_range_asm);
 364
 365 #define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
 366 static unsigned long parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;
 367
 368 #define FLUSH_TLB_THRESHOLD (2*1024*1024) /* 2MB initial TLB threshold */
 369 static unsigned long parisc_tlb_flush_threshold __read_mostly = FLUSH_TLB_THRESHOLD;
 370
 371 void __init parisc_setup_cache_timing(void)
 372 {
 373         unsigned long rangetime, alltime;
 374         unsigned long size, start;
 375         unsigned long threshold;
 376
 377         alltime = mfctl(16);
 378         flush_data_cache();
 379         alltime = mfctl(16) - alltime;
 380
 381         size = (unsigned long)(_end - _text);
 382         rangetime = mfctl(16);
 383         flush_kernel_dcache_range((unsigned long)_text, size);
 384         rangetime = mfctl(16) - rangetime;
 385
 386         printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
 387                 alltime, size, rangetime);
 388
 389         threshold = L1_CACHE_ALIGN(size * alltime / rangetime);
 390         if (threshold > cache_info.dc_size)
 391                 threshold = cache_info.dc_size;
 392         if (threshold)
 393                 parisc_cache_flush_threshold = threshold;
 394         printk(KERN_INFO "Cache flush threshold set to %lu KiB\n",
 395                 parisc_cache_flush_threshold/1024);
 396
 397         /* calculate TLB flush threshold */
 398
 399         /* On SMP machines, skip the TLB measure of kernel text which
 400          * has been mapped as huge pages. */
 401         if (num_online_cpus() > 1 && !parisc_requires_coherency()) {
 402                 threshold = max(cache_info.it_size, cache_info.dt_size);
 403                 threshold *= PAGE_SIZE;
 404                 threshold /= num_online_cpus();
 405                 goto set_tlb_threshold;
 406         }
 407
 408         alltime = mfctl(16);
 409         flush_tlb_all();
 410         alltime = mfctl(16) - alltime;
 411
 412         size = 0;
 413         start = (unsigned long) _text;
 414         rangetime = mfctl(16);
 415         while (start < (unsigned long) _end) {
 416                 flush_tlb_kernel_range(start, start + PAGE_SIZE);
 417                 start += PAGE_SIZE;
 418                 size += PAGE_SIZE;
 419         }
 420         rangetime = mfctl(16) - rangetime;
 421
 422         printk(KERN_DEBUG "Whole TLB flush %lu cycles, flushing %lu bytes %lu cycles\n",
 423                 alltime, size, rangetime);
 424
 425         threshold = PAGE_ALIGN(num_online_cpus() * size * alltime / rangetime);
 426
 427 set_tlb_threshold:
 428         if (threshold)
 429                 parisc_tlb_flush_threshold = threshold;
 430         printk(KERN_INFO "TLB flush threshold set to %lu KiB\n",
 431                 parisc_tlb_flush_threshold/1024);
 432 }
 433
 434 extern void purge_kernel_dcache_page_asm(unsigned long);
 435 extern void clear_user_page_asm(void *, unsigned long);
 436 extern void copy_user_page_asm(void *, void *, unsigned long);
 437
 438 void flush_kernel_dcache_page_addr(void *addr)
 439 {
 440         unsigned long flags;
 441
 442         flush_kernel_dcache_page_asm(addr);
 443         purge_tlb_start(flags);
 444         pdtlb_kernel(addr);
 445         purge_tlb_end(flags);
 446 }
 447 EXPORT_SYMBOL(flush_kernel_dcache_page_addr);
 448
 449 void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
 450         struct page *pg)
 451 {
 452        /* Copy using kernel mapping.  No coherency is needed (all in
 453           kunmap) for the `to' page.  However, the `from' page needs to
 454           be flushed through a mapping equivalent to the user mapping
 455           before it can be accessed through the kernel mapping. */
 456         preempt_disable();
 457         flush_dcache_page_asm(__pa(vfrom), vaddr);
 458         copy_page_asm(vto, vfrom);
 459         preempt_enable();
 460 }
 461 EXPORT_SYMBOL(copy_user_page);
 462
 463 /* __flush_tlb_range()
 464  *
 465  * returns 1 if all TLBs were flushed.
 466  */
 467 int __flush_tlb_range(unsigned long sid, unsigned long start,
 468                       unsigned long end)
 469 {
 470         unsigned long flags;
 471
 472         if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
 473             end - start >= parisc_tlb_flush_threshold) {
 474                 flush_tlb_all();
 475                 return 1;
 476         }
 477
 478         /* Purge TLB entries for small ranges using the pdtlb and
 479            pitlb instructions.  These instructions execute locally
 480            but cause a purge request to be broadcast to other TLBs.  */
 481         if (likely(!split_tlb)) {
 482                 while (start < end) {
 483                         purge_tlb_start(flags);
 484                         mtsp(sid, 1);
 485                         pdtlb(start);
 486                         purge_tlb_end(flags);
 487                         start += PAGE_SIZE;
 488                 }
 489                 return 0;
 490         }
 491
 492         /* split TLB case */
 493         while (start < end) {
 494                 purge_tlb_start(flags);
 495                 mtsp(sid, 1);
 496                 pdtlb(start);
 497                 pitlb(start);
 498                 purge_tlb_end(flags);
 499                 start += PAGE_SIZE;
 500         }
 501         return 0;
 502 }
 503
 504 static void cacheflush_h_tmp_function(void *dummy)
 505 {
 506         flush_cache_all_local();
 507 }
 508
 509 void flush_cache_all(void)
 510 {
 511         on_each_cpu(cacheflush_h_tmp_function, NULL, 1);
 512 }
 513
 514 static inline unsigned long mm_total_size(struct mm_struct *mm)
 515 {
 516         struct vm_area_struct *vma;
 517         unsigned long usize = 0;
 518
 519         for (vma = mm->mmap; vma; vma = vma->vm_next)
 520                 usize += vma->vm_end - vma->vm_start;
 521         return usize;
 522 }
 523
 524 static inline pte_t *get_ptep(pgd_t *pgd, unsigned long addr)
 525 {
 526         pte_t *ptep = NULL;
 527
 528         if (!pgd_none(*pgd)) {
 529                 pud_t *pud = pud_offset(pgd, addr);
 530                 if (!pud_none(*pud)) {
 531                         pmd_t *pmd = pmd_offset(pud, addr);
 532                         if (!pmd_none(*pmd))
 533                                 ptep = pte_offset_map(pmd, addr);
 534                 }
 535         }
 536         return ptep;
 537 }
 538
 539 void flush_cache_mm(struct mm_struct *mm)
 540 {
 541         struct vm_area_struct *vma;
 542         pgd_t *pgd;
 543
 544         /* Flushing the whole cache on each cpu takes forever on
 545            rp3440, etc.  So, avoid it if the mm isn't too big.  */
 546         if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
 547             mm_total_size(mm) >= parisc_cache_flush_threshold) {
 548                 if (mm->context)
 549                         flush_tlb_all();
 550                 flush_cache_all();
 551                 return;
 552         }
 553
 554         if (mm->context == mfsp(3)) {
 555                 for (vma = mm->mmap; vma; vma = vma->vm_next) {
 556                         flush_user_dcache_range_asm(vma->vm_start, vma->vm_end);
 557                         if (vma->vm_flags & VM_EXEC)
 558                                 flush_user_icache_range_asm(vma->vm_start, vma->vm_end);
 559                         flush_tlb_range(vma, vma->vm_start, vma->vm_end);
 560                 }
 561                 return;
 562         }
 563
 564         pgd = mm->pgd;
 565         for (vma = mm->mmap; vma; vma = vma->vm_next) {
 566                 unsigned long addr;
 567
 568                 for (addr = vma->vm_start; addr < vma->vm_end;
 569                      addr += PAGE_SIZE) {
 570                         unsigned long pfn;
 571                         pte_t *ptep = get_ptep(pgd, addr);
 572                         if (!ptep)
 573                                 continue;
 574                         pfn = pte_pfn(*ptep);
 575                         if (!pfn_valid(pfn))
 576                                 continue;
 577                         if (unlikely(mm->context))
 578                                 flush_tlb_page(vma, addr);
 579                         __flush_cache_page(vma, addr, PFN_PHYS(pfn));
 580                 }
 581         }
 582 }
 583
 584 void flush_cache_range(struct vm_area_struct *vma,
 585                 unsigned long start, unsigned long end)
 586 {
 587         pgd_t *pgd;
 588         unsigned long addr;
 589
 590         if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
 591             end - start >= parisc_cache_flush_threshold) {
 592                 if (vma->vm_mm->context)
 593                         flush_tlb_range(vma, start, end);
 594                 flush_cache_all();
 595                 return;
 596         }
 597
 598         if (vma->vm_mm->context == mfsp(3)) {
 599                 flush_user_dcache_range_asm(start, end);
 600                 if (vma->vm_flags & VM_EXEC)
 601                         flush_user_icache_range_asm(start, end);
 602                 flush_tlb_range(vma, start, end);
 603                 return;
 604         }
 605
 606         pgd = vma->vm_mm->pgd;
 607         for (addr = vma->vm_start; addr < vma->vm_end; addr += PAGE_SIZE) {
 608                 unsigned long pfn;
 609                 pte_t *ptep = get_ptep(pgd, addr);
 610                 if (!ptep)
 611                         continue;
 612                 pfn = pte_pfn(*ptep);
 613                 if (pfn_valid(pfn)) {
 614                         if (unlikely(vma->vm_mm->context))
 615                                 flush_tlb_page(vma, addr);
 616                         __flush_cache_page(vma, addr, PFN_PHYS(pfn));
 617                 }
 618         }
 619 }
 620
 621 void
 622 flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
 623 {
 624         if (pfn_valid(pfn)) {
 625                 if (likely(vma->vm_mm->context))
 626                         flush_tlb_page(vma, vmaddr);
 627                 __flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
 628         }
 629 }
 630
 631 void flush_kernel_vmap_range(void *vaddr, int size)
 632 {
 633         unsigned long start = (unsigned long)vaddr;
 634         unsigned long end = start + size;
 635
 636         if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
 637             (unsigned long)size >= parisc_cache_flush_threshold) {
 638                 flush_tlb_kernel_range(start, end);
 639                 flush_data_cache();
 640                 return;
 641         }
 642
 643         flush_kernel_dcache_range_asm(start, end);
 644         flush_tlb_kernel_range(start, end);
 645 }
 646 EXPORT_SYMBOL(flush_kernel_vmap_range);
 647
 648 void invalidate_kernel_vmap_range(void *vaddr, int size)
 649 {
 650         unsigned long start = (unsigned long)vaddr;
 651         unsigned long end = start + size;
 652
 653         if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
 654             (unsigned long)size >= parisc_cache_flush_threshold) {
 655                 flush_tlb_kernel_range(start, end);
 656                 flush_data_cache();
 657                 return;
 658         }
 659
 660         purge_kernel_dcache_range_asm(start, end);
 661         flush_tlb_kernel_range(start, end);
 662 }
 663 EXPORT_SYMBOL(invalidate_kernel_vmap_range);