2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
7 * Copyright (C) 1999 SuSE GmbH Nuernberg
8 * Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
10 * Cache and TLB management
14 #include <linux/init.h>
15 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/seq_file.h>
19 #include <linux/pagemap.h>
20 #include <linux/sched.h>
21 #include <linux/sched/mm.h>
23 #include <asm/cache.h>
24 #include <asm/cacheflush.h>
25 #include <asm/tlbflush.h>
27 #include <asm/processor.h>
28 #include <asm/sections.h>
29 #include <asm/shmparam.h>
30 #include <asm/mmu_context.h>
32 int split_tlb __ro_after_init;
33 int dcache_stride __ro_after_init;
34 int icache_stride __ro_after_init;
35 EXPORT_SYMBOL(dcache_stride);
37 void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
38 EXPORT_SYMBOL(flush_dcache_page_asm);
39 void purge_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
40 void flush_icache_page_asm(unsigned long phys_addr, unsigned long vaddr);
42 /* Internal implementation in arch/parisc/kernel/pacache.S */
43 void flush_data_cache_local(void *); /* flushes local data-cache only */
44 void flush_instruction_cache_local(void); /* flushes local code-cache only */
46 /* On some machines (i.e., ones with the Merced bus), there can be
47 * only a single PxTLB broadcast at a time; this must be guaranteed
48 * by software. We need a spinlock around all TLB flushes to ensure
51 DEFINE_SPINLOCK(pa_tlb_flush_lock);
53 #if defined(CONFIG_64BIT) && defined(CONFIG_SMP)
54 int pa_serialize_tlb_flushes __ro_after_init;
57 struct pdc_cache_info cache_info __ro_after_init;
59 static struct pdc_btlb_info btlb_info __ro_after_init;
62 DEFINE_STATIC_KEY_TRUE(parisc_has_cache);
63 DEFINE_STATIC_KEY_TRUE(parisc_has_dcache);
64 DEFINE_STATIC_KEY_TRUE(parisc_has_icache);
66 static void cache_flush_local_cpu(void *dummy)
68 if (static_branch_likely(&parisc_has_icache))
69 flush_instruction_cache_local();
70 if (static_branch_likely(&parisc_has_dcache))
71 flush_data_cache_local(NULL);
74 void flush_cache_all_local(void)
76 cache_flush_local_cpu(NULL);
79 void flush_cache_all(void)
81 if (static_branch_likely(&parisc_has_cache))
82 on_each_cpu(cache_flush_local_cpu, NULL, 1);
85 static inline void flush_data_cache(void)
87 if (static_branch_likely(&parisc_has_dcache))
88 on_each_cpu(flush_data_cache_local, NULL, 1);
92 /* Kernel virtual address of pfn. */
93 #define pfn_va(pfn) __va(PFN_PHYS(pfn))
96 __update_cache(pte_t pte)
98 unsigned long pfn = pte_pfn(pte);
101 /* We don't have pte special. As a result, we can be called with
102 an invalid pfn and we don't need to flush the kernel dcache page.
103 This occurs with FireGL card in C8000. */
107 page = pfn_to_page(pfn);
108 if (page_mapping_file(page) &&
109 test_bit(PG_dcache_dirty, &page->flags)) {
110 flush_kernel_dcache_page_addr(pfn_va(pfn));
111 clear_bit(PG_dcache_dirty, &page->flags);
112 } else if (parisc_requires_coherency())
113 flush_kernel_dcache_page_addr(pfn_va(pfn));
117 show_cache_info(struct seq_file *m)
121 seq_printf(m, "I-cache\t\t: %ld KB\n",
122 cache_info.ic_size/1024 );
123 if (cache_info.dc_loop != 1)
124 snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
125 seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s, alias=%d)\n",
126 cache_info.dc_size/1024,
127 (cache_info.dc_conf.cc_wt ? "WT":"WB"),
128 (cache_info.dc_conf.cc_sh ? ", shared I/D":""),
129 ((cache_info.dc_loop == 1) ? "direct mapped" : buf),
130 cache_info.dc_conf.cc_alias
132 seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
135 cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
139 /* BTLB - Block TLB */
140 if (btlb_info.max_size==0) {
141 seq_printf(m, "BTLB\t\t: not supported\n" );
144 "BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
145 "BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
146 "BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
147 btlb_info.max_size, (int)4096,
148 btlb_info.max_size>>8,
149 btlb_info.fixed_range_info.num_i,
150 btlb_info.fixed_range_info.num_d,
151 btlb_info.fixed_range_info.num_comb,
152 btlb_info.variable_range_info.num_i,
153 btlb_info.variable_range_info.num_d,
154 btlb_info.variable_range_info.num_comb
161 parisc_cache_init(void)
163 if (pdc_cache_info(&cache_info) < 0)
164 panic("parisc_cache_init: pdc_cache_info failed");
167 printk("ic_size %lx dc_size %lx it_size %lx\n",
172 printk("DC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
174 cache_info.dc_stride,
178 printk("dc_conf = 0x%lx alias %d blk %d line %d shift %d\n",
179 *(unsigned long *) (&cache_info.dc_conf),
180 cache_info.dc_conf.cc_alias,
181 cache_info.dc_conf.cc_block,
182 cache_info.dc_conf.cc_line,
183 cache_info.dc_conf.cc_shift);
184 printk(" wt %d sh %d cst %d hv %d\n",
185 cache_info.dc_conf.cc_wt,
186 cache_info.dc_conf.cc_sh,
187 cache_info.dc_conf.cc_cst,
188 cache_info.dc_conf.cc_hv);
190 printk("IC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
192 cache_info.ic_stride,
196 printk("IT base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
197 cache_info.it_sp_base,
198 cache_info.it_sp_stride,
199 cache_info.it_sp_count,
201 cache_info.it_off_base,
202 cache_info.it_off_stride,
203 cache_info.it_off_count);
205 printk("DT base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
206 cache_info.dt_sp_base,
207 cache_info.dt_sp_stride,
208 cache_info.dt_sp_count,
210 cache_info.dt_off_base,
211 cache_info.dt_off_stride,
212 cache_info.dt_off_count);
214 printk("ic_conf = 0x%lx alias %d blk %d line %d shift %d\n",
215 *(unsigned long *) (&cache_info.ic_conf),
216 cache_info.ic_conf.cc_alias,
217 cache_info.ic_conf.cc_block,
218 cache_info.ic_conf.cc_line,
219 cache_info.ic_conf.cc_shift);
220 printk(" wt %d sh %d cst %d hv %d\n",
221 cache_info.ic_conf.cc_wt,
222 cache_info.ic_conf.cc_sh,
223 cache_info.ic_conf.cc_cst,
224 cache_info.ic_conf.cc_hv);
226 printk("D-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
227 cache_info.dt_conf.tc_sh,
228 cache_info.dt_conf.tc_page,
229 cache_info.dt_conf.tc_cst,
230 cache_info.dt_conf.tc_aid,
231 cache_info.dt_conf.tc_sr);
233 printk("I-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
234 cache_info.it_conf.tc_sh,
235 cache_info.it_conf.tc_page,
236 cache_info.it_conf.tc_cst,
237 cache_info.it_conf.tc_aid,
238 cache_info.it_conf.tc_sr);
242 if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
243 if (cache_info.dt_conf.tc_sh == 2)
244 printk(KERN_WARNING "Unexpected TLB configuration. "
245 "Will flush I/D separately (could be optimized).\n");
250 /* "New and Improved" version from Jim Hull
251 * (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
252 * The following CAFL_STRIDE is an optimized version, see
253 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
254 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
256 #define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
257 dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
258 icache_stride = CAFL_STRIDE(cache_info.ic_conf);
262 if (pdc_btlb_info(&btlb_info) < 0) {
263 memset(&btlb_info, 0, sizeof btlb_info);
267 if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
268 PDC_MODEL_NVA_UNSUPPORTED) {
269 printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
271 panic("SMP kernel required to avoid non-equivalent aliasing");
276 void disable_sr_hashing(void)
278 int srhash_type, retval;
279 unsigned long space_bits;
281 switch (boot_cpu_data.cpu_type) {
282 case pcx: /* We shouldn't get this far. setup.c should prevent it. */
289 srhash_type = SRHASH_PCXST;
293 srhash_type = SRHASH_PCXL;
296 case pcxl2: /* pcxl2 doesn't support space register hashing */
299 default: /* Currently all PA2.0 machines use the same ins. sequence */
300 srhash_type = SRHASH_PA20;
304 disable_sr_hashing_asm(srhash_type);
306 retval = pdc_spaceid_bits(&space_bits);
307 /* If this procedure isn't implemented, don't panic. */
308 if (retval < 0 && retval != PDC_BAD_OPTION)
309 panic("pdc_spaceid_bits call failed.\n");
311 panic("SpaceID hashing is still on!\n");
315 __flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
316 unsigned long physaddr)
318 if (!static_branch_likely(&parisc_has_cache))
321 flush_dcache_page_asm(physaddr, vmaddr);
322 if (vma->vm_flags & VM_EXEC)
323 flush_icache_page_asm(physaddr, vmaddr);
327 static void flush_user_cache_page(struct vm_area_struct *vma, unsigned long vmaddr)
329 unsigned long flags, space, pgd, prot;
330 #ifdef CONFIG_TLB_PTLOCK
331 unsigned long pgd_lock;
338 /* Set context for flush */
339 local_irq_save(flags);
341 space = mfsp(SR_USER);
343 #ifdef CONFIG_TLB_PTLOCK
344 pgd_lock = mfctl(28);
346 switch_mm_irqs_off(NULL, vma->vm_mm, NULL);
347 local_irq_restore(flags);
349 flush_user_dcache_range_asm(vmaddr, vmaddr + PAGE_SIZE);
350 if (vma->vm_flags & VM_EXEC)
351 flush_user_icache_range_asm(vmaddr, vmaddr + PAGE_SIZE);
352 flush_tlb_page(vma, vmaddr);
354 /* Restore previous context */
355 local_irq_save(flags);
356 #ifdef CONFIG_TLB_PTLOCK
360 mtsp(space, SR_USER);
362 local_irq_restore(flags);
367 static inline pte_t *get_ptep(struct mm_struct *mm, unsigned long addr)
370 pgd_t *pgd = mm->pgd;
375 if (!pgd_none(*pgd)) {
376 p4d = p4d_offset(pgd, addr);
377 if (!p4d_none(*p4d)) {
378 pud = pud_offset(p4d, addr);
379 if (!pud_none(*pud)) {
380 pmd = pmd_offset(pud, addr);
382 ptep = pte_offset_map(pmd, addr);
389 static inline bool pte_needs_flush(pte_t pte)
391 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_NO_CACHE))
392 == (_PAGE_PRESENT | _PAGE_ACCESSED);
395 void flush_dcache_page(struct page *page)
397 struct address_space *mapping = page_mapping_file(page);
398 struct vm_area_struct *mpnt;
399 unsigned long offset;
400 unsigned long addr, old_addr = 0;
401 unsigned long count = 0;
405 if (mapping && !mapping_mapped(mapping)) {
406 set_bit(PG_dcache_dirty, &page->flags);
410 flush_kernel_dcache_page_addr(page_address(page));
418 * We have carefully arranged in arch_get_unmapped_area() that
419 * *any* mappings of a file are always congruently mapped (whether
420 * declared as MAP_PRIVATE or MAP_SHARED), so we only need
421 * to flush one address here for them all to become coherent
422 * on machines that support equivalent aliasing
424 flush_dcache_mmap_lock_irqsave(mapping, flags);
425 vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
426 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
427 addr = mpnt->vm_start + offset;
428 if (parisc_requires_coherency()) {
431 ptep = get_ptep(mpnt->vm_mm, addr);
432 if (ptep && pte_needs_flush(*ptep))
433 flush_user_cache_page(mpnt, addr);
436 * The TLB is the engine of coherence on parisc:
437 * The CPU is entitled to speculate any page
438 * with a TLB mapping, so here we kill the
439 * mapping then flush the page along a special
440 * flush only alias mapping. This guarantees that
441 * the page is no-longer in the cache for any
442 * process and nor may it be speculatively read
443 * in (until the user or kernel specifically
444 * accesses it, of course)
446 flush_tlb_page(mpnt, addr);
447 if (old_addr == 0 || (old_addr & (SHM_COLOUR - 1))
448 != (addr & (SHM_COLOUR - 1))) {
449 __flush_cache_page(mpnt, addr, page_to_phys(page));
451 * Software is allowed to have any number
452 * of private mappings to a page.
454 if (!(mpnt->vm_flags & VM_SHARED))
457 pr_err("INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %pD\n",
458 old_addr, addr, mpnt->vm_file);
462 WARN_ON(++count == 4096);
464 flush_dcache_mmap_unlock_irqrestore(mapping, flags);
466 EXPORT_SYMBOL(flush_dcache_page);
468 /* Defined in arch/parisc/kernel/pacache.S */
469 EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
470 EXPORT_SYMBOL(flush_kernel_icache_range_asm);
472 #define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
473 static unsigned long parisc_cache_flush_threshold __ro_after_init = FLUSH_THRESHOLD;
475 #define FLUSH_TLB_THRESHOLD (16*1024) /* 16 KiB minimum TLB threshold */
476 static unsigned long parisc_tlb_flush_threshold __ro_after_init = ~0UL;
478 void __init parisc_setup_cache_timing(void)
480 unsigned long rangetime, alltime;
482 unsigned long threshold, threshold2;
486 alltime = mfctl(16) - alltime;
488 size = (unsigned long)(_end - _text);
489 rangetime = mfctl(16);
490 flush_kernel_dcache_range((unsigned long)_text, size);
491 rangetime = mfctl(16) - rangetime;
493 printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
494 alltime, size, rangetime);
496 threshold = L1_CACHE_ALIGN((unsigned long)((uint64_t)size * alltime / rangetime));
497 pr_info("Calculated flush threshold is %lu KiB\n",
501 * The threshold computed above isn't very reliable. The following
502 * heuristic works reasonably well on c8000/rp3440.
504 threshold2 = cache_info.dc_size * num_online_cpus();
505 parisc_cache_flush_threshold = threshold2;
506 printk(KERN_INFO "Cache flush threshold set to %lu KiB\n",
507 parisc_cache_flush_threshold/1024);
509 /* calculate TLB flush threshold */
511 /* On SMP machines, skip the TLB measure of kernel text which
512 * has been mapped as huge pages. */
513 if (num_online_cpus() > 1 && !parisc_requires_coherency()) {
514 threshold = max(cache_info.it_size, cache_info.dt_size);
515 threshold *= PAGE_SIZE;
516 threshold /= num_online_cpus();
517 goto set_tlb_threshold;
520 size = (unsigned long)_end - (unsigned long)_text;
521 rangetime = mfctl(16);
522 flush_tlb_kernel_range((unsigned long)_text, (unsigned long)_end);
523 rangetime = mfctl(16) - rangetime;
527 alltime = mfctl(16) - alltime;
529 printk(KERN_INFO "Whole TLB flush %lu cycles, Range flush %lu bytes %lu cycles\n",
530 alltime, size, rangetime);
532 threshold = PAGE_ALIGN((num_online_cpus() * size * alltime) / rangetime);
533 printk(KERN_INFO "Calculated TLB flush threshold %lu KiB\n",
537 if (threshold > FLUSH_TLB_THRESHOLD)
538 parisc_tlb_flush_threshold = threshold;
540 parisc_tlb_flush_threshold = FLUSH_TLB_THRESHOLD;
542 printk(KERN_INFO "TLB flush threshold set to %lu KiB\n",
543 parisc_tlb_flush_threshold/1024);
546 extern void purge_kernel_dcache_page_asm(unsigned long);
547 extern void clear_user_page_asm(void *, unsigned long);
548 extern void copy_user_page_asm(void *, void *, unsigned long);
550 void flush_kernel_dcache_page_addr(const void *addr)
554 flush_kernel_dcache_page_asm(addr);
555 purge_tlb_start(flags);
556 pdtlb(SR_KERNEL, addr);
557 purge_tlb_end(flags);
559 EXPORT_SYMBOL(flush_kernel_dcache_page_addr);
561 static void flush_cache_page_if_present(struct vm_area_struct *vma,
562 unsigned long vmaddr, unsigned long pfn)
564 pte_t *ptep = get_ptep(vma->vm_mm, vmaddr);
567 * The pte check is racy and sometimes the flush will trigger
568 * a non-access TLB miss. Hopefully, the page has already been
571 if (ptep && pte_needs_flush(*ptep))
572 flush_cache_page(vma, vmaddr, pfn);
575 void copy_user_highpage(struct page *to, struct page *from,
576 unsigned long vaddr, struct vm_area_struct *vma)
580 kfrom = kmap_local_page(from);
581 kto = kmap_local_page(to);
582 flush_cache_page_if_present(vma, vaddr, page_to_pfn(from));
583 copy_page_asm(kto, kfrom);
588 void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
589 unsigned long user_vaddr, void *dst, void *src, int len)
591 flush_cache_page_if_present(vma, user_vaddr, page_to_pfn(page));
592 memcpy(dst, src, len);
593 flush_kernel_dcache_range_asm((unsigned long)dst, (unsigned long)dst + len);
596 void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
597 unsigned long user_vaddr, void *dst, void *src, int len)
599 flush_cache_page_if_present(vma, user_vaddr, page_to_pfn(page));
600 memcpy(dst, src, len);
603 /* __flush_tlb_range()
605 * returns 1 if all TLBs were flushed.
607 int __flush_tlb_range(unsigned long sid, unsigned long start,
612 if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
613 end - start >= parisc_tlb_flush_threshold) {
618 /* Purge TLB entries for small ranges using the pdtlb and
619 pitlb instructions. These instructions execute locally
620 but cause a purge request to be broadcast to other TLBs. */
621 while (start < end) {
622 purge_tlb_start(flags);
624 pdtlb(SR_TEMP1, start);
625 pitlb(SR_TEMP1, start);
626 purge_tlb_end(flags);
632 static void flush_cache_pages(struct vm_area_struct *vma, unsigned long start, unsigned long end)
634 unsigned long addr, pfn;
637 for (addr = start; addr < end; addr += PAGE_SIZE) {
639 * The vma can contain pages that aren't present. Although
640 * the pte search is expensive, we need the pte to find the
641 * page pfn and to check whether the page should be flushed.
643 ptep = get_ptep(vma->vm_mm, addr);
644 if (ptep && pte_needs_flush(*ptep)) {
645 if (parisc_requires_coherency()) {
646 flush_user_cache_page(vma, addr);
648 pfn = pte_pfn(*ptep);
649 if (WARN_ON(!pfn_valid(pfn)))
651 __flush_cache_page(vma, addr, PFN_PHYS(pfn));
657 static inline unsigned long mm_total_size(struct mm_struct *mm)
659 struct vm_area_struct *vma;
660 unsigned long usize = 0;
661 VMA_ITERATOR(vmi, mm, 0);
663 for_each_vma(vmi, vma) {
664 if (usize >= parisc_cache_flush_threshold)
666 usize += vma->vm_end - vma->vm_start;
671 void flush_cache_mm(struct mm_struct *mm)
673 struct vm_area_struct *vma;
674 VMA_ITERATOR(vmi, mm, 0);
677 * Flushing the whole cache on each cpu takes forever on
678 * rp3440, etc. So, avoid it if the mm isn't too big.
680 * Note that we must flush the entire cache on machines
681 * with aliasing caches to prevent random segmentation
684 if (!parisc_requires_coherency()
685 || mm_total_size(mm) >= parisc_cache_flush_threshold) {
686 if (WARN_ON(IS_ENABLED(CONFIG_SMP) && arch_irqs_disabled()))
694 for_each_vma(vmi, vma)
695 flush_cache_pages(vma, vma->vm_start, vma->vm_end);
698 void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
700 if (!parisc_requires_coherency()
701 || end - start >= parisc_cache_flush_threshold) {
702 if (WARN_ON(IS_ENABLED(CONFIG_SMP) && arch_irqs_disabled()))
704 flush_tlb_range(vma, start, end);
709 flush_cache_pages(vma, start, end);
712 void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
714 if (WARN_ON(!pfn_valid(pfn)))
716 if (parisc_requires_coherency())
717 flush_user_cache_page(vma, vmaddr);
719 __flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
722 void flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr)
727 if (parisc_requires_coherency()) {
728 if (vma->vm_flags & VM_SHARED)
731 flush_user_cache_page(vma, vmaddr);
735 flush_tlb_page(vma, vmaddr);
737 flush_dcache_page_asm(page_to_phys(page), vmaddr);
741 void flush_kernel_vmap_range(void *vaddr, int size)
743 unsigned long start = (unsigned long)vaddr;
744 unsigned long end = start + size;
746 if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
747 (unsigned long)size >= parisc_cache_flush_threshold) {
748 flush_tlb_kernel_range(start, end);
753 flush_kernel_dcache_range_asm(start, end);
754 flush_tlb_kernel_range(start, end);
756 EXPORT_SYMBOL(flush_kernel_vmap_range);
758 void invalidate_kernel_vmap_range(void *vaddr, int size)
760 unsigned long start = (unsigned long)vaddr;
761 unsigned long end = start + size;
763 /* Ensure DMA is complete */
766 if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
767 (unsigned long)size >= parisc_cache_flush_threshold) {
768 flush_tlb_kernel_range(start, end);
773 purge_kernel_dcache_range_asm(start, end);
774 flush_tlb_kernel_range(start, end);
776 EXPORT_SYMBOL(invalidate_kernel_vmap_range);