arch/parisc/kernel/cache.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
   7  * Copyright (C) 1999 SuSE GmbH Nuernberg
   8  * Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
   9  *
  10  * Cache and TLB management
  11  *
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mm.h>
  17 #include <linux/module.h>
  18 #include <linux/seq_file.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/sched.h>
  21 #include <linux/sched/mm.h>
  22 #include <asm/pdc.h>
  23 #include <asm/cache.h>
  24 #include <asm/cacheflush.h>
  25 #include <asm/tlbflush.h>
  26 #include <asm/page.h>
  27 #include <asm/processor.h>
  28 #include <asm/sections.h>
  29 #include <asm/shmparam.h>
  30
  31 int split_tlb __ro_after_init;
  32 int dcache_stride __ro_after_init;
  33 int icache_stride __ro_after_init;
  34 EXPORT_SYMBOL(dcache_stride);
  35
  36 void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
  37 EXPORT_SYMBOL(flush_dcache_page_asm);
  38 void purge_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
  39 void flush_icache_page_asm(unsigned long phys_addr, unsigned long vaddr);
  40
  41
  42 /* On some machines (i.e., ones with the Merced bus), there can be
  43  * only a single PxTLB broadcast at a time; this must be guaranteed
  44  * by software. We need a spinlock around all TLB flushes to ensure
  45  * this.
  46  */
  47 DEFINE_SPINLOCK(pa_tlb_flush_lock);
  48
  49 #if defined(CONFIG_64BIT) && defined(CONFIG_SMP)
  50 int pa_serialize_tlb_flushes __ro_after_init;
  51 #endif
  52
  53 struct pdc_cache_info cache_info __ro_after_init;
  54 #ifndef CONFIG_PA20
  55 static struct pdc_btlb_info btlb_info __ro_after_init;
  56 #endif
  57
  58 #ifdef CONFIG_SMP
  59 void
  60 flush_data_cache(void)
  61 {
  62         on_each_cpu(flush_data_cache_local, NULL, 1);
  63 }
  64 void
  65 flush_instruction_cache(void)
  66 {
  67         on_each_cpu(flush_instruction_cache_local, NULL, 1);
  68 }
  69 #endif
  70
  71 void
  72 flush_cache_all_local(void)
  73 {
  74         flush_instruction_cache_local(NULL);
  75         flush_data_cache_local(NULL);
  76 }
  77 EXPORT_SYMBOL(flush_cache_all_local);
  78
  79 /* Virtual address of pfn.  */
  80 #define pfn_va(pfn)     __va(PFN_PHYS(pfn))
  81
  82 void
  83 __update_cache(pte_t pte)
  84 {
  85         unsigned long pfn = pte_pfn(pte);
  86         struct page *page;
  87
  88         /* We don't have pte special.  As a result, we can be called with
  89            an invalid pfn and we don't need to flush the kernel dcache page.
  90            This occurs with FireGL card in C8000.  */
  91         if (!pfn_valid(pfn))
  92                 return;
  93
  94         page = pfn_to_page(pfn);
  95         if (page_mapping_file(page) &&
  96             test_bit(PG_dcache_dirty, &page->flags)) {
  97                 flush_kernel_dcache_page_addr(pfn_va(pfn));
  98                 clear_bit(PG_dcache_dirty, &page->flags);
  99         } else if (parisc_requires_coherency())
 100                 flush_kernel_dcache_page_addr(pfn_va(pfn));
 101 }
 102
 103 void
 104 show_cache_info(struct seq_file *m)
 105 {
 106         char buf[32];
 107
 108         seq_printf(m, "I-cache\t\t: %ld KB\n",
 109                 cache_info.ic_size/1024 );
 110         if (cache_info.dc_loop != 1)
 111                 snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
 112         seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n",
 113                 cache_info.dc_size/1024,
 114                 (cache_info.dc_conf.cc_wt ? "WT":"WB"),
 115                 (cache_info.dc_conf.cc_sh ? ", shared I/D":""),
 116                 ((cache_info.dc_loop == 1) ? "direct mapped" : buf));
 117         seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
 118                 cache_info.it_size,
 119                 cache_info.dt_size,
 120                 cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
 121         );
 122
 123 #ifndef CONFIG_PA20
 124         /* BTLB - Block TLB */
 125         if (btlb_info.max_size==0) {
 126                 seq_printf(m, "BTLB\t\t: not supported\n" );
 127         } else {
 128                 seq_printf(m,
 129                 "BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
 130                 "BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
 131                 "BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
 132                 btlb_info.max_size, (int)4096,
 133                 btlb_info.max_size>>8,
 134                 btlb_info.fixed_range_info.num_i,
 135                 btlb_info.fixed_range_info.num_d,
 136                 btlb_info.fixed_range_info.num_comb,
 137                 btlb_info.variable_range_info.num_i,
 138                 btlb_info.variable_range_info.num_d,
 139                 btlb_info.variable_range_info.num_comb
 140                 );
 141         }
 142 #endif
 143 }
 144
 145 void __init
 146 parisc_cache_init(void)
 147 {
 148         if (pdc_cache_info(&cache_info) < 0)
 149                 panic("parisc_cache_init: pdc_cache_info failed");
 150
 151 #if 0
 152         printk("ic_size %lx dc_size %lx it_size %lx\n",
 153                 cache_info.ic_size,
 154                 cache_info.dc_size,
 155                 cache_info.it_size);
 156
 157         printk("DC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
 158                 cache_info.dc_base,
 159                 cache_info.dc_stride,
 160                 cache_info.dc_count,
 161                 cache_info.dc_loop);
 162
 163         printk("dc_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
 164                 *(unsigned long *) (&cache_info.dc_conf),
 165                 cache_info.dc_conf.cc_alias,
 166                 cache_info.dc_conf.cc_block,
 167                 cache_info.dc_conf.cc_line,
 168                 cache_info.dc_conf.cc_shift);
 169         printk("        wt %d sh %d cst %d hv %d\n",
 170                 cache_info.dc_conf.cc_wt,
 171                 cache_info.dc_conf.cc_sh,
 172                 cache_info.dc_conf.cc_cst,
 173                 cache_info.dc_conf.cc_hv);
 174
 175         printk("IC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
 176                 cache_info.ic_base,
 177                 cache_info.ic_stride,
 178                 cache_info.ic_count,
 179                 cache_info.ic_loop);
 180
 181         printk("IT  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
 182                 cache_info.it_sp_base,
 183                 cache_info.it_sp_stride,
 184                 cache_info.it_sp_count,
 185                 cache_info.it_loop,
 186                 cache_info.it_off_base,
 187                 cache_info.it_off_stride,
 188                 cache_info.it_off_count);
 189
 190         printk("DT  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
 191                 cache_info.dt_sp_base,
 192                 cache_info.dt_sp_stride,
 193                 cache_info.dt_sp_count,
 194                 cache_info.dt_loop,
 195                 cache_info.dt_off_base,
 196                 cache_info.dt_off_stride,
 197                 cache_info.dt_off_count);
 198
 199         printk("ic_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
 200                 *(unsigned long *) (&cache_info.ic_conf),
 201                 cache_info.ic_conf.cc_alias,
 202                 cache_info.ic_conf.cc_block,
 203                 cache_info.ic_conf.cc_line,
 204                 cache_info.ic_conf.cc_shift);
 205         printk("        wt %d sh %d cst %d hv %d\n",
 206                 cache_info.ic_conf.cc_wt,
 207                 cache_info.ic_conf.cc_sh,
 208                 cache_info.ic_conf.cc_cst,
 209                 cache_info.ic_conf.cc_hv);
 210
 211         printk("D-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
 212                 cache_info.dt_conf.tc_sh,
 213                 cache_info.dt_conf.tc_page,
 214                 cache_info.dt_conf.tc_cst,
 215                 cache_info.dt_conf.tc_aid,
 216                 cache_info.dt_conf.tc_sr);
 217
 218         printk("I-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
 219                 cache_info.it_conf.tc_sh,
 220                 cache_info.it_conf.tc_page,
 221                 cache_info.it_conf.tc_cst,
 222                 cache_info.it_conf.tc_aid,
 223                 cache_info.it_conf.tc_sr);
 224 #endif
 225
 226         split_tlb = 0;
 227         if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
 228                 if (cache_info.dt_conf.tc_sh == 2)
 229                         printk(KERN_WARNING "Unexpected TLB configuration. "
 230                         "Will flush I/D separately (could be optimized).\n");
 231
 232                 split_tlb = 1;
 233         }
 234
 235         /* "New and Improved" version from Jim Hull
 236          *      (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
 237          * The following CAFL_STRIDE is an optimized version, see
 238          * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
 239          * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
 240          */
 241 #define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
 242         dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
 243         icache_stride = CAFL_STRIDE(cache_info.ic_conf);
 244 #undef CAFL_STRIDE
 245
 246 #ifndef CONFIG_PA20
 247         if (pdc_btlb_info(&btlb_info) < 0) {
 248                 memset(&btlb_info, 0, sizeof btlb_info);
 249         }
 250 #endif
 251
 252         if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
 253                                                 PDC_MODEL_NVA_UNSUPPORTED) {
 254                 printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
 255 #if 0
 256                 panic("SMP kernel required to avoid non-equivalent aliasing");
 257 #endif
 258         }
 259 }
 260
 261 void __init disable_sr_hashing(void)
 262 {
 263         int srhash_type, retval;
 264         unsigned long space_bits;
 265
 266         switch (boot_cpu_data.cpu_type) {
 267         case pcx: /* We shouldn't get this far.  setup.c should prevent it. */
 268                 BUG();
 269                 return;
 270
 271         case pcxs:
 272         case pcxt:
 273         case pcxt_:
 274                 srhash_type = SRHASH_PCXST;
 275                 break;
 276
 277         case pcxl:
 278                 srhash_type = SRHASH_PCXL;
 279                 break;
 280
 281         case pcxl2: /* pcxl2 doesn't support space register hashing */
 282                 return;
 283
 284         default: /* Currently all PA2.0 machines use the same ins. sequence */
 285                 srhash_type = SRHASH_PA20;
 286                 break;
 287         }
 288
 289         disable_sr_hashing_asm(srhash_type);
 290
 291         retval = pdc_spaceid_bits(&space_bits);
 292         /* If this procedure isn't implemented, don't panic. */
 293         if (retval < 0 && retval != PDC_BAD_OPTION)
 294                 panic("pdc_spaceid_bits call failed.\n");
 295         if (space_bits != 0)
 296                 panic("SpaceID hashing is still on!\n");
 297 }
 298
 299 static inline void
 300 __flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
 301                    unsigned long physaddr)
 302 {
 303         preempt_disable();
 304         flush_dcache_page_asm(physaddr, vmaddr);
 305         if (vma->vm_flags & VM_EXEC)
 306                 flush_icache_page_asm(physaddr, vmaddr);
 307         preempt_enable();
 308 }
 309
 310 static inline void
 311 __purge_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
 312                    unsigned long physaddr)
 313 {
 314         preempt_disable();
 315         purge_dcache_page_asm(physaddr, vmaddr);
 316         if (vma->vm_flags & VM_EXEC)
 317                 flush_icache_page_asm(physaddr, vmaddr);
 318         preempt_enable();
 319 }
 320
 321 void flush_dcache_page(struct page *page)
 322 {
 323         struct address_space *mapping = page_mapping_file(page);
 324         struct vm_area_struct *mpnt;
 325         unsigned long offset;
 326         unsigned long addr, old_addr = 0;
 327         unsigned long flags;
 328         pgoff_t pgoff;
 329
 330         if (mapping && !mapping_mapped(mapping)) {
 331                 set_bit(PG_dcache_dirty, &page->flags);
 332                 return;
 333         }
 334
 335         flush_kernel_dcache_page_addr(page_address(page));
 336
 337         if (!mapping)
 338                 return;
 339
 340         pgoff = page->index;
 341
 342         /* We have carefully arranged in arch_get_unmapped_area() that
 343          * *any* mappings of a file are always congruently mapped (whether
 344          * declared as MAP_PRIVATE or MAP_SHARED), so we only need
 345          * to flush one address here for them all to become coherent */
 346
 347         flush_dcache_mmap_lock_irqsave(mapping, flags);
 348         vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
 349                 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
 350                 addr = mpnt->vm_start + offset;
 351
 352                 /* The TLB is the engine of coherence on parisc: The
 353                  * CPU is entitled to speculate any page with a TLB
 354                  * mapping, so here we kill the mapping then flush the
 355                  * page along a special flush only alias mapping.
 356                  * This guarantees that the page is no-longer in the
 357                  * cache for any process and nor may it be
 358                  * speculatively read in (until the user or kernel
 359                  * specifically accesses it, of course) */
 360
 361                 flush_tlb_page(mpnt, addr);
 362                 if (old_addr == 0 || (old_addr & (SHM_COLOUR - 1))
 363                                       != (addr & (SHM_COLOUR - 1))) {
 364                         __flush_cache_page(mpnt, addr, page_to_phys(page));
 365                         if (parisc_requires_coherency() && old_addr)
 366                                 printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %pD\n", old_addr, addr, mpnt->vm_file);
 367                         old_addr = addr;
 368                 }
 369         }
 370         flush_dcache_mmap_unlock_irqrestore(mapping, flags);
 371 }
 372 EXPORT_SYMBOL(flush_dcache_page);
 373
 374 /* Defined in arch/parisc/kernel/pacache.S */
 375 EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
 376 EXPORT_SYMBOL(flush_data_cache_local);
 377 EXPORT_SYMBOL(flush_kernel_icache_range_asm);
 378
 379 #define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
 380 static unsigned long parisc_cache_flush_threshold __ro_after_init = FLUSH_THRESHOLD;
 381
 382 #define FLUSH_TLB_THRESHOLD (16*1024) /* 16 KiB minimum TLB threshold */
 383 static unsigned long parisc_tlb_flush_threshold __ro_after_init = ~0UL;
 384
 385 void __init parisc_setup_cache_timing(void)
 386 {
 387         unsigned long rangetime, alltime;
 388         unsigned long size;
 389         unsigned long threshold;
 390
 391         alltime = mfctl(16);
 392         flush_data_cache();
 393         alltime = mfctl(16) - alltime;
 394
 395         size = (unsigned long)(_end - _text);
 396         rangetime = mfctl(16);
 397         flush_kernel_dcache_range((unsigned long)_text, size);
 398         rangetime = mfctl(16) - rangetime;
 399
 400         printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
 401                 alltime, size, rangetime);
 402
 403         threshold = L1_CACHE_ALIGN(size * alltime / rangetime);
 404         if (threshold > cache_info.dc_size)
 405                 threshold = cache_info.dc_size;
 406         if (threshold)
 407                 parisc_cache_flush_threshold = threshold;
 408         printk(KERN_INFO "Cache flush threshold set to %lu KiB\n",
 409                 parisc_cache_flush_threshold/1024);
 410
 411         /* calculate TLB flush threshold */
 412
 413         /* On SMP machines, skip the TLB measure of kernel text which
 414          * has been mapped as huge pages. */
 415         if (num_online_cpus() > 1 && !parisc_requires_coherency()) {
 416                 threshold = max(cache_info.it_size, cache_info.dt_size);
 417                 threshold *= PAGE_SIZE;
 418                 threshold /= num_online_cpus();
 419                 goto set_tlb_threshold;
 420         }
 421
 422         size = (unsigned long)_end - (unsigned long)_text;
 423         rangetime = mfctl(16);
 424         flush_tlb_kernel_range((unsigned long)_text, (unsigned long)_end);
 425         rangetime = mfctl(16) - rangetime;
 426
 427         alltime = mfctl(16);
 428         flush_tlb_all();
 429         alltime = mfctl(16) - alltime;
 430
 431         printk(KERN_INFO "Whole TLB flush %lu cycles, Range flush %lu bytes %lu cycles\n",
 432                 alltime, size, rangetime);
 433
 434         threshold = PAGE_ALIGN((num_online_cpus() * size * alltime) / rangetime);
 435         printk(KERN_INFO "Calculated TLB flush threshold %lu KiB\n",
 436                 threshold/1024);
 437
 438 set_tlb_threshold:
 439         if (threshold > FLUSH_TLB_THRESHOLD)
 440                 parisc_tlb_flush_threshold = threshold;
 441         else
 442                 parisc_tlb_flush_threshold = FLUSH_TLB_THRESHOLD;
 443
 444         printk(KERN_INFO "TLB flush threshold set to %lu KiB\n",
 445                 parisc_tlb_flush_threshold/1024);
 446 }
 447
 448 extern void purge_kernel_dcache_page_asm(unsigned long);
 449 extern void clear_user_page_asm(void *, unsigned long);
 450 extern void copy_user_page_asm(void *, void *, unsigned long);
 451
 452 void flush_kernel_dcache_page_addr(void *addr)
 453 {
 454         unsigned long flags;
 455
 456         flush_kernel_dcache_page_asm(addr);
 457         purge_tlb_start(flags);
 458         pdtlb_kernel(addr);
 459         purge_tlb_end(flags);
 460 }
 461 EXPORT_SYMBOL(flush_kernel_dcache_page_addr);
 462
 463 void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
 464         struct page *pg)
 465 {
 466        /* Copy using kernel mapping.  No coherency is needed (all in
 467           kunmap) for the `to' page.  However, the `from' page needs to
 468           be flushed through a mapping equivalent to the user mapping
 469           before it can be accessed through the kernel mapping. */
 470         preempt_disable();
 471         flush_dcache_page_asm(__pa(vfrom), vaddr);
 472         copy_page_asm(vto, vfrom);
 473         preempt_enable();
 474 }
 475 EXPORT_SYMBOL(copy_user_page);
 476
 477 /* __flush_tlb_range()
 478  *
 479  * returns 1 if all TLBs were flushed.
 480  */
 481 int __flush_tlb_range(unsigned long sid, unsigned long start,
 482                       unsigned long end)
 483 {
 484         unsigned long flags;
 485
 486         if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
 487             end - start >= parisc_tlb_flush_threshold) {
 488                 flush_tlb_all();
 489                 return 1;
 490         }
 491
 492         /* Purge TLB entries for small ranges using the pdtlb and
 493            pitlb instructions.  These instructions execute locally
 494            but cause a purge request to be broadcast to other TLBs.  */
 495         while (start < end) {
 496                 purge_tlb_start(flags);
 497                 mtsp(sid, 1);
 498                 pdtlb(start);
 499                 pitlb(start);
 500                 purge_tlb_end(flags);
 501                 start += PAGE_SIZE;
 502         }
 503         return 0;
 504 }
 505
 506 static void cacheflush_h_tmp_function(void *dummy)
 507 {
 508         flush_cache_all_local();
 509 }
 510
 511 void flush_cache_all(void)
 512 {
 513         on_each_cpu(cacheflush_h_tmp_function, NULL, 1);
 514 }
 515
 516 static inline unsigned long mm_total_size(struct mm_struct *mm)
 517 {
 518         struct vm_area_struct *vma;
 519         unsigned long usize = 0;
 520
 521         for (vma = mm->mmap; vma; vma = vma->vm_next)
 522                 usize += vma->vm_end - vma->vm_start;
 523         return usize;
 524 }
 525
 526 static inline pte_t *get_ptep(pgd_t *pgd, unsigned long addr)
 527 {
 528         pte_t *ptep = NULL;
 529
 530         if (!pgd_none(*pgd)) {
 531                 p4d_t *p4d = p4d_offset(pgd, addr);
 532                 if (!p4d_none(*p4d)) {
 533                         pud_t *pud = pud_offset(p4d, addr);
 534                         if (!pud_none(*pud)) {
 535                                 pmd_t *pmd = pmd_offset(pud, addr);
 536                                 if (!pmd_none(*pmd))
 537                                         ptep = pte_offset_map(pmd, addr);
 538                         }
 539                 }
 540         }
 541         return ptep;
 542 }
 543
 544 void flush_cache_mm(struct mm_struct *mm)
 545 {
 546         struct vm_area_struct *vma;
 547         pgd_t *pgd;
 548
 549         /* Flushing the whole cache on each cpu takes forever on
 550            rp3440, etc.  So, avoid it if the mm isn't too big.  */
 551         if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
 552             mm_total_size(mm) >= parisc_cache_flush_threshold) {
 553                 if (mm->context)
 554                         flush_tlb_all();
 555                 flush_cache_all();
 556                 return;
 557         }
 558
 559         if (mm->context == mfsp(3)) {
 560                 for (vma = mm->mmap; vma; vma = vma->vm_next) {
 561                         flush_user_dcache_range_asm(vma->vm_start, vma->vm_end);
 562                         if (vma->vm_flags & VM_EXEC)
 563                                 flush_user_icache_range_asm(vma->vm_start, vma->vm_end);
 564                         flush_tlb_range(vma, vma->vm_start, vma->vm_end);
 565                 }
 566                 return;
 567         }
 568
 569         pgd = mm->pgd;
 570         for (vma = mm->mmap; vma; vma = vma->vm_next) {
 571                 unsigned long addr;
 572
 573                 for (addr = vma->vm_start; addr < vma->vm_end;
 574                      addr += PAGE_SIZE) {
 575                         unsigned long pfn;
 576                         pte_t *ptep = get_ptep(pgd, addr);
 577                         if (!ptep)
 578                                 continue;
 579                         pfn = pte_pfn(*ptep);
 580                         if (!pfn_valid(pfn))
 581                                 continue;
 582                         if (unlikely(mm->context)) {
 583                                 flush_tlb_page(vma, addr);
 584                                 __flush_cache_page(vma, addr, PFN_PHYS(pfn));
 585                         } else {
 586                                 __purge_cache_page(vma, addr, PFN_PHYS(pfn));
 587                         }
 588                 }
 589         }
 590 }
 591
 592 void flush_cache_range(struct vm_area_struct *vma,
 593                 unsigned long start, unsigned long end)
 594 {
 595         pgd_t *pgd;
 596         unsigned long addr;
 597
 598         if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
 599             end - start >= parisc_cache_flush_threshold) {
 600                 if (vma->vm_mm->context)
 601                         flush_tlb_range(vma, start, end);
 602                 flush_cache_all();
 603                 return;
 604         }
 605
 606         if (vma->vm_mm->context == mfsp(3)) {
 607                 flush_user_dcache_range_asm(start, end);
 608                 if (vma->vm_flags & VM_EXEC)
 609                         flush_user_icache_range_asm(start, end);
 610                 flush_tlb_range(vma, start, end);
 611                 return;
 612         }
 613
 614         pgd = vma->vm_mm->pgd;
 615         for (addr = vma->vm_start; addr < vma->vm_end; addr += PAGE_SIZE) {
 616                 unsigned long pfn;
 617                 pte_t *ptep = get_ptep(pgd, addr);
 618                 if (!ptep)
 619                         continue;
 620                 pfn = pte_pfn(*ptep);
 621                 if (pfn_valid(pfn)) {
 622                         if (unlikely(vma->vm_mm->context)) {
 623                                 flush_tlb_page(vma, addr);
 624                                 __flush_cache_page(vma, addr, PFN_PHYS(pfn));
 625                         } else {
 626                                 __purge_cache_page(vma, addr, PFN_PHYS(pfn));
 627                         }
 628                 }
 629         }
 630 }
 631
 632 void
 633 flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
 634 {
 635         if (pfn_valid(pfn)) {
 636                 if (likely(vma->vm_mm->context)) {
 637                         flush_tlb_page(vma, vmaddr);
 638                         __flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
 639                 } else {
 640                         __purge_cache_page(vma, vmaddr, PFN_PHYS(pfn));
 641                 }
 642         }
 643 }
 644
 645 void flush_kernel_vmap_range(void *vaddr, int size)
 646 {
 647         unsigned long start = (unsigned long)vaddr;
 648         unsigned long end = start + size;
 649
 650         if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
 651             (unsigned long)size >= parisc_cache_flush_threshold) {
 652                 flush_tlb_kernel_range(start, end);
 653                 flush_data_cache();
 654                 return;
 655         }
 656
 657         flush_kernel_dcache_range_asm(start, end);
 658         flush_tlb_kernel_range(start, end);
 659 }
 660 EXPORT_SYMBOL(flush_kernel_vmap_range);
 661
 662 void invalidate_kernel_vmap_range(void *vaddr, int size)
 663 {
 664         unsigned long start = (unsigned long)vaddr;
 665         unsigned long end = start + size;
 666
 667         if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
 668             (unsigned long)size >= parisc_cache_flush_threshold) {
 669                 flush_tlb_kernel_range(start, end);
 670                 flush_data_cache();
 671                 return;
 672         }
 673
 674         purge_kernel_dcache_range_asm(start, end);
 675         flush_tlb_kernel_range(start, end);
 676 }
 677 EXPORT_SYMBOL(invalidate_kernel_vmap_range);