2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
7 * Copyright (C) 1999 SuSE GmbH Nuernberg
8 * Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
10 * Cache and TLB management
14 #include <linux/init.h>
15 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/seq_file.h>
19 #include <linux/pagemap.h>
20 #include <linux/sched.h>
21 #include <linux/sched/mm.h>
23 #include <asm/cache.h>
24 #include <asm/cacheflush.h>
25 #include <asm/tlbflush.h>
27 #include <asm/processor.h>
28 #include <asm/sections.h>
29 #include <asm/shmparam.h>
31 int split_tlb __ro_after_init;
32 int dcache_stride __ro_after_init;
33 int icache_stride __ro_after_init;
34 EXPORT_SYMBOL(dcache_stride);
36 void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
37 EXPORT_SYMBOL(flush_dcache_page_asm);
38 void purge_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
39 void flush_icache_page_asm(unsigned long phys_addr, unsigned long vaddr);
42 /* On some machines (i.e., ones with the Merced bus), there can be
43 * only a single PxTLB broadcast at a time; this must be guaranteed
44 * by software. We need a spinlock around all TLB flushes to ensure
47 DEFINE_SPINLOCK(pa_tlb_flush_lock);
49 #if defined(CONFIG_64BIT) && defined(CONFIG_SMP)
50 int pa_serialize_tlb_flushes __ro_after_init;
53 struct pdc_cache_info cache_info __ro_after_init;
55 static struct pdc_btlb_info btlb_info __ro_after_init;
60 flush_data_cache(void)
62 on_each_cpu(flush_data_cache_local, NULL, 1);
65 flush_instruction_cache(void)
67 on_each_cpu(flush_instruction_cache_local, NULL, 1);
72 flush_cache_all_local(void)
74 flush_instruction_cache_local(NULL);
75 flush_data_cache_local(NULL);
77 EXPORT_SYMBOL(flush_cache_all_local);
79 /* Virtual address of pfn. */
80 #define pfn_va(pfn) __va(PFN_PHYS(pfn))
83 __update_cache(pte_t pte)
85 unsigned long pfn = pte_pfn(pte);
88 /* We don't have pte special. As a result, we can be called with
89 an invalid pfn and we don't need to flush the kernel dcache page.
90 This occurs with FireGL card in C8000. */
94 page = pfn_to_page(pfn);
95 if (page_mapping_file(page) &&
96 test_bit(PG_dcache_dirty, &page->flags)) {
97 flush_kernel_dcache_page_addr(pfn_va(pfn));
98 clear_bit(PG_dcache_dirty, &page->flags);
99 } else if (parisc_requires_coherency())
100 flush_kernel_dcache_page_addr(pfn_va(pfn));
104 show_cache_info(struct seq_file *m)
108 seq_printf(m, "I-cache\t\t: %ld KB\n",
109 cache_info.ic_size/1024 );
110 if (cache_info.dc_loop != 1)
111 snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
112 seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n",
113 cache_info.dc_size/1024,
114 (cache_info.dc_conf.cc_wt ? "WT":"WB"),
115 (cache_info.dc_conf.cc_sh ? ", shared I/D":""),
116 ((cache_info.dc_loop == 1) ? "direct mapped" : buf));
117 seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
120 cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
124 /* BTLB - Block TLB */
125 if (btlb_info.max_size==0) {
126 seq_printf(m, "BTLB\t\t: not supported\n" );
129 "BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
130 "BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
131 "BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
132 btlb_info.max_size, (int)4096,
133 btlb_info.max_size>>8,
134 btlb_info.fixed_range_info.num_i,
135 btlb_info.fixed_range_info.num_d,
136 btlb_info.fixed_range_info.num_comb,
137 btlb_info.variable_range_info.num_i,
138 btlb_info.variable_range_info.num_d,
139 btlb_info.variable_range_info.num_comb
146 parisc_cache_init(void)
148 if (pdc_cache_info(&cache_info) < 0)
149 panic("parisc_cache_init: pdc_cache_info failed");
152 printk("ic_size %lx dc_size %lx it_size %lx\n",
157 printk("DC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
159 cache_info.dc_stride,
163 printk("dc_conf = 0x%lx alias %d blk %d line %d shift %d\n",
164 *(unsigned long *) (&cache_info.dc_conf),
165 cache_info.dc_conf.cc_alias,
166 cache_info.dc_conf.cc_block,
167 cache_info.dc_conf.cc_line,
168 cache_info.dc_conf.cc_shift);
169 printk(" wt %d sh %d cst %d hv %d\n",
170 cache_info.dc_conf.cc_wt,
171 cache_info.dc_conf.cc_sh,
172 cache_info.dc_conf.cc_cst,
173 cache_info.dc_conf.cc_hv);
175 printk("IC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
177 cache_info.ic_stride,
181 printk("IT base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
182 cache_info.it_sp_base,
183 cache_info.it_sp_stride,
184 cache_info.it_sp_count,
186 cache_info.it_off_base,
187 cache_info.it_off_stride,
188 cache_info.it_off_count);
190 printk("DT base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n",
191 cache_info.dt_sp_base,
192 cache_info.dt_sp_stride,
193 cache_info.dt_sp_count,
195 cache_info.dt_off_base,
196 cache_info.dt_off_stride,
197 cache_info.dt_off_count);
199 printk("ic_conf = 0x%lx alias %d blk %d line %d shift %d\n",
200 *(unsigned long *) (&cache_info.ic_conf),
201 cache_info.ic_conf.cc_alias,
202 cache_info.ic_conf.cc_block,
203 cache_info.ic_conf.cc_line,
204 cache_info.ic_conf.cc_shift);
205 printk(" wt %d sh %d cst %d hv %d\n",
206 cache_info.ic_conf.cc_wt,
207 cache_info.ic_conf.cc_sh,
208 cache_info.ic_conf.cc_cst,
209 cache_info.ic_conf.cc_hv);
211 printk("D-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
212 cache_info.dt_conf.tc_sh,
213 cache_info.dt_conf.tc_page,
214 cache_info.dt_conf.tc_cst,
215 cache_info.dt_conf.tc_aid,
216 cache_info.dt_conf.tc_sr);
218 printk("I-TLB conf: sh %d page %d cst %d aid %d sr %d\n",
219 cache_info.it_conf.tc_sh,
220 cache_info.it_conf.tc_page,
221 cache_info.it_conf.tc_cst,
222 cache_info.it_conf.tc_aid,
223 cache_info.it_conf.tc_sr);
227 if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
228 if (cache_info.dt_conf.tc_sh == 2)
229 printk(KERN_WARNING "Unexpected TLB configuration. "
230 "Will flush I/D separately (could be optimized).\n");
235 /* "New and Improved" version from Jim Hull
236 * (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
237 * The following CAFL_STRIDE is an optimized version, see
238 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
239 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
241 #define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
242 dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
243 icache_stride = CAFL_STRIDE(cache_info.ic_conf);
247 if (pdc_btlb_info(&btlb_info) < 0) {
248 memset(&btlb_info, 0, sizeof btlb_info);
252 if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
253 PDC_MODEL_NVA_UNSUPPORTED) {
254 printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
256 panic("SMP kernel required to avoid non-equivalent aliasing");
261 void __init disable_sr_hashing(void)
263 int srhash_type, retval;
264 unsigned long space_bits;
266 switch (boot_cpu_data.cpu_type) {
267 case pcx: /* We shouldn't get this far. setup.c should prevent it. */
274 srhash_type = SRHASH_PCXST;
278 srhash_type = SRHASH_PCXL;
281 case pcxl2: /* pcxl2 doesn't support space register hashing */
284 default: /* Currently all PA2.0 machines use the same ins. sequence */
285 srhash_type = SRHASH_PA20;
289 disable_sr_hashing_asm(srhash_type);
291 retval = pdc_spaceid_bits(&space_bits);
292 /* If this procedure isn't implemented, don't panic. */
293 if (retval < 0 && retval != PDC_BAD_OPTION)
294 panic("pdc_spaceid_bits call failed.\n");
296 panic("SpaceID hashing is still on!\n");
300 __flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
301 unsigned long physaddr)
304 flush_dcache_page_asm(physaddr, vmaddr);
305 if (vma->vm_flags & VM_EXEC)
306 flush_icache_page_asm(physaddr, vmaddr);
311 __purge_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
312 unsigned long physaddr)
315 purge_dcache_page_asm(physaddr, vmaddr);
316 if (vma->vm_flags & VM_EXEC)
317 flush_icache_page_asm(physaddr, vmaddr);
321 void flush_dcache_page(struct page *page)
323 struct address_space *mapping = page_mapping_file(page);
324 struct vm_area_struct *mpnt;
325 unsigned long offset;
326 unsigned long addr, old_addr = 0;
329 if (mapping && !mapping_mapped(mapping)) {
330 set_bit(PG_dcache_dirty, &page->flags);
334 flush_kernel_dcache_page_addr(page_address(page));
341 /* We have carefully arranged in arch_get_unmapped_area() that
342 * *any* mappings of a file are always congruently mapped (whether
343 * declared as MAP_PRIVATE or MAP_SHARED), so we only need
344 * to flush one address here for them all to become coherent */
346 flush_dcache_mmap_lock(mapping);
347 vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
348 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
349 addr = mpnt->vm_start + offset;
351 /* The TLB is the engine of coherence on parisc: The
352 * CPU is entitled to speculate any page with a TLB
353 * mapping, so here we kill the mapping then flush the
354 * page along a special flush only alias mapping.
355 * This guarantees that the page is no-longer in the
356 * cache for any process and nor may it be
357 * speculatively read in (until the user or kernel
358 * specifically accesses it, of course) */
360 flush_tlb_page(mpnt, addr);
361 if (old_addr == 0 || (old_addr & (SHM_COLOUR - 1))
362 != (addr & (SHM_COLOUR - 1))) {
363 __flush_cache_page(mpnt, addr, page_to_phys(page));
364 if (parisc_requires_coherency() && old_addr)
365 printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %pD\n", old_addr, addr, mpnt->vm_file);
369 flush_dcache_mmap_unlock(mapping);
371 EXPORT_SYMBOL(flush_dcache_page);
373 /* Defined in arch/parisc/kernel/pacache.S */
374 EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
375 EXPORT_SYMBOL(flush_data_cache_local);
376 EXPORT_SYMBOL(flush_kernel_icache_range_asm);
378 #define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
379 static unsigned long parisc_cache_flush_threshold __ro_after_init = FLUSH_THRESHOLD;
381 #define FLUSH_TLB_THRESHOLD (16*1024) /* 16 KiB minimum TLB threshold */
382 static unsigned long parisc_tlb_flush_threshold __ro_after_init = ~0UL;
384 void __init parisc_setup_cache_timing(void)
386 unsigned long rangetime, alltime;
388 unsigned long threshold;
392 alltime = mfctl(16) - alltime;
394 size = (unsigned long)(_end - _text);
395 rangetime = mfctl(16);
396 flush_kernel_dcache_range((unsigned long)_text, size);
397 rangetime = mfctl(16) - rangetime;
399 printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
400 alltime, size, rangetime);
402 threshold = L1_CACHE_ALIGN(size * alltime / rangetime);
403 if (threshold > cache_info.dc_size)
404 threshold = cache_info.dc_size;
406 parisc_cache_flush_threshold = threshold;
407 printk(KERN_INFO "Cache flush threshold set to %lu KiB\n",
408 parisc_cache_flush_threshold/1024);
410 /* calculate TLB flush threshold */
412 /* On SMP machines, skip the TLB measure of kernel text which
413 * has been mapped as huge pages. */
414 if (num_online_cpus() > 1 && !parisc_requires_coherency()) {
415 threshold = max(cache_info.it_size, cache_info.dt_size);
416 threshold *= PAGE_SIZE;
417 threshold /= num_online_cpus();
418 goto set_tlb_threshold;
421 size = (unsigned long)_end - (unsigned long)_text;
422 rangetime = mfctl(16);
423 flush_tlb_kernel_range((unsigned long)_text, (unsigned long)_end);
424 rangetime = mfctl(16) - rangetime;
428 alltime = mfctl(16) - alltime;
430 printk(KERN_INFO "Whole TLB flush %lu cycles, Range flush %lu bytes %lu cycles\n",
431 alltime, size, rangetime);
433 threshold = PAGE_ALIGN((num_online_cpus() * size * alltime) / rangetime);
434 printk(KERN_INFO "Calculated TLB flush threshold %lu KiB\n",
438 if (threshold > FLUSH_TLB_THRESHOLD)
439 parisc_tlb_flush_threshold = threshold;
441 parisc_tlb_flush_threshold = FLUSH_TLB_THRESHOLD;
443 printk(KERN_INFO "TLB flush threshold set to %lu KiB\n",
444 parisc_tlb_flush_threshold/1024);
447 extern void purge_kernel_dcache_page_asm(unsigned long);
448 extern void clear_user_page_asm(void *, unsigned long);
449 extern void copy_user_page_asm(void *, void *, unsigned long);
451 void flush_kernel_dcache_page_addr(void *addr)
455 flush_kernel_dcache_page_asm(addr);
456 purge_tlb_start(flags);
458 purge_tlb_end(flags);
460 EXPORT_SYMBOL(flush_kernel_dcache_page_addr);
462 void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
465 /* Copy using kernel mapping. No coherency is needed (all in
466 kunmap) for the `to' page. However, the `from' page needs to
467 be flushed through a mapping equivalent to the user mapping
468 before it can be accessed through the kernel mapping. */
470 flush_dcache_page_asm(__pa(vfrom), vaddr);
471 copy_page_asm(vto, vfrom);
474 EXPORT_SYMBOL(copy_user_page);
476 /* __flush_tlb_range()
478 * returns 1 if all TLBs were flushed.
480 int __flush_tlb_range(unsigned long sid, unsigned long start,
485 if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
486 end - start >= parisc_tlb_flush_threshold) {
491 /* Purge TLB entries for small ranges using the pdtlb and
492 pitlb instructions. These instructions execute locally
493 but cause a purge request to be broadcast to other TLBs. */
494 while (start < end) {
495 purge_tlb_start(flags);
499 purge_tlb_end(flags);
505 static void cacheflush_h_tmp_function(void *dummy)
507 flush_cache_all_local();
510 void flush_cache_all(void)
512 on_each_cpu(cacheflush_h_tmp_function, NULL, 1);
515 static inline unsigned long mm_total_size(struct mm_struct *mm)
517 struct vm_area_struct *vma;
518 unsigned long usize = 0;
520 for (vma = mm->mmap; vma; vma = vma->vm_next)
521 usize += vma->vm_end - vma->vm_start;
525 static inline pte_t *get_ptep(pgd_t *pgd, unsigned long addr)
529 if (!pgd_none(*pgd)) {
530 p4d_t *p4d = p4d_offset(pgd, addr);
531 if (!p4d_none(*p4d)) {
532 pud_t *pud = pud_offset(p4d, addr);
533 if (!pud_none(*pud)) {
534 pmd_t *pmd = pmd_offset(pud, addr);
536 ptep = pte_offset_map(pmd, addr);
543 void flush_cache_mm(struct mm_struct *mm)
545 struct vm_area_struct *vma;
548 /* Flushing the whole cache on each cpu takes forever on
549 rp3440, etc. So, avoid it if the mm isn't too big. */
550 if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
551 mm_total_size(mm) >= parisc_cache_flush_threshold) {
558 if (mm->context == mfsp(3)) {
559 for (vma = mm->mmap; vma; vma = vma->vm_next) {
560 flush_user_dcache_range_asm(vma->vm_start, vma->vm_end);
561 if (vma->vm_flags & VM_EXEC)
562 flush_user_icache_range_asm(vma->vm_start, vma->vm_end);
563 flush_tlb_range(vma, vma->vm_start, vma->vm_end);
569 for (vma = mm->mmap; vma; vma = vma->vm_next) {
572 for (addr = vma->vm_start; addr < vma->vm_end;
575 pte_t *ptep = get_ptep(pgd, addr);
578 pfn = pte_pfn(*ptep);
581 if (unlikely(mm->context)) {
582 flush_tlb_page(vma, addr);
583 __flush_cache_page(vma, addr, PFN_PHYS(pfn));
585 __purge_cache_page(vma, addr, PFN_PHYS(pfn));
591 void flush_cache_range(struct vm_area_struct *vma,
592 unsigned long start, unsigned long end)
597 if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
598 end - start >= parisc_cache_flush_threshold) {
599 if (vma->vm_mm->context)
600 flush_tlb_range(vma, start, end);
605 if (vma->vm_mm->context == mfsp(3)) {
606 flush_user_dcache_range_asm(start, end);
607 if (vma->vm_flags & VM_EXEC)
608 flush_user_icache_range_asm(start, end);
609 flush_tlb_range(vma, start, end);
613 pgd = vma->vm_mm->pgd;
614 for (addr = vma->vm_start; addr < vma->vm_end; addr += PAGE_SIZE) {
616 pte_t *ptep = get_ptep(pgd, addr);
619 pfn = pte_pfn(*ptep);
620 if (pfn_valid(pfn)) {
621 if (unlikely(vma->vm_mm->context)) {
622 flush_tlb_page(vma, addr);
623 __flush_cache_page(vma, addr, PFN_PHYS(pfn));
625 __purge_cache_page(vma, addr, PFN_PHYS(pfn));
632 flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
634 if (pfn_valid(pfn)) {
635 if (likely(vma->vm_mm->context)) {
636 flush_tlb_page(vma, vmaddr);
637 __flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
639 __purge_cache_page(vma, vmaddr, PFN_PHYS(pfn));
644 void flush_kernel_vmap_range(void *vaddr, int size)
646 unsigned long start = (unsigned long)vaddr;
647 unsigned long end = start + size;
649 if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
650 (unsigned long)size >= parisc_cache_flush_threshold) {
651 flush_tlb_kernel_range(start, end);
656 flush_kernel_dcache_range_asm(start, end);
657 flush_tlb_kernel_range(start, end);
659 EXPORT_SYMBOL(flush_kernel_vmap_range);
661 void invalidate_kernel_vmap_range(void *vaddr, int size)
663 unsigned long start = (unsigned long)vaddr;
664 unsigned long end = start + size;
666 if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
667 (unsigned long)size >= parisc_cache_flush_threshold) {
668 flush_tlb_kernel_range(start, end);
673 purge_kernel_dcache_range_asm(start, end);
674 flush_tlb_kernel_range(start, end);
676 EXPORT_SYMBOL(invalidate_kernel_vmap_range);