1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Linux architectural port borrowing liberally from similar works of
6 * others. All original copyrights apply as per the original source
9 * Modifications for the OpenRISC architecture:
10 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
13 * This file handles the architecture-dependent parts of initialization
16 #include <linux/errno.h>
17 #include <linux/sched.h>
18 #include <linux/kernel.h>
20 #include <linux/stddef.h>
21 #include <linux/unistd.h>
22 #include <linux/ptrace.h>
23 #include <linux/slab.h>
24 #include <linux/tty.h>
25 #include <linux/ioport.h>
26 #include <linux/delay.h>
27 #include <linux/console.h>
28 #include <linux/init.h>
29 #include <linux/memblock.h>
30 #include <linux/seq_file.h>
31 #include <linux/serial.h>
32 #include <linux/initrd.h>
33 #include <linux/of_fdt.h>
35 #include <linux/device.h>
37 #include <asm/sections.h>
38 #include <asm/pgtable.h>
39 #include <asm/types.h>
40 #include <asm/setup.h>
42 #include <asm/cpuinfo.h>
43 #include <asm/delay.h>
47 static void __init setup_memory(void)
49 unsigned long ram_start_pfn;
50 unsigned long ram_end_pfn;
51 phys_addr_t memory_start, memory_end;
52 struct memblock_region *region;
54 memory_end = memory_start = 0;
56 /* Find main memory where is the kernel, we assume its the only one */
57 for_each_memblock(memory, region) {
58 memory_start = region->base;
59 memory_end = region->base + region->size;
60 printk(KERN_INFO "%s: Memory: 0x%x-0x%x\n", __func__,
61 memory_start, memory_end);
68 ram_start_pfn = PFN_UP(memory_start);
69 ram_end_pfn = PFN_DOWN(memblock_end_of_DRAM());
71 /* setup bootmem globals (we use no_bootmem, but mm still depends on this) */
72 min_low_pfn = ram_start_pfn;
73 max_low_pfn = ram_end_pfn;
74 max_pfn = ram_end_pfn;
77 * initialize the boot-time allocator (with low memory only).
79 * This makes the memory from the end of the kernel to the end of
82 memblock_reserve(__pa(_stext), _end - _stext);
84 early_init_fdt_reserve_self();
85 early_init_fdt_scan_reserved_mem();
90 struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS];
92 static void print_cpuinfo(void)
94 unsigned long upr = mfspr(SPR_UPR);
95 unsigned long vr = mfspr(SPR_VR);
97 unsigned int revision;
98 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
100 version = (vr & SPR_VR_VER) >> 24;
101 revision = (vr & SPR_VR_REV);
103 printk(KERN_INFO "CPU: OpenRISC-%x (revision %d) @%d MHz\n",
104 version, revision, cpuinfo->clock_frequency / 1000000);
106 if (!(upr & SPR_UPR_UP)) {
108 "-- no UPR register... unable to detect configuration\n");
112 if (upr & SPR_UPR_DCP)
114 "-- dcache: %4d bytes total, %2d bytes/line, %d way(s)\n",
115 cpuinfo->dcache_size, cpuinfo->dcache_block_size,
116 cpuinfo->dcache_ways);
118 printk(KERN_INFO "-- dcache disabled\n");
119 if (upr & SPR_UPR_ICP)
121 "-- icache: %4d bytes total, %2d bytes/line, %d way(s)\n",
122 cpuinfo->icache_size, cpuinfo->icache_block_size,
123 cpuinfo->icache_ways);
125 printk(KERN_INFO "-- icache disabled\n");
127 if (upr & SPR_UPR_DMP)
128 printk(KERN_INFO "-- dmmu: %4d entries, %lu way(s)\n",
129 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
130 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
131 if (upr & SPR_UPR_IMP)
132 printk(KERN_INFO "-- immu: %4d entries, %lu way(s)\n",
133 1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
134 1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW));
136 printk(KERN_INFO "-- additional features:\n");
137 if (upr & SPR_UPR_DUP)
138 printk(KERN_INFO "-- debug unit\n");
139 if (upr & SPR_UPR_PCUP)
140 printk(KERN_INFO "-- performance counters\n");
141 if (upr & SPR_UPR_PMP)
142 printk(KERN_INFO "-- power management\n");
143 if (upr & SPR_UPR_PICP)
144 printk(KERN_INFO "-- PIC\n");
145 if (upr & SPR_UPR_TTP)
146 printk(KERN_INFO "-- timer\n");
147 if (upr & SPR_UPR_CUP)
148 printk(KERN_INFO "-- custom unit(s)\n");
151 static struct device_node *setup_find_cpu_node(int cpu)
154 struct device_node *cpun;
156 for_each_of_cpu_node(cpun) {
157 if (of_property_read_u32(cpun, "reg", &hwid))
166 void __init setup_cpuinfo(void)
168 struct device_node *cpu;
169 unsigned long iccfgr, dccfgr;
170 unsigned long cache_set_size;
171 int cpu_id = smp_processor_id();
172 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu_id];
174 cpu = setup_find_cpu_node(cpu_id);
176 panic("Couldn't find CPU%d in device tree...\n", cpu_id);
178 iccfgr = mfspr(SPR_ICCFGR);
179 cpuinfo->icache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
180 cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
181 cpuinfo->icache_block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
182 cpuinfo->icache_size =
183 cache_set_size * cpuinfo->icache_ways * cpuinfo->icache_block_size;
185 dccfgr = mfspr(SPR_DCCFGR);
186 cpuinfo->dcache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
187 cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
188 cpuinfo->dcache_block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
189 cpuinfo->dcache_size =
190 cache_set_size * cpuinfo->dcache_ways * cpuinfo->dcache_block_size;
192 if (of_property_read_u32(cpu, "clock-frequency",
193 &cpuinfo->clock_frequency)) {
195 "Device tree missing CPU 'clock-frequency' parameter."
196 "Assuming frequency 25MHZ"
197 "This is probably not what you want.");
200 cpuinfo->coreid = mfspr(SPR_COREID);
210 * Handles the pointer to the device tree that this kernel is to use
211 * for establishing the available platform devices.
213 * Falls back on built-in device tree in case null pointer is passed.
216 void __init or32_early_setup(void *fdt)
219 pr_info("FDT at %p\n", fdt);
222 pr_info("Compiled-in FDT at %p\n", fdt);
224 early_init_devtree(fdt);
227 static inline unsigned long extract_value_bits(unsigned long reg,
228 short bit_nr, short width)
230 return (reg >> bit_nr) & (0 << width);
233 static inline unsigned long extract_value(unsigned long reg, unsigned long mask)
235 while (!(mask & 0x1)) {
242 void __init detect_unit_config(unsigned long upr, unsigned long mask,
243 char *text, void (*func) (void))
254 printk("not present\n");
260 * Lightweight calibrate_delay implementation that calculates loops_per_jiffy
261 * from the clock frequency passed in via the device tree
265 void calibrate_delay(void)
268 struct device_node *cpu = setup_find_cpu_node(smp_processor_id());
270 val = of_get_property(cpu, "clock-frequency", NULL);
272 panic("no cpu 'clock-frequency' parameter in device tree");
273 loops_per_jiffy = *val / HZ;
274 pr_cont("%lu.%02lu BogoMIPS (lpj=%lu)\n",
275 loops_per_jiffy / (500000 / HZ),
276 (loops_per_jiffy / (5000 / HZ)) % 100, loops_per_jiffy);
281 void __init setup_arch(char **cmdline_p)
283 unflatten_and_copy_device_tree();
291 /* process 1's initial memory region is the kernel code/data */
292 init_mm.start_code = (unsigned long)_stext;
293 init_mm.end_code = (unsigned long)_etext;
294 init_mm.end_data = (unsigned long)_edata;
295 init_mm.brk = (unsigned long)_end;
297 #ifdef CONFIG_BLK_DEV_INITRD
298 initrd_start = (unsigned long)&__initrd_start;
299 initrd_end = (unsigned long)&__initrd_end;
300 if (initrd_start == initrd_end) {
304 initrd_below_start_ok = 1;
307 /* setup memblock allocator */
310 /* paging_init() sets up the MMU and marks all pages as reserved */
313 #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
315 conswitchp = &dummy_con;
318 *cmdline_p = boot_command_line;
320 printk(KERN_INFO "OpenRISC Linux -- http://openrisc.io\n");
323 static int show_cpuinfo(struct seq_file *m, void *v)
325 unsigned int vr, cpucfgr;
327 unsigned int version;
328 struct cpuinfo_or1k *cpuinfo = v;
331 cpucfgr = mfspr(SPR_CPUCFGR);
334 seq_printf(m, "processor\t\t: %d\n", cpuinfo->coreid);
336 if (vr & SPR_VR_UVRP) {
338 version = vr & SPR_VR2_VER;
339 avr = mfspr(SPR_AVR);
340 seq_printf(m, "cpu architecture\t: "
341 "OpenRISC 1000 (%d.%d-rev%d)\n",
345 seq_printf(m, "cpu implementation id\t: 0x%x\n",
346 (vr & SPR_VR2_CPUID) >> 24);
347 seq_printf(m, "cpu version\t\t: 0x%x\n", version);
349 version = (vr & SPR_VR_VER) >> 24;
350 seq_printf(m, "cpu\t\t\t: OpenRISC-%x\n", version);
351 seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV);
353 seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ);
354 seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache_size);
355 seq_printf(m, "dcache block size\t: %d bytes\n",
356 cpuinfo->dcache_block_size);
357 seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache_ways);
358 seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache_size);
359 seq_printf(m, "icache block size\t: %d bytes\n",
360 cpuinfo->icache_block_size);
361 seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache_ways);
362 seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n",
363 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
364 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
365 seq_printf(m, "dmmu\t\t\t: %d entries, %lu ways\n",
366 1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
367 1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW));
368 seq_printf(m, "bogomips\t\t: %lu.%02lu\n",
369 (loops_per_jiffy * HZ) / 500000,
370 ((loops_per_jiffy * HZ) / 5000) % 100);
372 seq_puts(m, "features\t\t: ");
373 seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OB32S ? "orbis32" : "");
374 seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OB64S ? "orbis64" : "");
375 seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OF32S ? "orfpx32" : "");
376 seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OF64S ? "orfpx64" : "");
377 seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OV64S ? "orvdx64" : "");
385 static void *c_start(struct seq_file *m, loff_t *pos)
387 *pos = cpumask_next(*pos - 1, cpu_online_mask);
388 if ((*pos) < nr_cpu_ids)
389 return &cpuinfo_or1k[*pos];
393 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
396 return c_start(m, pos);
399 static void c_stop(struct seq_file *m, void *v)
403 const struct seq_operations cpuinfo_op = {
407 .show = show_cpuinfo,